PI6ULS5V9306 PERICOM | Alldatasheet
Document overview
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Technical content
Features
2-bit bidirectional translator for SDA and SCL lines in mixed-mode I2C-bus applications Standard-mode, Fast-mode, and Fast-mode Plus I2C-bus and SMBus compatible Less than 1.5 ns maximum propagation delay to accommodate Standard mode and Fast mode I2C- bus devices and multiple masters Allows voltage level translation between: 0.9V V REF1 and 1.8 V, 2.5 V, 3.3 V or 5 V VREF2 1.2 V VREF1 and 1.8 V, 2.5 V, 3.3 V or 5 V VREF2 1.5 V VREF1 and 2.5 V, 3.3 V or 5 V VREF2 1.8 V VREF1 and 3.3 V or 5 V VREF2 2.5 V VREF1 and 5 V VREF2 3.3 V VREF1 and 5 V VREF2 Provides bidirectional voltage translation with no direction pin Low 3.5 ohm -state connection between input and output ports provides less signal distortion Open-drain I2C-bus I/O ports (SCL1, SDA1, SCL2 and SDA2) 5 V tolerant I2C-bus I/O ports to support mixed- mode signal operation High-impedance SCL1, SDA1, SCL2 and SDA2 pins for EN = LOW Lock-up free operation for isolation when EN = LOW Flow through pin out for ease of printed-circuit board trace routing ESD protection exceeds 4KV HBM per JESD22- A114 Package: TDFN2x3-8L, MSOP-8L,SOIC-8L
Description
The PI6ULS5V9306 is a dual bidirectional I 2C-bus and SMBus voltage-level translator with an enable (EN) input, and is operational from 1. 0 V to 3. 3 V (VREF1) and 1.8 V to 5.5 V(VREF2). The PI6ULS5V9306 allows bidirectional voltage translations between 1.0 V and 5 V without the use of a direction pin. The low ON -state resistance (Ron) of the switch allows connections to be made with minimal propagation delay . When EN is HIGH, the translator switch is on, and the SCL1 and SDA1 I/O are connected to the SCL2 and SDA2 I/O respectively, allowing bidirectional data flow between ports. When EN is LOW, the translator switch is off, and a high -impedance state exists between ports. The PI6ULS5V9306 is not a bus buffer that provides both level translation and physically isolates to ei ther side of the bus when both sides are connected. The PI6ULS5V9306 only isolates both sides when the device is disabled and provides vol tage level translation when active. The PI6ULS5V9306 can also be used to run two buses, one at 400 kHz operating frequency and the other at 100 kHz operating frequency. If the two buses are operating at different frequencies, the 100 kHz bus must be isolated when the 400 kHz operation of the other bus is required. If the master is running at 400 kHz, the maximum system operating frequency may be less than 400 kHz because of the delays added by the translator. As with the standard I 2C-bus system, pull -up resistors are required to provide the logic HIGH levels on the translator’s bus. The PI6ULS5V9306 has a standard open -collector configuration of the I 2C-bus. The size of these pull-up resistors depends on the system, but each side of the translator must have a pull -up resistor. The device is designed to work with Standard- mode, Fast-mode and Fast mode Plus I 2C-bus devices in addition to SMBus devices. When the SDA1 or SDA2 port is LOW, the clamp is in the ON -state and a low resistance connection exists between the SDA1 and SDA2 ports. When the higher voltage is on the SDA2 port , and the SDA2 port is HIGH , the voltage on the SDA1 port is limited to the voltage set by VREF1. When the SDA1 port is HIGH, the SDA2 port is pulled to the drain pull-up supply voltage (V DPU) by the pull -up resistors. This functionality allows a seamless translation between higher and lower voltages selected by the user without the need for directional control. The SCL1/SCL2 channel also functions as the SDA1/SDA2 channel. All channels have the same electrical characteristics and there is minimal deviation from one output to another in voltage or propagation delay. This is a benefit over discrete transistor voltage translation solutions, since the fabrication of the switch is symmetric al. The translator provides excellent ESD protection to lower voltage devices, and at the same time protects less ESD- resistant devices.
2015-08-0006 PT0451-5 8/18/15 PI6ULS5V9306 Dual bidirectional I2C-bus and SMBus voltage-level translator Pin Configuration MSOP-8L/SOIC-8L(Top View) TDFN2x3-8L(Top View) Pin Description Pin No Name Description
1 GND ground (0 V)
2 VREF1 low-voltage side reference supply voltage for SCL1 and SDA1
3 SCL1 serial clock, low-voltage side; connect to VREF1 through a pull-up resistor
4 SDA1 serial data, low-voltage side; connect to VREF1 through a pull-up resistor
5 SDA2 serial data, high-voltage side; connect to VREF2 through a pull-up resistor
6 SCL2 serial clock, high-voltage side; connect to VREF2 through a pull-up resistor
7 VREF2 high-voltage side reference supply voltage for SCL2 and SDA2
8 EN switch enable input; connect to VREF2 and pull-up through a high resistor
Figure.1Block Diagram EN Function H SCL1 = SCL2; SDA1 = SDA2 L disabled
2015-08-0006 PT0451-5 8/18/15 PI6ULS5V9306 Dual bidirectional I2C-bus and SMBus voltage-level translator Maximum Ratings Recommended operation conditions VCC = 2.7 V to 5.5 V; GND = 0 V; TA = -40 C to +85 C; unless otherwise specified Symbol Parameter Test Conditions Min. Typ. Max. Unit VI/O Voltage on an input/output pin SCL1, SDA1, SCL2, SDA2 0 - 5 V VREF1 Reference voltage (1) VREF1 0 - 5 V VREF2 Reference bias voltage (2) VREF2 0 - 5 V VI(EN) Input voltage on pin EN - 0 - 5 V I(pass) Pass switch current - - - 64 mA TA Ambient temperature - -40 - 85 oC TA = -40 C to +85 C; unless otherwise specified Parameter Description Test Conditions(1) Min Typ.(2) Max Unit Input and output SDAB and SCLB VIK input clamping voltage II = -18mA; VI(EN) = 0 V - - -1.2 V IIH HIGH-level input current VI = 5 V; VI(EN) = 0 V - - 5 µA Ci(EN) input capacitance on pin EN VI = 3 V or 0 V - 11 - pF Cio(off) off-state input/output capacitance (SCLn, SDAn) VO = 3 V or 0 V; VI(EN) = 0 V - 4 - pF Cio(on) on-state input/output capacitance (SCLn, SDAn) VO = 3 V or 0 V; VI(EN) = 3 V - 10.5 - pF Ron ON-state resistance(2) (SCLn, SDAn) VI = 0V; IO = 64mA VI(EN) = 3 V - 4.7 7.0 Ω VI(EN) = 1.5 V - 60 140 Ω VI = 2.4V; IO = 15mA VI(EN) = 4.5 V 1 6 15 Ω VI(EN) = 3 V 20 60 140 Ω VI = 1.7V; IO = 15mA VI(EN) = 2.3 V 20 60 140 Ω Notes: 1) All typical values are at TA = 25 ° C. 2) Measured by the voltage drop between the SCL1 and SCL2, or SDA1 and SDA2 terminals at the indicated current through the switc h. ON-state resistance is determined by the lowest voltage of the two terminals. Note: 1. Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. T his is a stress rating only and functional operation of the dev ice at these or any other condi tions above those i ndicated in the operational sec tions of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. The input and input/output negative voltage ratings may be exceeded if the input and input/output clamp current ratings are observed.
2015-08-0006 PT0451-5 8/18/15 PI6ULS5V9306 Dual bidirectional I2C-bus and SMBus voltage-level translator Dynamic characteristics TA = -40 C to +85 C; unless otherwise specified. Values guaranteed by design. Symbol Parameter Conditions CL = 50 pF CL = 30 pF CL = 15 pF Unit Min Max Min Max Min Max VI(EN) = 3.3 V; VIH = 3.3 V; VIL = 0 V; VM = 1.15 V tPLH LOW-to-HIGH propagation delay from (input) SCL2 or SDA2 to (output) SCL1 or SDA1 0 0.8 0 0.6 0 0.3 ns tPHL HIGH-to-LOW propagation delay from (input) SCL2 or SDA2 to (output) SCL1 or SDA1 0 1.2 0 1 0 0.5 ns VI(EN) = 2.5 V; VIH = 3.3 V; VIL = 0 V; VM = 0.75 V tPLH LOW-to-HIGH propagation delay from (input) SCL2 or SDA2 to (output) SCL1 or SDA1 0 1 0 0.7 0 0.4 ns tPHL HIGH-to-LOW propagation delay from (input) SCL2 or SDA2 to (output) SCL1 or SDA1 0 1.3 0 1 0 0.6 ns VI(EN) = 3.3 V; VIH = 2.3 V; VIL = 0 V; VT = 3.3 V; VM = 1.15 V; RL = 300 tPLH LOW-to-HIGH propagation delay ffrom (input) SCL1 orSDA1 to (output) SCL2 or SDA2 0 0.9 0 0.6 0 0.4 ns tPHL HIGH-to-LOW propagation delay from (input) SCL1 or SDA1 to (output) SCL2 or SDA2 0 1.4 0 1.1 0 0.7 ns VI(EN) = 2.5 V; VIH = 1.5 V; VIL = 0 V; VT = 2.5 V; VM = 0.75 V; RL = 300 tPLH LOW-to-HIGH propagation delay from (input) SCL1 orSDA1 to (output) SCL2 or SDA2 0 1 0 0.6 0 0.4 ns tPHL HIGH-to-LOW propagation delay from (input) SCL1 or SDA1 to (output) SCL2 or SDA2 0 1.3 0 1.3 0 0.8 ns Figure.2 Load Circuit for Outputs
2015-08-0006 PT0451-5 8/18/15 PI6ULS5V9306 Dual bidirectional I2C-bus and SMBus voltage-level translator Functional Description The PI6ULS5V9306 is a dual bidirectional I 2C-bus and SMBus voltage -level translator with an enable (EN) input, and is The PI6ULS5V9306 allows bidirectional voltage translations between 1.2 V and 5 V without the use of a direction pin. The low ON-state resistance (Ron) of the switch allows connections to be made with minimal propagation delay. When EN is HIGH, the translator sw itch is on, and the SCL1 and SDA1 I/O are connected to the SCL2 and SDA2 I/O respectively, allowing bidirectional data flow between ports. When EN is LOW, the translator switch i s off, and a high -impedance state exists between ports. The PI6ULS5V9306 is not a bus buffer that provide s both level translation and physically isolates to ei ther side of the bus when both sides are connected. The PI6ULS5V9306 only isolates both sides when the device is disabled and provides voltage level translation when active. The PI6ULS5V9306 can also be used to run two buses, one at 400 kHz operating frequency and the other at 100 kHz operating frequency. If the two buses are operating at different frequencies, the 100 kHz bus must be isolated when the 400 kHz operation of the other bus is required. If the master is running at 400 kHz, the maximum system operating frequency may be less than 400 kHz because of the delays added by the translator. As with the standard I 2C-bus system, pull -up resistors are required to provide the lo gic HIGH levels on the translator’s bus. The PI6ULS5V9306 has a standard open-collector configuration of the I2C-bus. The size of these pull -up resistors depends on the system, but each side of the translator must have a pull -up resistor. The device is des igned to work with Standard -mode, Fast - mode and Fast mode Plus I2C-bus devices in addition to SMBus devices. When the SDA1 or SDA2 port is LOW, the clamp is in the ON -state and a low resistance connection exists between the SDA1 and SDA2 ports. When the higher voltage is on the SDA2 port, and the SDA2 port is HIGH, the voltage on the SDA1 port is limited to the voltage set by VREF1. When the SDA1 port is HIGH, the SDA2 port is pulled to the drain pull-up supply voltage (VDPU) by the pull -up resistors. This functionality allows a seamless translation between higher and lower voltages selected by the user without the need for directional control. The SCL1/SCL2 channel also functions as the SDA1/SDA2 channel. All channels have the same electrical characteristics and there is minimal deviation from one output to another in voltage or propagation delay. This is a benefit over discrete transistor voltage translation solutions, since the fabrication of the switch is symmetrical. The translator provides excellent E SD protection to lower voltage devices, and at the same time protects less ESD - resistant devices.
Application Information
Figure.3 Typical Open Drain Application Circuit (Switch Always Enabled ) 0.1μF or 0.01μF
2015-08-0006 PT0451-5 8/18/15 PI6ULS5V9306 Dual bidirectional I2C-bus and SMBus voltage-level translator Figure.4 Typical Open Drain Application Circuit (Switch Enabled Control) Open Drain Application For the bidirectional clamping configuration (higher voltage to lower voltage or lower voltage to higher voltage), the EN input must be connected to VREF2 and both pins pulled to high-side VDPU through a pull-up resistor (typically 200 kΩ). This allows VREF2 to regulate the EN input. A filter capacitor on VREF2 is recommended. Figure.5 Typical push-pull Application Circuit (Switch Enabled Control) Push Pull Application If used in push-pull system, the pull-up resistors on REF side are also needed. The data must be unidirectional or the outputs must be 3-stateable and be controlled by some direction-control mechanism to prevent high-to-low contentions in either direction. 0.1μF or 0.01μF
Figure 6. Typical Open Drain Application Circuit The device would sink the total current from both pull-up resistors. I_sink=Ipass+I_2=I_1+I_2 . The same thing will happen when I2C master pull low the I2C bus. The I_sink should be limited to not larger than the tolerance of the I2C devices. In normal application , the VIL of external devices should always be larger than the VOL of PI6ULS5V9306. The value of PI6ULS5V9306’s VOL is determined by the pass through current and the low voltage added on the SDA,SCL pins. VREF1 is less than 1.8V, the VOL of REF1 side is a concern in system . the VOL of REF2 side can up to 0.1*VDPU=0.36V sometimes. The system designer must make sure this situation doesn’t happen. A limit for the VOL of REF2 side devices is required then.
2015-08-0006 PT0451-5 8/18/15 PI6ULS5V9306 Dual bidirectional I2C-bus and SMBus voltage-level translator The bellow table shows the requirement for VOL of VREF2 side devices when using PI6ULS5V9306 (Requirement for VOL_DEVICE in figure 6) The VOL requirement of VREF2 side external devices (Temp=25º C, Assume the VIL of VREF1 side devices is 0.3*VREF1) I_pass VREF1 ≤3mA 10mA 15mA 0.9V ≤0.15V ≤0.1V Not Recommended 1.2V ≤0.2V ≤0.15V Not Recommended Pull-up resistors and minimum values Sizing the pull-up resistor on an open-drain bus is specific to the individual application and is dependent on the following driver characteristics: The driver sink current The VOL of driver The VOL of the PI6ULS5V9306 The VIL of the driver Frequency of operation The following tables can be used to estimate the pull-up resistor value in different use cases so that the minimum resistance for the pull-up resistor can be found. Tables in bellow contain suggested minimum values of pull-up resistors for the PI6UILS5V9306 with typical voltage translation levels and drive currents. The calculated values assume that both drive currents are the same. VOL = VIL = 0.1*VCC and accounts for a 5 % VCC tolerance of the supplies, 1 % resistor values. It should be noted that the resistor chosen in the final application should be equal to or larger tha n the values shown in the tablew to ensure that the pass voltage is less than 10 % of the VCC voltage, and the external driver should be able to sink the total current from both pull -up resistors. Pull-up resistor minimum values, 3 mA driver sink current for PI6ULS5V9306 A Side B side 0.9V RPU(A) = 845Ω RPU(B) = 845Ω RPU(A) = 976Ω RPU(B) = 976Ω RPU(A) = none RPU(B) = 887Ω Or both 1.2kΩ RPU(A) = none RPU(B) = 1.18kΩ Or both 1.5kΩ RPU(A) = none RPU(B) = 1.82kΩ Or both 2.15kΩ 1.2V RPU(A) = 1.02kΩ RPU(B) = 1.02kΩ RPU(A) = none RPU(B) = 887Ω Or both 1.3kΩ RPU(A) = none RPU(B) = 1.18kΩ Or both 1.5kΩ RPU(A) = none RPU(B) = 1.82kΩ Or both 2.25kΩ 1.5V RPU(A) = none RPU(B) = 866Ω Or both 1.38kΩ RPU(A) = none RPU(B) = 1.18kΩ Or both 1.5kΩ RPU(A) = none RPU(B) = 1.78kΩ Or both 2.31kΩ 1.8V RPU(A) = 1.47kΩ RPU(B) = 1.47kΩ RPU(A) = none RPU(B) = 1.15kΩ Or both 1.5kΩ RPU(A) = none RPU(B) = 1.78kΩ Or both 2.42kΩ 2.5V RPU(A) = 1.96kΩ RPU(B) = 1.96kΩ RPU(A) = none RPU(B) = 1.78kΩ Or both 2.67kΩ 3.3V RPU(A) = none RPU(B) = 1.74kΩ Or both 2.95kΩ
2015-08-0006 PT0451-5 8/18/15 PI6ULS5V9306 Dual bidirectional I2C-bus and SMBus voltage-level translator Pull-up resistor minimum values, 10 mA driver sink current for PI6ULS5V9306 A Side B side 0.9V RPU(A) = 255Ω RPU(B) = 255Ω RPU(A) = 287Ω RPU(B) = 287Ω RPU(A) = none RPU(B) = 267Ω Or both 363Ω RPU(A) = none RPU(B) = 357Ω Or both 449Ω RPU(A) = none RPU(B) = 549Ω Or both 648Ω 1.2V RPU(A) = 309Ω RPU(B) = 309Ω RPU(A) = none RPU(B) = 267Ω Or both 395Ω RPU(A) = none RPU(B) = 357Ω Or both 481Ω RPU(A) = none RPU(B) = 549Ω Or both 681Ω 1.5V RPU(A) = none RPU(B) = 261Ω Or both 427Ω RPU(A) = none RPU(B) = 348Ω Or both 506Ω RPU(A) = none RPU(B) = 536Ω Or both 697Ω 1.8V RPU(A) = 442Ω RPU(B) = 442Ω RPU(A) = none RPU(B) = 348Ω Or both 538Ω RPU(A) = none RPU(B) = 536Ω Or both 729Ω 2.5V RPU(A) = 590Ω RPU(B) = 590Ω RPU(A) = none RPU(B) = 521Ω Or both 782Ω 3.3V RPU(A) = none RPU(B) = 521Ω Or both 865Ω Pull-up resistor minimum values, 15 mA driver sink current for PI6ULS5V9306 A Side B side 0.9V RPU(A) = 169Ω RPU(B) = 169Ω RPU(A) = 191Ω RPU(B) = 191Ω RPU(A) = none RPU(B) = 178Ω Or both 242Ω RPU(A) = none RPU(B) = 237Ω Or both 302Ω RPU(A) = none RPU(B) = 365Ω Or both 431Ω 1.2V RPU(A) = 205Ω RPU(B) = 205Ω RPU(A) = none RPU(B) = 178Ω Or both 263Ω RPU(A) = none RPU(B) = 237Ω Or both 323Ω RPU(A) = none RPU(B) = 365Ω Or both 453Ω 1.5V RPU(A) = none RPU(B) = 174Ω Or both 278Ω RPU(A) = none RPU(B) = 232Ω Or both 337Ω RPU(A) = none RPU(B) = 464Ω Or both 697Ω 1.8V RPU(A) = 294Ω RPU(B) = 294Ω RPU(A) = none RPU(B) = 232Ω Or both 359Ω RPU(A) = none RPU(B) = 486Ω Or both 729Ω 2.5V RPU(A) = 392Ω RPU(B) = 392Ω RPU(A) = none RPU(B) = 536Ω Or both 782Ω 3.3V RPU(A) = none RPU(B) = 348Ω Or both 578Ω
2015-08-0006 PT0451-5 8/18/15 PI6ULS5V9306 Dual bidirectional I2C-bus and SMBus voltage-level translator Max Frequency Application The maximum frequency is limited by the minimum pulse width LOW and HIGH as well as rise time and fall time. The rise and fall times are dependent upon translation voltages, the drive strength, the total node capacitance (CL) and the pull- up resistors (RPU) that are present on the bus. The node capacitance is the addition of the PCB trace capacitance and the device capacitance that exists on the bus. Because of the dependency of the external components, PCB layout and the different device operating states the calculation of rise and fall times is complex and has several inflection points along the curve. The main component of the rise and fall times is the RC time constant of the bus line when the device is in its two primary operating states: when device is in the ON state and it is low-impedance, the other is when the device is OFF isolating the A-side from the B-side. There are some basic guidelines to follow that will help maximize the performance of the device:
- Keep trace length to a minimum by placing the PI6ULS5V9306 close to the processor.
- The signal round trip time on trace should be shorter than the rise or fall time of signal to reduce reflections.
- The faster the edge of the signal, the higher the chance for ringing.
- The higher drive strength controlled by the pull-up resistor (up to 15 mA), the higher the frequency the device can use. The system designer must design the pull-up resistor value based on external current drive strength and limit the node capacitance (minimize the wire, stub, connector and trace length) to get the desired operation frequency result.
2015-08-0006 PT0451-5 8/18/15 PI6ULS5V9306 Dual bidirectional I2C-bus and SMBus voltage-level translator Mechanical Information TDFN2x3-8(ZE) SYMBOL MIN. MAX A 0.70 0.80 A1 0.00 0.50 D 1.92 2.08 E 2.92 3.07 D1 1.40 1.60 E1 1.40 1.60 k b 0.20 0.30 e L 0.22 0.38 PKG. DIMENSIONS(MM) 0.20REF 0.20MIN 0.50TYP Note: Ref: JEDEC MO-229
2015-08-0006 PT0451-5 8/18/15 PI6ULS5V9306 Dual bidirectional I2C-bus and SMBus voltage-level translator Recommended Land pattern for TDFN2x3-8L Note: All linear dimensions are in millimeters
2015-08-0006 PT0451-5 8/18/15 PI6ULS5V9306 Dual bidirectional I2C-bus and SMBus voltage-level translator MSOP-8(U)
2015-08-0006 PT0451-5 8/18/15 PI6ULS5V9306 Dual bidirectional I2C-bus and SMBus voltage-level translator SOIC-8(W)
Ordering Information
Part No. Package Code Package PI6ULS5V9306ZEEX ZE Lead free and Green TDFN2x3-8L,Tape & Reel PI6ULS5V9306UE U Lead free and Green MSOP-8L PI6ULS5V9306UEX U Lead free and Green MSOP-8L,Tape & Reel PI6ULS5V9306WE W 8-Pin,150 mil Wide SOIC PI6ULS5V9306WEX W 8-Pin,150 mil Wide SOIC, Tape & Reel Note: E = Pb-free and Green Adding X Suffix= Tape/Reel Pericom Semiconductor Corporation 1-800-435-2336 www.pericom.com Pericom reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. Pericom does not assume any responsibility for use of any circuitry described other than the circuitry embodied in Pericom product. The company makes no representations that circuitry described herein is free from patent infringement or other rights, of Pericom.