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Technical content

Features

Î P hase jitter filter for PCIe® 2.0 application Î F our pairs of HCSL PCIe 2.0 Differential Clocks Î P rop delay <± 250ps (in PLL mode) Î L ow skew < 50ps Î L ow jitter < 50ps cycle-to-cycle Î < 1 p s additive RMS phase jitter Î 1 00 MHz PLL Mode operation Î 3 .3V operation Î P ackaging (Pb-free and Green): à 2 0-Pin 4.0mm x 4.0mm x0.75mm TQFN (ZD20)

Description

Pericom Semiconductor's PI6PCIEB24 is a PCI Express® (PCIe) 2.0 compliant high-speed, low-noise differential clock buffer. The device distributes the input differential PCIe clock to four differ- ential pairs of clock outputs with zero delay PLL. Block Diagram OUT0 OUT0# OUT1 OUT1# OUT2 OUT2# OUT3 OUT3# PLLPWRDWN# SRC SRC# PLL/BYPASS# OE_0 OE_3 Pin Configuration OE_3 OE_0 IREF VDD OUT3 OUT3# OUT2 OUT2# PWRDWN# VDD_A SRC SRC# PLL/BYPASS# OUT0 OUT0# OUT1 OUT1# VDD VDD VDD 10-0210

www.pericom.com PS9070A 09/01/10 PI6PCIEB24 1:4 PCI Express® Clock Driver Pin Descriptions Pin Name Type Pin No Description SRC & SRC# Input 19, 20 0.7V Differential SRC input from PI6C410 clock synthesizer OUT[0:3] & OUT[0:3]# Output 2, 3, 5, 6, 12, 11, 15, 14 0.7V Differential outputs IREF Input 16 External resistor connection to set the differential output current VDD Power 1, 7, 10, 18 3.3V Power Supply for Outputs PWRDWN# Input 9 3.3V LVTTL active LOW input for power down operation VDD_A Power 17 3.3V Power Supply for PLL PLL/BYPASS# Input 8 When HIGH, PLL is enabled, When LOW, PLL is bypassed. OE_0, OE_3 Input 4, 13 When HIGH, enables corresponding OUT0, OUT3 respectively. Ground connection is through the package metal plate underneath. 10-0210

1 Normal Normal

0 IREF × 2 Low

Figure 1. Power down sequence When PWRDWN# is asserted (Low), 2xI REF current flows through OUT pin. Figure 2. Power down de-assert sequence

www.pericom.com PS9070A 09/01/10 PI6PCIEB24 1:4 PCI Express® Clock Driver Absolute Maximum Ratings (Over operating free-air temperature range) Symbol Parameters Min. Max. Units VDD_A 3.3V Core Supply Voltage -0.5 4.6 V VDD 3.3V I/O Supply Voltage -0.5 4.6 VIH Input High Voltage 4.6 VIL Input Low Voltage -0.5 Ts Storage Temperature -65 150 °C VESD ESD Protection 2000 V Stress beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Symbol Parameters Condition Min. Max. Units VDD_A 3.3V Core Supply Voltage 3.135 3.465 V VDD 3.3V I/O Supply Voltage 3.135 3.465 VIH 3.3V Input High Voltage VDD 2.0 V DD + 0.3 VIL 3.3V Input Low Voltage VSS – 0.3 0.8 IIK Input Leakage Current 0 < VIN < VDD -5 +5 μA IOH Output High Current IOH = 6 x IREF, IREF = 2.32mA 12.2 mA 15.6 CIN Input Pin Capacitance 3 5 pF COUT Output Pin Capacitance 6 LPIN Pin Inductance 7 nH IDD Power Supply Current VDD = 3.465V, FCPU = 100MHz 200 mA ISS Power Down Current Driven outputs 40 TA Ambient Temperature -45 85 °C 10-0210

www.pericom.com PS9070A 09/01/10 PI6PCIEB24 1:4 PCI Express® Clock Driver Configuration Test Load Board Termination 475Ω 49.9Ω Rp 49.9Ω Rp 33Ω Rs 33Ω Rs PI6PCIEB24 TLA TLB OUT OUT# 2pF 2pF AC Switching Characteristics (VDD = 3.3±5%, VDD_A = 3.3±5%) Symbol Parameters Min Max. Units Notes FIN 95 105 MHz Trise / Tfall Rise and Fall Time (measured between 0.175V to 0.525V) 175 700 ps 2 DTrise / DTfall Rise and Fall Time Variation 125 ps 2 Rise/Fall Matching 20 % 2 Tpd PLL Mode (PLL/BYPASS# = 1) ±250 ps Tjitter Cycle – Cycle Jitter 50 ps 3, 4 VHIGH Voltage High including overshoot 660 1150 mV 2 VLOW Voltage Low including undershoot -300 mV 2 Vcross Absolute crossing point voltages 250 550 mV 2 ΔVcross Total Variation of Vcross over all edges 140 mV 2 TDC Duty Cycle 45 55 % 3 Tjadd Additive RMS phase jitter for PCIe GenII <0 1 ps 5 Tpd(bypass) Bypass mode (PLL/BYPASS# = 0) 2.5 6.5 ns 1. T est configuration is R s = 33.2Ω, Rp = 49.9Ω, and 2pF. M easurement taken from Single Ended waveform. M easurement taken from Differential waveform. M easurement taken using M1 data capture analysis tool. A dditive jitter is calculated from input and output RMS phase jitter using PCIe 2.0 filter by T jadd = √(output jitter)2 – (input jitter)2 10-0210

www.pericom.com PS9070A 09/01/10 PI6PCIEB24 1:4 PCI Express® Clock Driver Ordering Information(1-3) Ordering Code Package Code Package Description PI6PCIEB24ZDE ZD 20-pin, 4.0mm x 4.0mm, TQFN, Pb-Free and Green 1. Th ermal characteristics can be found on the company web site at www.pericom.com/packaging/ E = P b-free and Green A dding an X suffix = Tape/Reel Pericom Semiconductor Corporation • 1-800-435-2336 : 20-Lead, Thin Fine Pitch Quad Flat No-Lead (TQFN)N O I T P I R C S E D : E D O C E G A K C A P 2084 - D P : # L O R T N O C T N E M U C O D - - : N O I S I V E R 8 0 / 1 1 / 9 0 : E T A D ZD20 08-0456 Packaging Mechanical: 20-Pin TQFN (ZD) PCI Express and PCIe are registered trademarks of PCI-SIG. Please visit pcisig.org for information. 10-0210