PI6LC48P04LIE

PI6LC48P04 PERICOM | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 10

Technical content

Features

ÎÎ Four differential LVPECL output pairs ÎÎ Selectable crystal oscillator interface or LVCMOS/LVTTL single-ended clock input ÎÎ Supports the following output frequencies: 212.5MHz, 159.375MHz, 106.25MHz, 53.125MHz, 156.25MHz, 187.5MHz ÎÎ RMS phase jitter @ 212.5MHz, using a 26.5625MHz crystal (12kHz – 20MHz): 0.3ps (typical) ÎÎ Full 3.3V or 2.5V supply modes ÎÎ -40°C to 85°C ambient operating temperature ÎÎ Available in lead-free package: 24-TSSOP

Applications

ÎÎ Networking systems Phase Detector VCO M = 24 (fixed) N_SEL[1:0] 0 0 ÷3 0 1 ÷4 1 0 ÷6 1 1 ÷12 OSC CLK0 CLK0# CLK1 CLK1# CLK2 CLK2# CLK3 CLK3# M_reset IN_SEL XTAL_OUT XTAL_IN Ref_IN PLL_Bypass N_SEL[1:0] 4-Output LVPECL Networking Clock Generator 15-0092

www.pericom.com PI6LC48P04 Rev .A 07/20/2015 PI6LC48P04 4-Output LVPECL Networking Clock Generator Pinout Table Pin No. Pin Name I/O Ty pe Description 1, 2 CLK1#, CLK1 Output LVPECL Output Clock 1 3, 22 VDDO Power Output supply pins 4, 5 CLK0, CLK0# Output LVPECL Output Clock 0 M_reset Input Pulldown Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs Qx to go low and the inverted outputs nQx to go high. When logic LOW, the internal dividers and outputs are enabled. PLL_Bypass Input Pulldown Selects either the PLL or the active input reference to be routed to the output dividers. When LOW, selects PLL (PLL enable). When HIGH, selects the reference clock (PLL bypass). 8, 18 NC Not connected VDDA Power Analog power supply 10, N_SEL0, N_SEL1 Input Pulldown Frequency select pins VDD Power Core power supply 13, XTAL_OUT, XTAL_IN Output / Input Parallel resonant crystal interface. XTAL_OUT is the output, and XTAL_IN is the input. 15, 19 G ND Power Ground Ref_IN Input Pulldown CMOS reference clock input IN_SEL Input Pulldown Selects between the single-ended Ref_IN or crystal interface as the PLL reference source. When HIGH, selects Ref_IN. When LOW selects XTAL inputs. 20, 21 CLK3#, CLK3 Output LVPECL Output Clock 3 23, 24 CLK2, CLK2# Output LVPECL Output Clock 2 Pin Configuration CLK0 4 CLK0# 5 V DDO PLL_Bypass 7 IN_SEL8 M_reset CLK2# VDDO CLK3 GND NC NC CLK1# CLK1 CLK3# CLK2 Ref_IN9 VDDA 16 GND10N_SEL0 15 XTAL_IN11 VDD 14 XTAL_OUT12 13N_SEL1 15-0092

www.pericom.com PI6LC48P04 Rev .A 07/20/2015 PI6LC48P04 4-Output LVPECL Networking Clock Generator Frequency Select Function Table Inputs Output Frequency (MHz) Input Frequency (MHz) N_SEL1 N_SEL0 M Div. Value N Div. Value M/N Div. Value 26.5625 0 0 24 3 8 212.5 26.5625 159.375 26.5625 106.25 26.5625 53.125 26.04166 156.25 23.4375 187.5 Typical Crystal Requirement Parameter Test Conditions Minimum Ty pica l Maximum Units Mode of Oscillation Fundamental Frequency 26.5625 MHz Equivalent Series Resistance (ESR) Ω Shunt Capacitance pF Recommended Crystal Specification Pericom recommends: 15-0092

www.pericom.com PI6LC48P04 Rev .A 07/20/2015 PI6LC48P04 4-Output LVPECL Networking Clock Generator Maximum Ratings (Over operating free-air temperature range) Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DC Specifications Power Supply DC Characterisitcs, (TA = -40 to 85ºC) Symbol Parameter Condition Min Ty p Max Units VDD Core Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage 3.135 3.3 3.465 V VDDO Output Supply Voltage 3.135 3.3 3.465 V IGND Power Supply Current 130 mA IDDA Analog Supply Current Included in IGND 30 mA Power Supply DC Characterisitcs, (TA = -40 to 85ºC) Symbol Parameter Condition Min Ty p Max Units VDD Core Supply Voltage 2.375 2.5 2.625 V VDDA Analog Supply Voltage 2.375 2.5 2.625 V VDDO Output Supply Voltage 2.375 2.5 2.625 V IGND Power Supply Current 125 mA IDDA Analog Supply Current Included in IGND 30 mA LVCMOS/LVTTL DC Characterisitcs, (TA = -40 to 85ºC) Symbol Parameter Condition Min Ty p Max Units VIH Input High Voltage VDD = 3.3V ± 5% 2 VDD + 0.3 V VDD = 2.5V ± 5% 1.7 VDD + 0.3 V VIL Input Low Voltage IIH Input High Current Ref_IN, M_reset, N_SEL[0:1], PLL_Bypass, IN_SEL, V DD = VIN = 3.465V 150 µ A IIL Input Low Current Ref_IN, M_reset, N_SEL[0:1], PLL_Bypass, IN_SEL, V DD = VIN = 0V -5 µA CIN Input Capacitance 4 pF RPULL - DOWN Input Pulldown Resistor 51 k Ω 15-0092

www.pericom.com PI6LC48P04 Rev .A 07/20/2015 PI6LC48P04 4-Output LVPECL Networking Clock Generator LVPECL DC Characterisitcs, (VDD = VDDO = 3.3V ± 5%, TA = -40 to 85ºC) Symbol Parameter Condition Min Ty p Max Units VOH Output High Voltage(1) VDD = 3.3V 1.9 2.4 V VDD = 2.5V 1.1 1.6 VOL Output Low Voltage(1) VDD = 3.3V 1.2 1.6 V VDD = 2.5V 0.4 0.8 Note: 1. LVPECL Termination: Source 150ohm to GND and 100ohm across CLK and CLK#. LVPECL Termination: Source 150ohm to GND and using 0.01uF ac-coupled to 50ohm to GND AC Characterisitcs, (VDD = VDDO = 3.3V ± 5%, TA = -40 to 85ºC) Symbol Parameter Condition Min. Ty p. Max Units fOUT Output Frequency Range N_SEL[1:0] = 00 186 226 MHz N_SEL[1:0] = 01 140 170 MHz N_SEL[1:0] = 10 93 113 MHz N_SEL[1:0] = 11 MHz tsk(o) Output Skew(1, 2) 70 ps tjit(Ø) RMS Phase Jitter, (Random)(3) 212.5MHz, (12kHz - 20MHz) 0.3 ps 159.375MHz, (12kHz - 20MHz) 0.3 ps 156.25MHz, (12kMHz - 20MHz) 0.3 ps 106.25MHz, (12kHz - 20MHz) 0.33 ps 106.25MHz, (637kHz - 50MHz) 0.3 ps 53.125MHz, (12kHz - 20MHz) 0.4 ps 53.125MHz, (637kHz - 50MHz) 0.5 ps tR / tF Output Rise/Fall Time 20% to 80% 400 ps odc Output Duty Cycle Note: Electrical parameters are quaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. Note1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross points. Note2: This parameter is defined in accordance with JEDEC Standard 65. Note3: Please refer to the Phase Noise Plots. 15-0092

www.pericom.com PI6LC48P04 Rev .A 07/20/2015 PI6LC48P04 4-Output LVPECL Networking Clock Generator AC Characterisitcs, (VDD = VDDO = 2.5V ± 5%, TA = -40 to 85ºC) Symbol Parameter Condition Min. Ty p. Max Units fOUT Output Frequency Range N_SEL[1:0] = 00 186 226 MHz N_SEL[1:0] = 01 140 170 MHz N_SEL[1:0] = 10 93 113 MHz N_SEL[1:0] = 11 MHz tsk(o) Output Skew(1, 2) 70 ps tjit(Ø) RMS Phase Jitter, (Random)(3) 212.5MHz, (12kHz - 20MHz) 0.3 ps 159.375MHz, (12kHz - 20MHz) 0.3 ps 156.25MHz, (12kMHz - 20MHz) 0.3 ps 106.25MHz, (12kHz - 20MHz) 0.3 ps 106.25MHz, (637kHz - 50MHz) 0.3 ps 53.125MHz, (12kHz - 20MHz) 0.4 ps 53.125MHz, (637kHz - 50MHz) 0.5 ps tR / tF Output Rise/Fall Time 20% to 80% 400 ps odc Output Duty Cycle Note: Electrical parameters are quaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. Note1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross points. Note2: This parameter is defined in accordance with JEDEC Standard 65. Note3: Please refer to the Phase Noise Plots. Phase Noise Plot (156.25MHz) 15-0092

www.pericom.com PI6LC48P04 Rev .A 07/20/2015 PI6LC48P04 4-Output LVPECL Networking Clock Generator LVPECL Test Circuit Power Supply Filtering Techniques As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter perfor - mance, power supply isolation is required. The PI6LC48P04 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. V DD, VDDA and VDDO should be individually connected to the power supply plane through vias, and 0.1μF bypass capacitors should be used for each pin. Figure below illustrates this for a generic V DD pin and also shows that VDDA requires that an additional 10Ω resistor along with a 10μF bypass capacitor be connected to the V DDA pin. VDD 0.1µF 0.1µF 10µF 10Ω 3.3V or 2.5V VDDA 15-0092

www.pericom.com PI6LC48P04 Rev .A 07/20/2015 PI6LC48P04 4-Output LVPECL Networking Clock Generator Recommendations for Unused Input and Output Pins Inputs: Crystal Inputs: For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. A 1kΩ resistor can be tied from XTAL_IN to ground for additional protection. Ref_IN Input: For applications not requiring the use of the clock, it can be left floating. A 1kΩ resistor tied from the Ref_IN to ground can provide additional protection. LVCMOS Control Pins: All control pins have internal pulldowns; A 1kΩ resistor tied from each control pin to ground can provide additional protection. Outputs: LVPECL Outputs: All unused LVPECL outputs can be left floating. Crystal Input Interface The clock generator has been characterized with 18pF parallel resonant crystals. The capacitor values shown in the figure below were determined using a 25MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error. 33pF 27pF XTAL_IN XTAL_OUT 18pF Parallel Crystal 15-0092

www.pericom.com PI6LC48P04 Rev .A 07/20/2015 PI6LC48P04 4-Output LVPECL Networking Clock Generator LVCMOS to XTAL Interface The XTAL_IN input can accept a single-ended LVCMOS signal through an AC coupling capacitor. A general interface diagram is shown in the figure below. The XTAL_OUT pin can be left floating. The input edge rate can be as slow as 10ns. For LVCMOS signals, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. This configuration requires that the output impedance of the driver (Ro) plus the series resis tance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of the two ways. First, R1 and R2 in parallel should equal the transmission line empedance. For most Ω applications, R1 and R2 can be 100 Ω. This can also be accomplished by removing R1 and making R2 50Ω. By overdriving the crystal oscillator, the device will be functional, but note, the device performance is quaranteed by using a quartz crystal. V 50Ω DD Ro Rs Zo = Ro + Rs XTAL_IN XTAL_OUT VDD 0.1µF 15-0092

www.pericom.com PI6LC48P04 Rev .A 07/20/2015 PI6LC48P04 4-Output LVPECL Networking Clock Generator

Ordering Information

Ordering Code Packaging Type Package Description Operating Temperature PI6LC48P04LIE L Pb-free & Green, 24-pin TSSOP Industrial PI6LC48P04LIEX L Pb-free & Green, 24-pin TSSOP, Tape & Reel Industrial Notes:

• Thermal characteristics can be found on the company web site at www.pericom.com/packaging/ "E" denotes Pb-free and Green Adding an "X" at the end of the ordering code denotes tape and reel packaging Pericom Semiconductor Corporation • 1-800-435-2336 • www .pericom.com Packaging Mechanical: 24-Contact TSSOP (L) DATE: 05/03/12 DESCRIPTION: 24-pin, 173mil Wide TSSOP PACKAGE CODE: L DOCUMENT CONTROL #: PD-1312 REVISION: F Notes: 1. Refer JEDEC: MO-153F/AD 2. Controlling dimensions in millimeters 3. Package outline exclusive of mold flash and metal burr 12-0374 15-0092