PI6LC4820

PI6LC4820 PERICOM | Alldatasheet

Document overview

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• PDF pages: 13

Technical content

Features

ÎÎ 3.3V supply voltage ÎÎ Crystal input: 25 MHz ÎÎ Differential input: 25MHz, 156.25 MHz ÎÎ Output frequencies of 312.5, 156.25, 125MHz supported ÎÎ 9 LVPECL or LVDS bank selectable outputs ÎÎ Low 1ps max integrated phase noise design (12kHz to 20MHz) ÎÎ Optional xtal or clock input selection ÎÎ PLL Bypass mode for test ÎÎ Power supply noise rejection: -50 dBc typical @ 156.25 MHz ÎÎ Packaging (Pb-free & Green): 48-lead 7×7mm TQFN

Description

The PI6LC4820 is an LC VCO based low phase noise design intended for 10GbE applications. Typical 10GbE usage assumes a 25Mhz crystal input, while the PLL loop is used to generate the 156.25MHz outputs. An additional buffered crystal oscilla tor output is provided to serve as a low noise reference for other circuitry. For Ethernet applications other than 10GbE, programmable dividers allow for simultaneous output of 312.5, 156.25, and 125MHz. Pin Configuration 20 19 18 17 16 15 14 13 41 42 43 44 45 46 47 48 V DD_QA QA0+ QA4+ QA3- QA3+ QA2- QA2+ QA1- QA1+ QA0- FS0 V DDA QC_Mode FS1 GND PLL_BYPS IN_SEL VDD_OSC IN_SE IN+ QB1+ QB2- QB2+ QA_Mode0 QB_Mode IN- GND FS_B V DD QA_Mode1 FS_C GND FS_A GND VDD_PLL GND 24 23 22 21 37 38 39 40 GND QC- VDD_QC QC+ VDD_QA QA4- VDD_QB QB0- QB0+ QB1- GND 13-0167

HiFlexTM Ethernet Network Clock Generator Block Diagram FS1 FS_B VDD PFD CHARGE/ VDD_PLL FS_A FS0 PLL_BYPS 0/NC 0/NCPOR QA4+ QA4- QB0+ QB0- QB1+ QB1- VDD_QA FS_C QC+ QC- Crystal Oscillator DIFF. IN+ IN- IN_SEL CMOS NC QA0+ QA0- QA1+ QA1- QA2+ QA2- QA3+ QA3- QA_Mode0 QC_Mode QB_Mode IN_SE QB2+ QB2- NC VDD_QB QA_Mode1 VDD_QC LC_VCO ÷A VDD_QC NC VDD_OSC F_VCO SaRonix-eCera GC25000-76B 13-0167

HiFlexTM Ethernet Network Clock Generator Pin Description Pin Number Pin Name Type Description FS0 Input (LVCMOS) Frequency Select Pin. Use FS0=FS1=0 for all 25MHz input sources. Internal pull-down is 100K-Ohm Input Crystal input pin. No internal xtal load capacitance Output Crystal output pin. No internal xtal load capacitance VDD_OSC Power VDD for reference oscillator IN_SEL Input (LVCMOS) Input mux selection pin PLL_BYPS Input (LVCMOS) Optional mode to bypass PLL and have input reference source connect directly to outputs GND Power Ground pin FS1 Input (LVCMOS) Frequency Select Pin. Use FS0=FS1=0 for all 25MHz input sources. Internal pull-down is 100K-Ohm QC_Mode Input (LVCMOS) Out mode control pin selects LVPECL or LVDS mode. If left floating, outputs are tri-stated VDDA Power VDD for analog circuitry GND Power Ground pin VDD_PLL Power VDD for PLL. GND Power Ground pin FS_B Input (LVCMOS) Frequency Select Pin for Bank B , Output Divider GND Power Ground pin FS_A Input (LVCMOS) Frequency Select Pin for Bank A , Output Divider GND Power Ground pin FS_C Input (LVCMOS) Frequency Select Pin for Bank C , Output Divider QA_Mode1 Input (LVCMOS) Out mode control pin selects LVPECL or LVDS mode. If left floating, outputs are tri-stated VDD Power VDD

21 GND Power Ground pin

22, QC-, QC+ Output (Differential) Bank C LVDS/LVPECL selectable output. Controlled by QC_Mode pin VDD_QC Power VDD for bank C outputs VDD_QA Power VDD for bank A outputs 26, QA4-, QA4+ Output (Differential) Bank A LVDS/LVPECL selectable output. Controlled by QA_Mode1 pin 28, QA3-, QA3+ Output (Differential) Bank A LVDS/LVPECL selectable output. Controlled by QA_Mode1 pin 30, QA2-, QA2+ Output (Differential) Bank A LVDS/LVPECL selectable output. Controlled by QA_Mode0 pin 13-0167

HiFlexTM Ethernet Network Clock Generator Input Mux Selection IN_SEL Input

0 Select Crystal Input (Pins 2, 3)

Select IN+, IN- Differential Input (Pins 46, 47) NC Select IN_SE LVCMOS Input (pin 48) PLL Bypass Control Function PLL_BYPS PLL operation

0 PLL enabled

PLL enabled for Banks A, B; Bank C is driven directly by the output of the input mux. Pin Number Pin Name Type Description 32, QA1-, QA1+ Output (Differential) Bank A LVDS/LVPECL selectable output. Controlled by QA_Mode0 pin 34, QA0-, QA0+ Output (Differential) Bank A LVDS/LVPECL selectable output. Controlled by QA_Mode0 pin VDD_QA Power VDD for bank A outputs VDD_QB Power VDD for bank B outputs 38, QB0-, QB0+ Output (Differential) Bank B LVDS/LVPECL selectable output. Controlled by QB_Mode pin 40, QB1-, QB1+ Output (Differential) Bank B LVDS/LVPECL selectable output. Controlled by QB_Mode pin 42, QB2-, QB2+ Output (Differential) Bank B LVDS/LVPECL selectable output. Controlled by QB_Mode pin 44, QA_Mode0, QB_Mode Input (LVCMOS) Out mode control pins select LVPECL, LVDS mode. If left floating, outputs are tri-stated IN- Input (Differential) Frequency input pin, differential (accepts: LVDS, LVPECL, HCSL) IN+ Input (Differential) Frequency input pin, differential (accepts: LVDS, LVPECL, HCSL) IN_SE Input Frequency input pin, Single Ended Input Divider Control Table FS0 Divider Ratio 0 1 Pin Description (Continued..) 13-0167

HiFlexTM Ethernet Network Clock Generator Bank A Output Control QA_Mode0 QA[2:0] QA_Mode1 QA[4:3]

0 LVDS 0 LVDS

QB_Mode QB[2:0]

0 LVDS

C-bank Output Interface Control Configuration QC_Mode QC+/- Output Frequency Control Table FS_A FS_B FS_C Output Frequency 0 0 0 156.25 125 NC NC NC 312.5 PLL Feedback Divider Control Table FS1 Feedback Divider Ratio 0 25 13-0167

HiFlexTM Ethernet Network Clock Generator Operating Conditions Symbol Parameters Min. Max. Units VDD General Power Supply Voltage 3.0 3.6 V TA Ambient Temperature –40 85 °C IDD Power Supply Current All outputs loaded 425 mA IDD_A Power Supply Current for pin10 13 IDD_PLL Power Supply Current for pin12 30 VDDA Analog Power Supply Voltage 2.7 3.6 V VDD_PLL PLL Power Supply Voltage 2.7 3.6 LVCMOS Input Electrical Characteristics Symbol Parameters Conditions Min. Ty p. Max. Units VIH Input High Voltage FS0, FS1 2 V VIL Input Low Voltage 0.8 V VIH Input High Current IN_SEL, PLL_BYPS, FS_A, FS_B, FS_C, QA_Mode, QB_Mode, QC_Mode 2.6 V VIL Input Low Current 0.8 V IIH Input High Current VIN = VDD 45 m A IIL Input Low Current VIN = 0V -45 mA Rpu Internal pull up resistance 100 K W Rdn Internal pull down resistance 100 K W TDC Input Duty Cycle 35 65 % CIN Input Capacitance1 1.5 pF FIN Input Frequency 15 160 MHz Note: 1. There is no internal load capacitance built in to the X1 and X2 pins Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Maximum Ratings (Above which useful life may be impaired. For user guidelines, not tested.) 13-0167

HiFlexTM Ethernet Network Clock Generator LVPECL Output Characteristics Symbol Parameters Condition Min. Ty p. Max. Units FOUT Output Frequency 25 312.5 MHz Trise / Tfall Rise and Fall Time 20% to 80%, single- ended 400 ps TDC Duty Cycle Differential 47 53 % Jphase Integrated phase jitter 12KHz-20MHz @ 156.25MHz, 25MHz Xtal input 0.54 1 ps rms TDIS Output Disable Time 80 ns TEN Output Enable Time 80 ns TLOCK PLL Lock Time 2 ms VPP Output peak-peak Voltage Single-ended 0.6 1 V VOH Output High Voltage VDD = 3.3V VDD-1.4 VDD-0.9 V VOL Output Low Voltage VDD = 3.3V VDD-2.0 VDD-1.7 V LVDS Output Characteristics Symbol Parameters Condition Min. Ty p. Max. Units FOUT Output Frequency 25 312.5 MHz Trise / Tfall Rise and Fall Time 20% to 80%, single- ended 270 ps TDC Duty Cycle Differential 47 53 % Jphase Integrated phase jitter 12KHz-20MHz @ 156.25MHz, 25MHz Xtal input 0.54 1 ps rms Differential Input Characteristics Symbol Parameters Conditions Min. Ty p. Max. Units VIH Input High Voltage VDD - 0.7 V VIL Input Low Voltage VDD - 2.0 V VCM Input Bias Voltage VDD - 1.8 VDD / 2 V RIN Input Differential Impedence2 80 100 120 W VIN-PP Input Differential Swing 0.3 1.8 VPP CIN Differential Input Capacitance 1.5 pF Note: 1. 2. Differential input can be AC or DC coupled. (Over Operating Conditions. See Fig. 1 and 2 for load conditions.) (Over Operating Conditions See Fig. 1 and 2 for load conditions.) 13-0167

HiFlexTM Ethernet Network Clock Generator Crystal Characteristic Parameters Description Min Ty p Max. Units OSCmode Mode of Oscillation Fundamental FREQ Frequency MHz ESR(1) Equivalent Series Resistance 50 Ohm Cload Load Capacitance pF Cshunt Shunt Capacitance pF Drive Level 0.1 mW Note: 1. ESR value is dependent upon frequency of oscillation Power Supply Noise Rejection Specification Parameter Conditions Min. typ Max. Units Supply Noise induced phase spur @ 156.25 NHz output (see note) Fm = 100kHz to 400KHz -50 dBc Note: 1. Measured with 50mVp-p Sinusoidal Interference on the supply VDDQx, measured with the supply filter as shown in Figure 2. Symbol Parameters Condition Min. Ty p. Max. Units TDIS Output Disable Time 80 ns TEN Output Enable Time 80 TLOCK PLL Lock Time 2 ms |VAMP|1 Differential Output Voltage Ampli - tude |VOH - VOL| with 100Ω external ter mination 250 520 mV |VOH - VOL| with 120Ω external ter mination 250 600 VOH Output High Voltage 1.8 V VOL Output Low Voltage 0.925 VOS Output offset voltage 1.125 1.375 ROL Differential output impedance 85 140 Ω Note: 1. Valid for part numbers with date code after Y1338. LVDS Output Characteristics (Continued..) (link to "http://www.pericom.com/saronix" for more detailed crystal specifications) 13-0167

HiFlexTM Ethernet Network Clock Generator Power Decoupling Schematic 1) It is suggested to use the schematic’s decoupling RC value to get best board noise filtering 2) Typical LVPECL is using 150 W pull down in AC or DC coupling drive according to ASIC ref_clk I/O spec 3) The crystal circuit C1/C2 load values are for CL=18pF crystal, they can be adjusted for other CL crystals 4) Please refer to the datasheet for other static I/O logic set for the request work modes and output frequencies 4. 7_603 VDD CLK_QA2_P CLK_QA1_N C10 0.01uF VDD_QA C16 0.1uF FS_0 25M (CL=18p) FS_1 CLK_QA0_P CLK_QB2_P VDD CLK_QC0_N 0.1uF C15 22uF 150 VDD OA4_P FS_A 2. 2_603 QB_MODE VDD INPUT_N CLK_QA4_P 4. 7_603 CLK_QB2_N VDD_QB CLK_QA0_N 1uF VDD CLK_QA3_N PI6LC4820 FS_A QA_MODE0 VDD_QA1 QC0+ QA0- QA0+ QA1- QA1+ QA2- QA2+ QA4- QA_MODE IN- VDD_QA2 FS_B VDD_QB QC_MODE FS_C VDD_QC IN+ IN_SE IN_SEL QB0- QB0+ QB1+ QB2- QB2+ QA3- QA_MODE1 QA3+ QA4+ FS_1 FS_0 PLL_BYPS QB1- QC0- VDDA VDD_PLL VDD GND6 EP GND5 GND4 GND3 GND2 GND1VDD_OSC QA4_N 2. 2_603 C12 0.1uF IN_SE CLK_QA4_N QA_MODE_1 33p C32.2uF CLK_QB1_N QA_MODE_0 27p 2. 2_603 CLK_QB0_N QC_MODE CLK_QA1_P 0.1uFC82.2uF Place to pin C62.2uF VDD VDD FS_C CLK_QB0_P PLL_BYPASS 10_802 VDD_QC 150 CLK_QC0_P C15 22uF 2. 2_603 Place to pin C14 0.1uF CLK_QA2_N Place to pin C15 22uF To LVPECLeq. 100 termination C11 0.01uF 0.1uF FS_B CLK_QB1_P IN_SELECT INPUT_P CLK_QA3_P 13-0167

HiFlexTM Ethernet Network Clock Generator

4 Copyright Pericom Semiconductor 2007 Last Slide

PERICOM CONFIDENTIAL INFORMATION 2. PI6LC4820 Crystal Circuit Layout Guide Pin name

1 FS0

4 VDD_OSC

5 IN_SEL

6 PLL-BYBS

7 GND

8 FS1

PCB Layers: L_1 Signal (Top) L_2 GND plane Solder pad Board via keep out area GND Pad Crystal pad C1 cap. pad GND via Crystal Circuit Oscillator Crystal circuit connection The following diagram shows PI6LC4820 crystal circuit connection with a parallel crystal. For the CL=18pF crystal, it is suggested to use C1=27pF, C2=33pF. C1 and C2 can be adjusted to fine tune to the target ppm of crystal oscillator according to different board layouts. 27pF Crystal(CL=18pF) 33pF SaRonix-eCera GC2500076B Crystal Oscillator Circuit Recommended Crystal Specification Pericom recommends: a) GC2500003 XTAL 49S/SMD(4.0 mm), 25M, CL=18pF, +/-30ppm, http://www.pericom.com/pdf/datasheets/se/GC_GF.pdf b) FY2500081, SMD 5x3.2(4P), 25M, CL=18pF, +/-30ppm, http://www.pericom.com/pdf/datasheets/se/FY_F9.pdf 13-0167

HiFlexTM Ethernet Network Clock Generator

6 Copyright Pericom Semiconductor 2007 Last Slide

PERICOM CONFIDENTIAL INFORMATION 2. PI6LC4820 Crystal Circuit Layout Guide Pin name PCB Layers: L_1 Signal (Top) L_2 GND plane Solder pad Board via keep out area GND Pad Crystal pad C1 cap. pad GND via GND via trace L_1 4. VDD and GND Pins Layout 1) Small value decoupling caps. (0.1uF, 1uF, and 2.2uF) should be placed close to each VDD pin or via 2) Each GND pin should have its own via to the common GND plane 3) Thermal pad must be connected to the GND plane for better thermal distribution and signal conducting with reasonable via counts (>6) 5. LVPECL Differential Output Layout 1) 150 W pull-down should be put close to clock output side with symmetrical position in one pair 2) Do not share 150 W pull-down GND via between each pairs 6. Differential Input 1) This device differential input (pin 47, 48) can accept 25MHz, 125MHz, and 156.25MHz frequencies in most common differential signals (LVPECL, LVDS, HCSL etc.) in either AC or DC coupling, with proper IN_SEL, FS0, and FS1 setting 2) The device differential input has equivalent 100 W differential termination on chip, so PCB 100 W external termination is normally not necessary. Crystal Layout Example 1) X1 pin is the most sensitive as crystal amplifier input 2) X1 and X2 pins connected to crystal trace loop should be very narrow without any board via in the loop and keep the via out of the area 3) Place crystal as close to the IC as possible along with C1/C2 load caps. There should be no via at the top layer to the crystal 4) Keep crystal load cap. C1/C2 to GND sides as close as possible so that the minimum board noise could be coupled into the caps 13-0167

HiFlexTM Ethernet Network Clock Generator Ordering Information(1-3) Ordering Code Package Code Package Description PI6LC4820ZDE ZD 48-Pin, Pb-free & Green (TQFN) Notes: 1. Thermal characteristics can be found on the company web site at www.pericom.com/packaging/ 2. E = Pb-free and Green 3. 3. Adding an X suffix = Tape/Reel Pericom Semiconductor Corporation • 1-800-435-2336 • www .pericom.com Packaging Mechanical: 48-Pin TQFN (ZD) DESCRIPTION: 48-Contact, Thin Fine Pitch Quad Flat No-Lead (TQFN) PACKAGE CODE: ZD (ZD48) DOCUMENT CONTROL #: PD-2045 REVISION: E Notes: 1. All dimensions are in millimeters, angles are in degrees. 2. Refer JEDEC MO-220/VKKD 3. Thermal Pad Soldering Area 4. Depending on the method of lead termination at the edge of the package, pull back maybe present. DATE: 05 4 3/09/12 12-0458 Note: 1. • For latest package info, please check: http://www.pericom.com/products/packaging/mechanicals.php 13-0167