PI6C2302 PERICOM | Alldatasheet

Document overview

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  • PDF pages: 4

Technical content

1 PS8418B 05/21/01

  • 2X CLK_IN on CLK_OUT
  • High-Performance Phase-Locked-Loop Clock Distribution for Networking, ATM, 100/134 MHz Registered DIMM Synchronous DRAM modules for server/workstation/ PC applications
  • Zero Input-to-Output delay
  • Low jitter: Cycle-to-Cycle jitter –100ps max.
  • On-chip series damping resistor at clock output drivers for low noise and EMI reduction
  • Operates at 3.3V V CC
  • Wide range of Clock Frequencies
  • Package: Plastic 8-pin SOIC Package (W) Phase-Locked Loop Clock Driver Product Description The PI6C2302 features a low-skew, low-jitter, phase-locked loop (PLL) clock driver. By connecting the feedback CLK_OUT output to the feedback FB_IN input, the propagation delay from the CLK_IN input to any clock output will be nearly zero. The PI6C2302 provides 2X CLK_IN on CLK_OUT output. Application If the system designer needs more than 16 outputs with the features just described, using two or more zero-delay buffers such as PI6C2509Q, and PI6C2510Q, is likely to be impractical. The device- to-device skew introduced can significantly reduce the perfor- mance. Pericom recommends the use of a zero-delay buffer and an eighteen output non-zero-delay buffer. As shown in Figure 1, this combination produces a zero-delay buffer with all the signal characteristics of the original zero-delay buffer, but with as many outputs as the non-zero-delay buffer part. For example, when combined with an eighteen output non-zero delay buffer, a system designer can create a seventeen-output zero-delay buffer.

Figure 1. This Combination Provides Zero-Delay Between the

Phase-Locked Loop Clock Driver

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Phase-Locked Loop Clock Driver

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Electrical Characteristics

(Over recommended operating free-air temperature range) AC Specifications Timing Requirements (Over recommended ranges of supply voltage and operating free-air temperature, CL = 25pF) lobmySr etemaraPn oitidnoCtseT. niM. pyT. xaMs tinU F KCOLC ycneuqerfkcolCl aicremmoC5 24 31 zHM ycneuqerfkcolCl airtsudnI5 20 01 D IYC elcycytudkcolctupnI0 40 6% purewopretfaemitnoitazilibatS 1s m tp rettijtuohtiwrorreesahP )3( NI_KLC ↑ zHM66dnazHM001ta0 51–0 51+ sp jte lcyc-ot-elcyc,rettiJz HM66dnazHM001tA0 01–0 01+ elcycytuD5 45 5% tr V0.2otV4.0,emit-esiR 0.1 sn tf V4.0otV0.2,emit-llaF 1.1 Note: 3. This switching parameter is guaranteed by design. lobmySn oitidnoCtseTe rutarepmeTV CC .niM. pyT. xaMs tinU I CC VI V= CC I;DNGro O 0= )2( laicremmoCV 6.30 1 Aµ VI V= CC I;DNGro O 0= )2( lairtsudnIV 564.30 1 CI VI V= CC DNGro V3.3 Fp CO VO V= CC DNGro6 I HO V TUO V4.2= 81– Am V TUO V0.2= 03– I LO V TUO V8.0=5 2 V TUO V55.0=7 1 Note: 2. Continuous Output Current

Phase-Locked Loop Clock Driver

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Ordering Information

.0040 .0098 SEATING PLANE .013 .020 .050 BSC .016 .0075 .0098 .0099 .0196 0-8˚ .050 .149 .157 X.XX X.XX DENOTES DIMENSIONS IN MILLIMETERS 3.78 3.99 .189 .196 4.80 5.00 1.27 .016 .026 1.35 1.75 .2284 .2440 5.80 6.20 0.406 0.660 0.330 0.508 0.10 0.25 0.40 1.27 0.19 0.25 0.25 0.50 x 45˚ .053 .068 REF