PI6C20800_12 PERICOM | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 10
Technical content
Features
- Eight Pairs of Differential Clocks
- Low skew 50ps
- Low Cycle-to-cycle jitter 50ps
- Output Enable for all outputs
- Outputs Tristate control via SMBus
- Power Management Control
- Programmable PLL Bandwidth
- PLL or Fanout operation
- 3.3V Operation
- 100-200 MHz PLL Mode Operation
- 100-400 MHz Bypass Mode Operation
- Packaging (Pb-Free Green): 48-Pin SSOP (V) 48-Pin TSSOP (A) PI6C20800
Description
PI6C20800 is a high-speed, low-noise differential clock buffer designed to be a companion to PI6C410B. The device distributes the differential SRC clock from PI6C410B to eight differential pairs of clock outputs either with or without PLL. The input SRC clock can be divided by when SRC_DIV# is LOW. The clock outputs are controlled by input selection of SRC_STOP#, PWRDWN# and SMBus, SCLK and SDA. When input of either SRC_STOP# or PWRDWN# is LOW, the output clocks are Tristated. When PWRDWN# is LOW, the SDA and SCLK inputs must be Tristated. Block Diagram 1:8 Clock Driver for Intel PCI Express® Chipsets Pin Configuration OUT0 OUT0# OUT1 OUT1# OUT2 OUT2# OUT3 OUT3# DIV Output Control SMBus Controller PLLPLL_BW# SRC SRC# PLL/BYPASS# SRC_DIV# SCLK SDA OE_INV OE [0:7] SRC_STOP# PWRDWN# OUT4 OUT4# OUT5 OUT5# OUT6 OUT6# OUT7 OUT7# LOCK VDD_A VSS_A IREF LOCK OE_7 OE_4 OUT7 OUT7# OE_INV V DD OUT6 OUT6# OE_6 OE_5 OUT5 OUT5# V SS VDD OUT4 OUT4# PLL_BW# SRC_STOP# PWRDWN# V SS SRC_DIV# VDD VSS SRC SRC# OE_0 OE_3 OUT0 OUT0# VSS VDD OUT1 OUT1# OE_1 OE_2 OUT2 OUT2# V SS VDD OUT3 OUT3# PLL/BYPASS# SCLK SDA 12-0205
1:8 Clock Driver for Intel PCI Express® Chipsets Pin Descriptions Pin Name Type Pin # Descriptions SRC_DIV# Input 1 3.3V LVTTL input for selecting input frequency divide by active LOW. SRC SRC# Input 4, 5 0.7V Differential SRC input from PI6C410 clock synthesizer OE [0:7] Input 6, 14, 15, 35, 36, 43, 44 3.3V LVTTL input for enabling outputs, active HIGH. OE_INV Input 40 3.3V LVTTL input for inverting the OE, SRC_STOP# and PWRDWN# pins. When same stage When OE[0:7], SRC_STOP#, PWRDWN# inverted. OUT[0:7] OUT[0:7]# Output 12, 13, 17, 20, 21, 29, 30, 33, 34, 37, 38, 41, 0.7V Differential outputs PLL/BYPASS# Input 22 3.3V LVTTL input for selecting fan-out of PLL operation. SCLK Input 23 SMBus compatible SCLOCK input SDA I/O 24 SMBus compatible SDATA IREF Input 46 External resistor connection to set the differential output current SRC_STOP# Input 27 3.3V LVTTL input for SRC stop, active LOW PLL_BW# Input 28 3.3V LVTTL input for selecting the PLL bandwidth PWRDWN# Input 26 3.3V LVTTL input for Power Down operation, active LOW LOCK Output 45 3.3V LVTTL output, transition high when PLL lock is achieved (Latched output) VDD Power 2, 11, 19, 31, 39 3.3V Power Supply for Outputs VSS Ground 3, 10, 18, 25, 32 Ground for Outputs VSS_A Ground 47 Ground for PLL VDD_A Power 48 3.3V Power Supply for PLL Serial Data Interface (SMBus) PI6C20800 is a slave only SMBus device that supports indexed block read and indexed block write protocol using a single 7-bit address and read/write bit as shown below. Address assignment A6 A5 A4 A3 A2 A1 A0 R/W 1 1 0 1 1 1 0 0/1 Data Protocol(1) 1 bit 7 bits 1 1 8 bits 1 8 bits 1 8 bits 1 8 bits 1 1 bit Start bit Slave Addr R/W Ack Register offset Ack Byte Count N Ack Data Byte
0 Ack
N Ack Stop bit Note: 1. Register offset for indicating the starting register for indexed block write and indexed block read. Byte Count in write mode cannot be 12-0205
1:8 Clock Driver for Intel PCI Express® Chipsets Data Byte 0: Control Register Bit Descriptions Type Power Up Condition Output(s) Affected Pin SRC_DIV# Divide by Normal RW 1 x1 OUT[0:7], OUT[0:7]# NA PLL/BYPASS# Fanout PLL RW 1 PLL OUT[0:7], OUT[0:7]# NA PLL Bandwidth HIGH Bandwidth, LOW Bandwidth RW 1 Low OUT[0:7], OUT[0:7]# NA
3 TBD NA
4 TBD NA
5 TBD NA
SRC_STOP# Driven when stopped Tristate RW 0 Driven when stopped OUT[0:7], OUT[0:7]# PWRDWN# Driven when stopped Tristate RW 0 Driven when stopped OUT[0:7], OUT[0:7]# NA Data Byte 1: Control Register Bit Descriptions Type Power Up Condition Output(s) Affected Pin OUTPUTS enable Enabled Disabled RW 1 Enabled OUT0, OUT0# NA
1 RW 1
Enabled OUT1, OUT1# NA
2 RW 1
Enabled OUT2, OUT2# NA
3 RW 1
Enabled OUT3, OUT3# NA
4 RW 1
Enabled OUT4, OUT4# NA
5 RW 1
Enabled OUT5, OUT5# NA
6 RW 1
Enabled OUT6, OUT6# NA
7 RW 1
Enabled OUT7, OUT7# NA 12-0205
1:8 Clock Driver for Intel PCI Express® Chipsets Data Byte 2: Control Register Bit Descriptions Type Power Up Condition Output(s) Affected Pin Allow control of OUTPUTS with assertion of SRC_STOP# Free running Stopped with SRC_Stop# RW 0 Free running OUT0, OUT0# NA
1 RW 0
running OUT1, OUT1# NA
2 RW 0
running OUT2, OUT2# NA
3 RW 0
running OUT3, OUT3# NA
4 RW 0
running OUT4, OUT4# NA
5 RW 0
running OUT5, OUT5# NA
6 RW 0
running OUT6, OUT6# NA
7 RW 0
running OUT7, OUT7# NA Data Byte 3: Control Register Bit Descriptions Type Power Up Condition Output(s) Affected Pin TBD RW 1 RW 2 RW 3 RW 4 RW 5 RW 6 RW 7 RW Data Byte 4: Pericom ID Register Bit Descriptions Type Power Up Condition Output(s) Affected Pin Pericom ID R 0 NA NA
1 R 0 NA NA
2 R 0 NA NA
3 R 0 NA NA
4 R 0 NA NA
5 R 1 NA NA
6 R 0 NA NA
7 R 0 NA NA
1 Normal Normal 1 Normal Normal
0 IREF × 2 or Float LOW 0 IREF × 6 or Float LOW
Figure 1. Power down sequence Figure 2. Power down de-assert sequence
Figure 9. Simplified diagram of current-mode output buffer Symbol Conditions Configuration Load Min. Max.
- I NOMINAL refers to the expected current based on the configuration of the device.
1:8 Clock Driver for Intel PCI Express® Chipsets Absolute Maximum Ratings(1) (Over operating free-air temperature range) Symbol Parameters Min. Max. Units VDD_A 3.3V Core Supply Voltage -0.5 4.6 VVDD 3.3V I/O Supply Voltage -0.5 4.6 VIH Input HIGH Voltage 4.6 VIL Input LOW Voltage -0.5 Ts Storage Temperature -65 150 °C VESD ESD Protection 2000 V Note: Stress beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Symbol Parameters Condition Min. Max. Units VDD_A 3.3V Core Supply Voltage 3.135 3.465 VVDD 3.3V I/O Supply Voltage 3.135 3.465 VIH 3.3V Input HIGH Voltage VDD 2.0 VDD + 0.3 VIL 3.3V Input LOW Voltage VSS – 0.3 0.8 IIK Input Leakage Current 0 < VIN < VDD -5 +5 µA VOH 3.3V Output HIGH Voltage IOH = -1mA 2.4 VVOL 3.3V Output LOW Voltage IOL = 1mA 0.4 IOH Output HIGH Current IOH = 6 x IREF, IREF = 2.32mA 12.2 mA15.6 CIN Logic Input Pin Capacitance 1.5 5 pFCOUT Output Pin Capacitance 6 LPIN Pin Inductance 7 nH IDD Power Supply Current VDD = 3.465V, FCPU = 200MHz 250 mAISS Power Down Current Driven outputs 60 ISS Power Down Current Tristate outputs 12 TA Ambient Temperature 0 70 °C 12-0205
1:8 Clock Driver for Intel PCI Express® Chipsets AC Switching Characteristics(1,2,3) (VDD = 3.3±5%, VDD_A = 3.3±5%) Symbol Parameters Min Max. Units Notes FIN PLL Mode 100 200 MHz Bypass Mode 100 400 MHz Trise / Tfall Rise and Fall Time (measured between 0.175V to 0.525V) 175 700 ps ∆Trise / ∆Tfall Rise and Fall Time Variation 125 2 Tskew Output-to-Output Skew 50 ps 3 VHIGH Voltage HIGH 660 850 mV VOVS Max. Voltage 1150 VUDS Min. Voltage -300 VLOW Voltage LOW -150 +150 2 Vcross Absolute crossing poing voltages 250 550 2 ∆Vcross Total Variation of Vcross over all edges 140 2 TDC Duty Cycle 45 55 % 3 Tjcyc-cyc Jitter, Cycle-to-cycle (PLL Mode, Measurement for differential waveform) 50 ps Jitter, Cycle-to-cycle (BYPASS mode as additive jitter) Notes: 1. Test configuration is RS = 33.2Ω, Rp = 49.9Ω, and 2pF. 2. Measurement taken from Single Ended waveform. Measurement taken from Differential waveform. Configuration Test Load Board Termination 475Ω 49.9Ω Rp 49.9Ω Rp 33Ω Rs 33Ω Rs PI6C20800 TLA TLB OUT OUT# 2pF 2pF 12-0205
1:8 Clock Driver for Intel PCI Express® Chipsets DATE: 09/27/11 DESCRIPTION: 48-Pin, 300-Mil Wide, SSOP PACKAGE CODE: V (V48) DOCUMENT CONTROL #: PD-1401 REVISION:F Notes: 1. All dimensions are in inches 2. JEDEC outline : MO-118 AA. 3. Dimensions E and D do not include mold protrusion. 11-0197 Packaging Mechanical: 48-Pin SSOP (V) 12-0205
1:8 Clock Driver for Intel PCI Express® Chipsets Ordering Information(1,2) Ordering Code Package Code Package Description PI6C20800VE V 48-pin, 300-mil wide, SSOP, Pb-Free and Green PI6C20800AE A 48-pin, 240-mil wide, TSSOP, Pb-Free and Green Notes:
- Thermal characteristics can be found on the company web site at www.pericom.com/packaging/
- E Pb-free and Green
- Adding an X suffix Tape/Reel Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com Packaging Mechanical: 48-Pin TSSOP (A) .236 .244 .488 .496 .002 .006 SEATING PLANE .007 .010 .0197 BSC .004 .008 .319 12.4 12.6 6.0 6.2 0.50 0.17 0.27 8.1 0.05 0.15 0.09 0.20 X.XX X.XX DENOTES DIMENSIONS IN MILLIMETERS .018 .030 0.45 0.75 .047
1.20 Max
DOCUMENT CONTROL NO. PD - 1501 REVISION: G DATE: 03/09/05 Note: 1. Controlling dimensions in millimeters. 2. Ref: JEDEC MO-153F/ED Dimension does not include mold flash, protrusions or gate burrs. Mold flash, protru- sions and gate burrs shall not exceed 0.15mm per side. 4. Dimension does not include interlead flash or protrusion. Interlead flash or protrusion shall not exceed 0.25mm per side. DESCRIPTION: 48-Pin 240-Mil Wide TSSOP PACKAGE CODE: A Pericom Semiconductor Corporation 3545 N. 1st Street, San Jose, CA 95134 1-800-435-2335
- www.pericom.com See Note 3 See Note 4 All trademarks are property of their respective owners. 12-0205