PI6C20800B

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Î P hase jitter filter for PCIe 3.0 application Î E ight Pairs of Differential Clocks Î L ow skew < 50ps (PI6C20800B), <60ps (PI6C20800BI) Î L ow Cycle-to-cycle jitter < 60ps Î O utput Enable for all outputs Î O utputs Tristate control via SMBus Î P ower Management Control Î P rogrammable PLL Bandwidth Î P LL or Fanout operation Î 3 .3V Operation Î I ndustrial Temperature Option - PI6C20800BI Î P ackaging (Pb-Free & Green): — 48-Pin TSSOP (A) PCI Express® 3.0 1:8 HCSL Clock Buffer OUT0 OUT0# OUT1 OUT1# OUT2 OUT2# OUT3 OUT3# DIV Output Control SMBus Controller PLLPLL_BW# SRC SRC# PLL/BYPASS# SRC_DIV# SCLK SDA OE_INV OE [0:7] SRC_STOP# PWRDWN# OUT4 OUT4# OUT5 OUT5# OUT6 OUT6# OUT7 OUT7# LOCK VDD_A VSS_A IREF LOCK OE_7 OE_4 OUT7 OUT7# OE_INV V DD OUT6 OUT6# OE_6 OE_5 OUT5 OUT5# V SS VDD OUT4 OUT4# PLL_BW# SRC_STOP# PWRDWN# V SS SRC_DIV# VDD VSS SRC SRC# OE_0 OE_3 OUT0 OUT0# VSS VDD OUT1 OUT1# OE_1 OE_2 OUT2 OUT2# V SS VDD OUT3 OUT3# PLL/BYPASS# SCLK SDA 11-0049

www.pericom.com P-0.1 04/27/1 1 PI6C20800B PCI Express® 3.0 1:8 HCSL Clock Buffer Serial Data Interface (SMBus) PI6C20800B is a slave only SMBus device that supports indexed block read and indexed block write protocol using a single 7-bit address and read/write bit as shown below. Address assignment A6 A5 A4 A3 A2 A1 A0 R/W 1 1 0 1 1 1 0 0/1 Data Write Protocol(1) 1 bit 7 bits 1 1 8 bits 1 8 bits 1 8 bits 1 8 bits 1 1 bit Start bit Slave Addr W Ack Register offset Ack Byte Count = N Ack Data Byte Offset Ack Data Byte N - 1 Ack Stop bit Pinout Table Pin Name Type Pin # Descriptions SRC_DIV# Input 1 3.3V LVTTL input for selecting input frequency divide by 2, active LOW. SRC & SRC# Input 4, 5 0.7V Differential SRC input from PI6C410 clock synthesizer OE [0:7] Input 6, 7, 14, 15, 35, 36, 43, 44 3.3V LVTTL input for enabling outputs, active HIGH. OE_INV Input 40 3.3V LVTTL input for inverting the OE, SRC_STOP# and PWRDWN# pins. When 0 = same stage When 1 = OE[0:7], SRC_STOP#, PWRDWN# inverted. OUT[0:7] & OUT[0:7]# Output 8, 9, 12, 13, 16 17, 20, 38, 41, 42 0.7V Differential outputs PLL/BYPASS# Input 22 3.3V LVTTL input for selecting fan-out of PLL operation. SCLK Input 23 SMBus compatible SCLOCK input SDA I/O 24 SMBus compatible SDATA I REF Input 46 External resistor connection to set the differential output current SRC_STOP# Input 27 3.3V LVTTL input for SRC stop, active LOW PLL_BW# Input 28 3.3V LVTTL input for selecting the PLL bandwidth PWRDWN# Input 26 3.3V LVTTL input for Power Down operation, active LOW LOCK Output 45 3.3V LVTTL output, transition high when PLL lock is achieved (Latched output) V DD Power 2, 11, 19, 31, 39 3.3V Power Supply for Outputs VSS Ground 3, 10, 18, 25, 32 Ground for Outputs VSS_A Ground 47 Ground for PLL VDD_A Power 48 3.3V Power Supply for PLL Note: R egister offset for indicating the starting register for indexed block write and indexed block read. Byte Count in write mode cannot be 0. 11-0049

www.pericom.com P-0.1 04/27/1 1 PI6C20800B PCI Express® 3.0 1:8 HCSL Clock Buffer Data Read Protocol(2) 1 bit 7 bits 1 1 8 bits 1 1 bits 1 1 8 bits 1 8 bits 1 8 bits 1 1 bit Start bit Slave Addr W Ack Register offset Ack Repeat Start Slave Addr R Ack Byte Count = N Ack Data Byte Offset Ack Data Byte N - 1 Not Ack Stop bit Note: R egister offset for indicating the starting register for indexed block write and indexed block read. Data Byte 0: Control Register Bit Descriptions Type Power Up Condition Output(s) Affected Pin SRC_DIV# 0 = Divide by 2 1 = Normal RW 1 = x1 OUT[0:7], OUT[0:7]# NA PLL/BYPASS# 0 = Fanout 1 = PLL RW 1 = PLL OUT[0:7], OUT[0:7]# NA PLL Bandwidth 0 = HIGH Bandwidth, 1 = LOW Bandwidth RW 1 = Low OUT[0:7], OUT[0:7]# NA

3 RESERVED

4 RESERVED

5 RESERVED

SRC_STOP# 0 = Driven when stopped 1 = Tristate RW 0 = Driven when stopped OUT[0:7], OUT[0:7]# PWRDWN# 0 = Driven when stopped 1 = Tristate RW 0 = Driven when stopped OUT[0:7], OUT[0:7]# NA 11-0049

www.pericom.com P-0.1 04/27/1 1 PI6C20800B PCI Express® 3.0 1:8 HCSL Clock Buffer Data Byte 1: Control Register Bit Descriptions Type Power Up Condition Output(s) Affected Pin OUTPUTS enable 1 = Enabled 0 = Disabled RW 1 = Enabled OUT0, OUT0# NA

1 RW 1 = Enabled OUT1, OUT1# NA

2 RW 1 = Enabled OUT2, OUT2# NA

3 RW 1 = Enabled OUT3, OUT3# NA

4 RW 1 = Enabled OUT4, OUT4# NA

5 RW 1 = Enabled OUT5, OUT5# NA

6 RW 1 = Enabled OUT6, OUT6# NA

7 RW 1 = Enabled OUT7, OUT7# NA

Data Byte 2: Control Register Bit Descriptions Type Power Up Condition Output(s) Affected Pin Allow control of OUTPUTS with assertion of SRC_STOP# 0 = Free running 1 = Stopped with SRC_Stop# RW 0 = Free running OUT0, OUT0# NA

1 RW 0 = Free running OUT1, OUT1# NA

2 RW 0 = Free running OUT2, OUT2# NA

3 RW 0 = Free running OUT3, OUT3# NA

4 RW 0 = Free running OUT4, OUT4# NA

5 RW 0 = Free running OUT5, OUT5# NA

6 RW 0 = Free running OUT6, OUT6# NA

7 RW 0 = Free running OUT7, OUT7# NA

Data Byte 3: Control Register Bit Descriptions Type Power Up Condition Output(s) Affected Pin RESERVED RW 1 RW 2 RW 3 RW 4 RW 5 RW 6 RW 7 RW 11-0049

www.pericom.com P-0.1 04/27/1 1 PI6C20800B PCI Express® 3.0 1:8 HCSL Clock Buffer Data Byte 4: Pericom ID Register Bit Descriptions Type Power Up Condition Output(s) Affected Pin Pericom ID R 0 NA NA

1 R 0 NA NA

2 R 0 NA NA

3 R 0 NA NA

4 R 0 NA NA

5 R 1 NA NA

6 R 0 NA NA

7 R 0 NA NA

PWRDWN# OUT OUT# SRC_Stop# OUT OUT#

1 Normal Normal 1 Normal Normal

0 IREF × 2 or Float LOW 0 IREF × 6 or Float LOW

Power Down (PWRDWN# assertion) PWRDWN# OUT# OUT Power Down (PWRDWN# De-assertion) PWRDWN# OUT OUT# Tdrive_PwrDwn# <300us, >200mV Tstable <1ms 11-0049

www.pericom.com P-0.1 04/27/1 1 PI6C20800B PCI Express® 3.0 1:8 HCSL Clock Buffer Differential Clock Buffer Characteristics Symbol Minimum Maximum RO 3000Ω N/A ROS unspecified unspecified VOUT N/A 850mV Current Accuracy Symbol Conditions Configuration Load Min. Max. IOUT VDD = 3.30 ±5% RREF = 475Ω 1% IREF = 2.32mA Nominal test load for given configuration -12% INOMINAL +12% INOMINAL Note: 1. INOMINAL refers to the expected current based on the configuration of the device. Current-mode output buffer characteristics of OUT[0:7], OUT[0:7]# IOUT 0.85V Slope ~ 1/Rs RO ROS VOUT = 0.85V max Iout VDD (3.3V ± 5%) Differential Clock Output Current Board Target Trace/Term Z Reference R, Iref = VDD/(3xRr) Output Current V OH @ Z 100Ω (100Ω differential ≈ 15% coupling ratio) RREF = 475Ω 1%, IREF = 2.32mA IOH = 6 x IREF 0.7V @ 50 11-0049

www.pericom.com P-0.1 04/27/1 1 PI6C20800B PCI Express® 3.0 1:8 HCSL Clock Buffer Absolute Maximum Ratings(1) (Over operating free-air temperature range) Symbol Parameters Min. Max. Units VDD_A 3.3V Core Supply Voltage -0.5 4.6 V VDD 3.3V I/O Supply Voltage -0.5 4.6 VIH Input HIGH Voltage 4.6 VIL Input LOW Voltage -0.5 Ts Storage Temperature -65 150 °C VESD ESD Protection 2000 V Note: S tress beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Symbol Parameters Condition Min. Max. Units VDD_A 3.3V Core Supply Voltage 3.135 3.465 V VDD 3.3V I/O Supply Voltage 3.135 3.465 VIH 3.3V Input HIGH Voltage 2.0 V DD + 0.3 VIL 3.3V Input LOW Voltage VSS – 0.3 0.8 IIK Input Leakage Current 0 < VIN < VDD -5 +5 µA VOH 3.3V Output HIGH Voltage I OH = -1mA 2.4 V VOL 3.3V Output LOW Voltage IOL = 1mA 0.4 IOH Output HIGH Current IOH = 6 x IREF, IREF = 2.32mA 12.2 mA 15.6 CIN Logic Input Pin Capacitance 1.5 5 pF COUT Output Pin Capacitance 6 LPIN Pin Inductance 7 nH IDD Power Supply Current VDD = 3.465V, FCPU = 100MHz 250 mAISS Power Down Current Driven outputs 80 ISS Power Down Current Tristate outputs 12 TA Ambient Temperature Commercial (PI6C20800B) 0 70 Industrial (PI6C20800BI) -40 85 11-0049

www.pericom.com P-0.1 04/27/1 1 PI6C20800B PCI Express® 3.0 1:8 HCSL Clock Buffer AC Switching Characteristics(1,2,3) (VDD = 3.3±5%, VDD_A = 3.3±5%) Symbol Parameters Min Typ. Max. Units Notes Fin SRC/SRC# Input Frequency PLL Mode 95 105 MHz 6 SRC/SRC# Input Frequency Bypass Mode 95 400 MHz 6 Trise / Tfall Rise and Fall Time (measured between 0.175V to 0.525V) 175 700 ps ΔTrise / ΔTfall Rise and Fall Time Variation 125 2 Tpd Input to Output Propagation Delay PLL Mode PI6C20800B -250 250 ps PI6C20800BI -450 450 Bypass Mode PI6C20800B -7.5 7.5 ns PI6C20800BI -8 8 T skew Output-to-Output Skew (PI6C20800B) 50 ps Output-to-Output Skew (PI6C20800BI) 65 3 VHIGH Voltage HIGH (Measured at 100MHz @ 3.3V) 600 900 mV VOVS Max. Voltage 1150 VUDS Min. Voltage -300 VLOW Voltage LOW -150 +150 2 Vcross Absolute crossing poing voltages 250 550 2 ΔVcross Total Variation of Vcross over all edges 140 2 TDC Duty Cycle (Measured at 100 MHz) 45 55 % 3 Tjcyc-cyc Jitter, Cycle-to-cycle (PLL Mode, Measurement for dif- ferential waveform) 60 ps 4 Jitter, Cycle-to-cycle (BYPASS mode as additive jitter) J add Additive RMS phase jitter for PCIe 2.0 <0 1 ps 5 Jadd RMS phase jitter for PCIe 3.0 PLL L-BW @ 2M & 5M 1 st H3 1.115 3 ps PLL L-BW @ 2M & 4M 1st H3 1.211 3 PLL L-BW @ 2M & 5M 1st H3 1.116 3 PLL L-BW @ 2M & 4M 1st H3 1.425 3 PLL H-BW @ 2M & 5M 1st H3 0.646 1 PLL H-BW @ 2M & 4M 1st H3 0.644 1 PLL H-BW @ 2M & 5M 1st H3 0.646 1 PLL H-BW @ 2M & 4M 1st H3 0.579 1 Notes: T est configuration is R S = 33.2Ω, Rp = 49.9Ω, and 2pF. M easurement taken from Single Ended waveform. M easurement taken from Differential waveform. M easured using M1 timing analyzer from Amherst. A dditive jitter is calculated from input and output RMS phase jitter by using PCIe 2.0 filter. (J add = √ (output jitter)2 – (input jitter)2 ) 0.5% downnspread input 11-0049

www.pericom.com P-0.1 04/27/1 1 PI6C20800B PCI Express® 3.0 1:8 HCSL Clock Buffer Configuration Test Load Board Termination 475Ω 49.9Ω Rp 49.9Ω Rp 33Ω Rs 33Ω Rs PI6C20800B or PI6C20800BI TLA TLB OUT OUT# 2pF 2pF 11-0049

www.pericom.com P-0.1 04/27/1 1 PI6C20800B PCI Express® 3.0 1:8 HCSL Clock Buffer Packaging Mechanical: 48-Pin TSSOP (A) .236 .244 .488 .496 .002 .006 SEATING PLANE .007 .010 .0197 BSC .004 .008 .319 12.4 12.6 6.0 6.2 0.50 0.17 0.27 8.1 0.05 0.15 0.09 0.20 X.XX X.XX DENOTES DIMENSIONS IN MILLIMETERS .018 .030 0.45 0.75 .047

1.20 Max

DOCUMENT CONTROL NO. PD - 1501 REVISION: G DATE: 03/09/05 Note: 1. Controlling dimensions in millimeters. 2. Ref: JEDEC MO-153F/ED Dimension does not include mold flash, protrusions or gate burrs. Mold flash, protru- sions and gate burrs shall not exceed 0.15mm per side. 4. Dimension does not include interlead flash or protrusion. Interlead flash or protrusion shall not exceed 0.25mm per side. DESCRIPTION: 48-Pin 240-Mil Wide TSSOP PACKAGE CODE: A Pericom Semiconductor Corporation 3545 N. 1st Street, San Jose, CA 95134 1-800-435-2335

• www.pericom.com See Note 3 See Note 4 Ordering Information(1,2) Ordering Code Package Code Package Description PI6C20800BAE AE 48-pin, 240-mil wide, TSSOP, Pb-Free and Green PI6C20800BIAE AE 48-pin, 240-mil wide, TSSOP, Pb-Free and Green (Industrial) Notes: Th ermal characteristics can be found on the company web site at www.pericom.com/packaging/ E = P b-free and Green A dding an X suffix = Tape/Reel PCIe® , and the PCI EXPRESS design mark ® are trademarks of PCI-SIG ® (www.pcisig.com) Pericom Semiconductor Corporation • 1-800-435-2336 11-0049