PI6C20400SH | DigiCamel IC Datasheet

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PI6C20400S PERICOM | Alldatasheet

Document overview

Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
PDF pages: 10

Technical content

Features

Phase jitter ﬁ lter for PCIe Gen II application
Four Pairs of Differential Clocks
Low skew < 50ps
Low jitter < 50ps cycle-to-cycle
< 1 ps additive RMS phase jitter
Output Enable for all outputs
Outputs tristate control via SMBus
Programmable PLL Bandwidth
100 MHz PLL Mode operation
100 - 400 MHz Bypass Mode operation
3.3V Operation
Packaging (Pb-free and Green): — 28-Pin SSOP (H28) & 28-Pin TSSOP (L28) PI6C20400S

Description

Pericom Semiconductor's PI6C20400S is a PCI Express GenII compliant high-speed, low-noise differential clock buffer designed to be companion to PI6C410BS. The device distributes the differential SRC clock from PI6C410BS to four differential pairs of clock outputs either with or without PLL. The clock outputs are controlled by input selection of SRC_STOP#, PWRDWN# and SMBus, SCLK and SDA. When input of either SRC_STOP# or PWRDWN# is low, the output clocks are Tristated. When PWRDWN# is low, the SDA and SCLK inputs must be Tri- stated. Block Diagram 1:4 Clock Driver for Intel PCI Express Chipsets Pin Conﬁ guration OUT0 OUT0# OUT1 OUT1# OUT2 OUT2# OUT3 OUT3# DIV Output Control SMBus Controller PLLPLL_BW# SRC SRC# PLL/BYPASS# SCLK SDA OE_INV OE_0 & OE_3 SRC_STOP# PWRDWN# VDD_A VSS_A IREF OE_INV VDD OUT3 OUT3# OE_3 OUT2 OUT2# V DD PLL_BW# SRC_STOP# PWRDWN# VDD SRC SRC# VSS VDD OUT0 OUT0# OE_0 OUT1 OUT1# VDD PLL/BYPASS# SCLK SDA 07-0265

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1:4 Clock Driver for Intel PCI Express Chipsets Pin Descriptions Pin Name Type Pin No Description SRC & SRC# Input 2, 3 0.7V Differential SRC input from PI6C410 clock synthesizer OE_0 & OE_3 Input 8, 21 3.3V LVTTL input for enabling outputs, active high. OE_0 for OUT0 / OUT0# OE_3 for OUT3 / OUT3# OE_INV Input 25 3.3V LVTTL input for inverting the OE, SRC_STOP# and PWRDWN# pins. When 0 = same stage When 1 = OE_0, OE_3, SRC_STOP#, PWRDWN# inverted. OUT[0:3] & OUT[0:3]# Output 6, 7, 9, 10, 19, 20, 22, 23 0.7V Differential outputs PLL/BYPASS# Input 12 3.3V LVTTL input for selecting fan-out of PLL operation. SCLK Input 13 SMBus compatible SCLOCK input SDA I/O 14 SMBus compatible SDATA IREF Input 26 External resistor connection to set the differential output current SRC_STOP# Input 16 3.3V LVTTL input for SRC stop, active low PLL_BW# Input 17 3.3V LVTTL input for selecting the PLL bandwidth PWRDWN# Input 15 3.3V LVTTL input for Power Down operation, active low V DD Power 1, 5, 11, 18, 24 3.3V Power Supply for Outputs VSS Ground 4 Ground for Outputs VSS_A Ground 27 Ground for PLL VDD_A Power 28 3.3V Power Supply for PLL Serial Data Interface (SMBus) PI6C20400S is a slave only SMBus device that supports indexed block read and indexed block write protocol using a single 7-bit address and read/write bit as shown below. Address assignment A6 A5 A4 A3 A2 A1 A0 R/W 1101 1 1 0 0 /1 Data Protocol 1 bit 7 bits 1 1 8 bits 1 8 bits 1 8 bits 1 8 bits 1 1 bit Start bit Slave Addr R/W Ack Register offset Ack Byte Count = N Ack Data Byte 0 Ack … Data Byte N - 1 Ack Stop bit Notes: 1. Register offset for indicating the starting register for indexed block write and indexed block read. Byte Count in write mode cannot be 0. 07-0265

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1:4 Clock Driver for Intel PCI Express Chipsets Data Byte 0: Control Register Bit Descriptions Type Power Up Condition Output(s) Affected Source Pin Outputs Mode 0 = Divide by 2 1 = Normal RW 1 = Normal OUT[0:3], OUT[0:3]# NA PLL/BYPASS# 0 = Fanout 1 = PLL RW 1 = PLL OUT[0:3], OUT[0:3]# NA PLL Bandwidth 0 = High Bandwidth, 1 = Low Bandwidth RW 1 = Low OUT[0:3], OUT[0:3]# NA

3 Reserved NA

4 Reserved NA

5 Reserved NA

SRC_STOP# 0 = Driven when stopped 1 = Tristate RW 0 = Driven when stopped OUT[0:3], OUT[0:3]# NA PWRDWN# 0 = Driven when stopped 1 = Tristate RW 0 = Driven when stopped OUT[0:3], OUT[0:3]# NA Data Byte 1: Control Register Bit Descriptions Type Power Up Condition Output(s) Affected Source Pin

0 Reserved NA

1 OUTPUTS enable

1 = Enabled 0 = Disabled RW 1 = Enabled OUT0, OUT0# NA

2 RW 1 = Enabled OUT1, OUT1# NA

5 OUTPUTS enable

1 = Enabled 0 = Disabled RW 1 = Enabled OUT2, OUT2# NA

6 RW 1 = Enabled OUT3, OUT3# NA

7 Reserved NA

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1:4 Clock Driver for Intel PCI Express Chipsets Data Byte 2: Control Register Bit Descriptions Type Power Up Condition Output(s) Affected Source Pin

1 Allow control of OUTPUTS with

assertion of SRC_STOP# 0 = Free running 1 = Stopped with SRC_Stop# RW 0 = Free running OUT0, OUT0# NA

2 RW 0 = Free running OUT1, OUT1# NA

5 Allow control of OUTPUTS with

assertion of SRC_STOP# 0 = Free running 1 = Stopped with SRC_Stop# RW 0 = Free running OUT2, OUT2# NA

6 RW 0 = Free running OUT3, OUT3# NA

Data Byte 3: Control Register Bit Descriptions Type Power Up Condition Output(s) Affected Source Pin Reserved RW 1R W 2R W 3R W 4R W 5R W 6R W 7R W Data Byte 4: Pericom ID Register Bit Descriptions Type Power Up Condition Output(s) Affected Pin Pericom ID R 0 NA NA 1R 0 NA NA 2R 0 NA NA 3R 0 NA NA 4R 0 NA NA 5R 1 NA NA 6R 0 NA NA 7R 0 NA NA 07-0265

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1 Normal Normal 1 Normal Normal

Figure 1. Power down sequence Figure 2. Power down de-assert sequence

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Figure 9. Simpliﬁ ed diagram of current-mode output buffer Symbol Conditions Con ﬁ guration Load Min. Max. NOMINAL refers to the expected current based on the conﬁ guration of the device.

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1:4 Clock Driver for Intel PCI Express Chipsets Absolute Maximum Ratings (Over operating free-air temperature range) Symbol Parameters Min. Max. Units VDD_A 3.3V Core Supply V oltage -0.5 4.6 VVDD 3.3V I/O Supply V oltage -0.5 4.6 VIH Input High V oltage 4.6 VIL Input Low V oltage -0.5 Ts Storage Temperature -65 150 °C VESD ESD Protection 2000 V Note: 1. Stress beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Symbol Parameters Condition Min. Max. Units VDD_A 3.3V Core Supply V oltage 3.135 3.465 VVDD 3.3V I/O Supply V oltage 3.135 3.465 VIH 3.3V Input High V oltage VDD 2.0 V DD + 0.3 VIL 3.3V Input Low V oltage VSS – 0.3 0.8 IIK Input Leakage Current 0 < VIN < VDD -5 +5 A VOH 3.3V Output High V oltage IOH = -1mA 2.4 VVOL 3.3V Output Low V oltage IOL = 1mA 0.4 IOH Output High Current IOH = 6 x IREF, IREF = 2.32mA 12.2 mA15.6 CIN Input Pin Capacitance 3 5 pFCOUT Output Pin Capacitance 6 LPIN Pin Inductance 7 nH IDD Power Supply Current VDD = 3.465V , FCPU = 100MHz 200 mAISS Power Down Current Driven outputs 40 ISS Power Down Current Tristate outputs 12 TA Ambient Temperature 0 70 °C 07-0265

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1:4 Clock Driver for Intel PCI Express Chipsets AC Switching Characteristics (VDD = 3.3±5%, VDD_A = 3.3±5%) Symbol Parameters Min Max. Units Notes FIN PLL Mode 95 105 MHz Bypass Mode 100 400 MHz Trise / Tfall Rise and Fall Time (measured between 0.175V to 0.525V) 175 700 ps 2 ΔTrise / ΔTfall Rise and Fall Time Variation 125 ps 2 Rise/Fall Matching 20 % 2 Tpd PLL Mode ±250 ps Non-PLL Mode 2.5 6.5 ns Tjitter Cycle – Cycle Jitter 50 ps 3, 4 VHIGH V oltage High including overshoot 660 1150 mV 2 VLOW V oltage Low including undershoot -300 mV 2 Vcross Absolute crossing point voltages 250 550 mV 2 Vcross Total Variation of Vcross over all edges 140 mV 2 TDC Duty Cycle 45 55 % 3 Tjadd Additive RMS phase jitter for PCIe GenII <0 1 ps 5 Notes: 1. Test conﬁ guration is Rs = 33.2Ω, Rp = 49.9Ω, and 2pF. 2. Measurement taken from Single Ended waveform. 3. Measurement taken from Differential waveform. 4. Measurement taken using M1 data capture analysis tool. 5. Additive jitter is calculated from input and output RMS phase jitter by using PCIr Gen II ﬁ lter. (T jadd = √(output jitter)2 – (input jitter)2 Conﬁ guration Test Load Board Termination 475Ω 49.9Ω Rp 49.9Ω Rp 33Ω Rs 33Ω Rs PI6C20400 TLA TLB OUT OUT# 2pF 2pF 07-0265

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1:4 Clock Driver for Intel PCI Express Chipsets $%3#2)04)/. 0IN -IL7IDE $/#5-%.4#/.42/,./ 2%6)3)/.$ $!4% Pericom Semiconductor Corporation 3545 N. 1st Street, San Jose, CA 95134 1-800-435-2335

www.pericom.com 3%!4).' 0,!.% "3# "3# -AX Note: 1. Package Outline Exclusive of Mold Flash and Metal Burr 2. Controlling dimentions in millimeters 3. Ref: JEDEC MO-153F/AE 07-0265

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1:4 Clock Driver for Intel PCI Express Chipsets Ordering Information(1-3) Ordering Code Package Code Package Description PI6C20400SH H 28-pin, 209-mil wide, SSOP PI6C20400SHE HE 28-pin, 209-mil wide, SSOP, Pb-Free and Green PI6C20400SL L 28-pin, 173-mil wide, TSSOP PI6C20400SLE LE 28-pin, 173-mil wide, TSSOP, Pb-Free and Green Notes: 1. Thermal characteristics can be found on the company web site at www.pericom.com/packaging/ 2. E = Pb-free and Green 3. Adding an X sufﬁ x = Tape/Reel Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com $%3#2)04)/. 0IN -IL7IDE $/#5-%.4#/.42/,./ 2%6)3)/.$ $!4% Pericom Semiconductor Corporation 3545 N. 1st Street, San Jose, CA 95134 1-800-435-2335

www.pericom.com 3%!4).' 0,!.% "3# "3# -AX Note: 1. Package Outline Exclusive of Mold Flash and Metal Burr 2. Controlling dimentions in millimeters 3. Ref: JEDEC MO-153F/AE 07-0265

Product Information

PI6C20400SH specifications and overview.

Summary

1 4 Clock Driver for Intel PCI Express Chipsets

Description

1 4 Clock Driver for Intel PCI Express Chipsets

Source title PI6C20400SH Datasheet(PDF) - Pericom Semiconductor Corporation

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