PI6C20400A PERICOM | Alldatasheet
Document overview
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- PDF pages: 10
Technical content
Features
- Phase jitter filter for PCIe® 2.0 application Four Pairs of Differential Clocks
- Low skew 50ps
- Low jitter 50ps cycle-to-cycle
- < ps additive RMS phase jitter
- Output Enable for all outputs
- Outputs tristate control via SMBus
- Programmable PLL Bandwidth
- 100 MHz PLL Mode operation
- 100 400 MHz Bypass Mode operation
- 3.3V Operation
- Packaging (Pb-free and Green): →28-Pin SSOP (H28) →28-Pin TSSOP (L28) PI6C20400A
Description
Pericom Semico nductor's PI6C20400A is a PCIe® 2.0 compliant high-speed, low-noise dif ferential clock buf fer designed to be companion to PI6C410BS. The device distributes the dif ferential SRC clock from PI6C410BS to four dif ferential pairs of clock outputs either with or without PLL. The clock outputs are controlled by input selection of SRC_ST OP#, PWRDWN# and SMBus, SCLK and SDA. When input of either SRC_ST OP# or PWRDWN# is low the output clocks are T ristated. When PWRDWN# is low the SDA and SCLK inputs must be T ri-stated. Block Diagram 1:4 Clock Driver for Intel PCIe® Chipsets Pin Configuration OUT0 OUT0# OUT1 OUT1# OUT2 OUT2# OUT3 OUT3# DIV Output Control SMBus Controller PLLPLL_BW# SRC SRC# PLL/BYPASS# SCLK SDA OE_INV OE_0 & OE_3 SRC_STOP# PWRDWN# VDD_A VSS_A IREF OE_INV VDD OUT3 OUT3# OE_3 OUT2 OUT2# V DD PLL_BW# SRC_STOP# PWRDWN# VDD SRC SRC# VSS VDD OUT0 OUT0# OE_0 OUT1 OUT1# VDD PLL/BYPASS# SCLK SDA 14-0195
1:4 Clock Driver for Intel PCIe® Chipsets www.pericom.com 03/27/13 Pin Descriptions Pin Name T ype Pin No Description SRC SRC# Input 2, 3 0.7V Differential SRC input from PI6C410 clock synthesizer OE_0 OE_3 Input 8, 3.3V LVTTL input for enabling outputs, active high. OE_0 for OUT0 OUT0# OE_3 for OUT3 OUT3# OE_INV Input 25 3.3V LVTTL input for inverting the OE, SRC_STOP# and PWRDWN# pins. When same stage When OE_0, OE_3, SRC_STOP#, PWRDWN# inverted. OUT[0:3] OUT[0:3]# Output 6, 10, 19, 20, 22, 23 0.7V Differential outputs PLL/BYPASS# Input 12 3.3V LVTTL input for selecting fan-out of PLL operation. SCLK Input 13 SMBus compatible SCLOCK input SDA I/O 14 SMBus compatible SDATA IREF Input 26 External resistor connection to set the differential output current SRC_STOP# Input 16 3.3V LVTTL input for SRC stop, active low PLL_BW# Input 17 3.3V LVTTL input for selecting the PLL bandwidth PWRDWN# Input 15 3.3V LVTTL input for Power Down operation, active low VDD Power 1, 5, 11, 18, 24 3.3V Power Supply for Outputs VSS Ground 4 Ground for Outputs VSS_A Ground 27 Ground for PLL VDD_A Power 28 3.3V Power Supply for PLL Serial Data Interface (SMBus) This part is a slave only SMBus device that supports indexed block read and indexed block write protocol using a single 7-bit address and read/write bit as shown below. Address Assignment A6 A5 A4 A3 A2 A1 A0 W/R 1 1 0 1 1 1 0 0/1 Data Protocol 1 bit 7 bits 1 1 8 bits 1 8 bits 1 8 bits 1 8 bits 1 1 bit Start bit Slave Addr R/W Ack Register of fset Ack Byte Count N Ack Data Byte
0 Ack …
N Ack Stop bit Notes: 1. Register offset for indicating the starting register for indexed block write and indexed block read. Byte Count in write mode cannot be 14-0195
1:4 Clock Driver for Intel PCIe® Chipsets www.pericom.com 03/27/13 Data Byte 0: Control Register Bit Descriptions Type Power Up Condition Output(s) Affected Source Pin Outputs Mode Divide by Normal RW 1 Normal OUT[0:3], OUT[0:3]# NA PLL/BYPASS# Fanout PLL RW 1 PLL OUT[0:3], OUT[0:3]# NA PLL Bandwidth High Bandwidth, Low Bandwidth RW 1 Low OUT[0:3], OUT[0:3]# NA
3 Reserved NA
4 Reserved NA
5 Reserved NA
SRC_STOP# Driven when stopped T ristate RW 0 Driven when stopped OUT[0:3], OUT[0:3]# NA PWRDWN# Driven when stopped T ristate RW 0 Driven when stopped OUT[0:3], OUT[0:3]# NA Data Byte 1: Control Register Bit Descriptions Type Power Up Condition Output(s) Affected Source Pin
0 Reserved NA
1 OUTPUTS
Enabled OUT0, OUT0# NA
2 RW 1
Enabled OUT1, OUT1# NA
5 OUTPUTS
Enabled OUT2, OUT2# NA
6 RW 1
Enabled OUT3, OUT3# NA
7 Reserved NA
1:4 Clock Driver for Intel PCIe® Chipsets www.pericom.com 03/27/13 Data Byte 2: Control Register Bit Descriptions Type Power Up Condition Output(s) Affected Source Pin
1 Allow
SRC_STOP# Free running Stopped with SRC_Stop# RW 0 Free running OUT0, OUT0# NA
2 RW 0
running OUT1, OUT1# NA
5 Allow
SRC_STOP# Free running Stopped with SRC_Stop# RW 0 Free running OUT2, OUT2# NA
6 RW 0
running OUT3, OUT3# NA Data Byte 3: Control Register Bit Descriptions Type Power Up Condition Output(s) Affected Source Pin Reserved RW 1 RW 2 RW 3 RW 4 RW 5 RW 6 RW 7 RW Data Byte 4: Pericom ID Register Bit Descriptions Type Power Up Condition Output(s) Affected Pin Pericom ID R 0 NA NA
1 R 0 NA NA
2 R 0 NA NA
3 R 0 NA NA
4 R 0 NA NA
5 R 1 NA NA
6 R 0 NA NA
7 R 0 NA NA
1 Normal Normal 1 Normal Normal
0 I REF × 2 or Float Low 0 IREF × 6 or Float Low
Figure 1. Power down sequence Figure 2. Power down de-assert sequence
Figure 9. Simplified diagram of current-mode output buffer Symbol Conditions Configuration Load Min. Max. INOMINAL refers to the expected current based on the configuration of the device.
1:4 Clock Driver for Intel PCIe® Chipsets www.pericom.com 03/27/13 Absolute Maximum Ratings (Over operating free-air temperature range) Symbol Parameters Min. Max. Units VDD_A 3.3V Core Supply V oltage -0.5 4.6 VVDD 3.3V I/O Supply V oltage -0.5 4.6 VIH Input High V oltage 4.6 VIL Input Low V oltage -0.5 Ts Storage T emperature -65 150 °C VESD ESD Protection 2000 V Note: Stress beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Symbol Parameters Condition Min. Max. Units VDD_A 3.3V Core Supply V oltage 3.135 3.465 VVDD 3.3V I/O Supply V oltage 3.135 3.465 VIH 3.3V Input High V oltage VDD 2.0 V DD + 0.3 VIL 3.3V Input Low V oltage VSS – 0.3 0.8 IIL Input Leakage Current 0 < VIN < VDD -5 +5 µA VOH 3.3V Output High V oltage IOH = -1mA 2.4 VVOL 3.3V Output Low V oltage IOL = 1mA 0.4 IOH Output High Current IOH = 6 x IREF, IREF = 2.32mA 12.2 mA15.6 CIN Input Pin Capacitance 2 5 pFCOUT Output Pin Capacitance 6 LPIN Pin Inductance 7 nH IDD(BYPASS) Power Supply Current (PLL Bypass) VDD = 3.465V, FCPU = 100MHz 90 mAIDD Power Supply Current VDD = 3.465V Bypass mode 100 FCPU = 100MHz PLL mode 130 ISS Power Down Current Driven outputs 40 ISS Power Down Current T ristate outputs 12 TA Ambient T emperature -40 85 °C 14-0195
1:4 Clock Driver for Intel PCIe® Chipsets www.pericom.com 03/27/13 AC Switching Characteristics (VDD = 3.3±5%, VDD_A = 3.3±5%) Symbol Parameters Min Max. Units Notes FIN PLL Mode 95 105 MHz Bypass Mode 100 400 MHz Trise / Tfall Rise and Fall T ime (measured between 0.175V to 0.525V) 175 700 ps 2 DTrise / DTfall Rise and Fall T ime V ariation 125 ps 2 Tpd PLL Mode ±250 ps Non-PLL Mode 2.5 6.5 ns Tjitter Cycle – Cycle Jitter 50 ps 3, 4 VHIGH Voltage High including overshoot 660 1 150 mV 2 VLOW Voltage Low including undershoot -300 mV 2 Vcross Absolute crossing point voltages 250 550 mV 2 DVcross Total V ariation of Vcross over all edges 140 mV 2 TDC Duty Cycle 45 55 % 3 Tjadd Additive RMS phase jitter for PCIe 2.0 <0 1 ps 5 Notes: Test configuration is Rs = 33.2Ω, Rp = 49.9Ω, and 2pF. Measurement taken from Single Ended waveform. Measurement taken from Differential waveform. Measurement taken using data capture analysis tool. Additive jitter is calculated from input and output RMS phase jitter by using PCIe 2.0 filter. (Tjadd = √(output jitter)2 – (input jitter)2 Configuration Test Load Board Termination 475Ω 49.9Ω Rp 49.9Ω Rp 33Ω Rs 33Ω Rs PI6C20400A TLA TLB OUT OUT# 2pF 2pF 14-0195
1:4 Clock Driver for Intel PCIe® Chipsets www.pericom.com 03/27/13 Packaging Mechanical: 28-Pin SSOP (H) : 28-Pin, 209-Mil Wide, SSOPN O I T P I R C S E D : E D O C E G A K C A P 1250 - D P : # L O R T N O C T N E M U C O D F : N O I S I V E R 8 0 / 0 1 / 4 0 : E T A D H28 08-0143 14-0195
1:4 Clock Driver for Intel PCIe® Chipsets www.pericom.com 03/27/13 Ordering Information(1-3) Ordering Code Package Code Package Description PI6C20400AHE HE 28-pin, 209-mil wide, SSOP, Pb-Free and Green PI6C20400ALE LE 28-pin, 173-mil wide, TSSOP Pb-Free and Green Notes: Thermal characteristics can be found on the company web site at www.pericom.com/packaging/ E Pb-free and Green Adding an X suffix T ape/Reel Pericom Semiconductor Corporation • 1-800-435-2336 • www .pericom.com PCIe® , and the PCI EXPRESS design mark® are trademarks of PCI-SIG® (www.pcisig.com) Packaging Mechanical: 28-Pin TSSOP (L) DESCRIPTION: 28-Pin, 173-Mil Wide, TSSOP PACKAGE CODE: L DOCUMENT CONTROL NO. PD - 1313 REVISION: D DATE: 03/09/05 Pericom Semiconductor Corporation 3545 N. 1st Street, San Jose, CA 95134 1-800-435-2335
- www.pericom.com .378 .386 .047 1.20.002 .006 SEATING PLANE .0256 BSC .018 .030 .252 BSC .169 .177 0.05 0.15 6.4 0.45 0.75 0.09 0.20 4.3 4.5 9.6 9.8 0.65 0.19 0.30 .007 .012 .004 .008 Max Note: 1. Package Outline Exclusive of Mold Flash and Metal Burr 2. Controlling dimentions in millimeters 3. Ref: JEDEC MO-153F/AE 14-0195