PI6C185-02B PERICOM | Alldatasheet

Document overview

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Technical content

Features

• High speed: 140 MHz • Low noise non-inverting 1-7 buffer • Supports up to three SDRAM DIMMs • Low skew (<250ps) between any two output clocks • I2C Serial Configuration interface • Multiple Vdd, Vss pins for noise reduction • 3.3V power supply voltage • 16-pin TSSOP (L) and QSOP (Q) packages

Description

The PI6C185-02B, a high-speed low-noise 1-7 non-inverting buffer, is designed for SDRAM clock buffer applications. It is intended to be used with the PI6C10X clock generator for Intel Architecture-based Mobile systems. At power up, all SDRAM outputs are enabled and active. The I2C Serial control may be used to individually activate/deactivate any of the seven output drivers. Note: Purchase of I2C components from Pericom conveys a license to use them in an I2C system as defined by Philips. /K53/K44/K52/K41/K4D/K36 /K53/K44/K52/K41/K4D/K32 /K53/K44/K52/K41/K4D/K31 /K53/K44/K52/K41/K4D/K30 /K42/K55/K46/K5F/K49/K4E /K53/K44/K41/K54/K41 /K53/K43/K4C/K4F/K43/K4B /K53/K44/K52/K41/K4D/K33 /K49/K32/K43 /K49/K2F/K4F /K2E/K2E/K2E/K2E/K2E/K2E/K2E /K31 /K32 /K33 /K56/K73/K73 /K34 /K42/K55/K46/K5F/K49/K4E /K35 /K53/K44/K52/K41/K4D/K31 /K36 /K56/K64/K64 /K37 /K53/K43/K4C/K4B/K38 /K53/K44/K52/K41/K4D/K32 /K53/K44/K52/K41/K4D/K36 /K56/K73/K73 /K56/K64/K64 /K53/K44/K52/K41/K4D/K33 /K56/K73/K73 /K53/K44/K41/K54/K41 /K31/K36 /K31/K35 /K31/K34 /K31/K33 /K31/K32 /K31/K31 /K31/K30 /K39 /K56/K64/K64 /K53/K44/K52/K41/K4D/K30 /K53/K44/K52/K41/K4D/K34 /K53/K44/K52/K41/K4D/K35 16-Pin L,Q

1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 PI6C185-02B Precision 1-7 Clock Buffer Pin Description PI6C185-02 Serial Configuration Map Byte0: SDRAM Active/Inactive Register (1 = enable, 0 = disable) Note: Inactive means outputs are held LOWand are disabled from switching PI6C185-02B I2C Address Assignment 6A5 A4 A3 A2 A1 A0 AW /R 1101001 0 tiB# niPn oitpircseD 7tiB6 2 MARDS 6tiB- ) 0otezilaitinI(CN 5tiB- ) 0otezilaitinI(CN 4tiB- ) 0otezilaitinI(CN 3tiB3 1 MARDS 2tiB2 0 MARDS 1tiB- ) 0otezilaitinI(CN 0tiB- ) 0otezilaitinI(CN Byte1: SDRAM Active/Inactive Register (1 = enable, 0 = disable) tiB# niPn oitpircseD 7tiB6 16 MARDS 6tiB5 15 MARDS 5tiB- ) 0otezilaitinI(CN 4tiB- ) 0otezilaitinI(CN 3tiB2 14 MARDS 2tiB1 13 MARDS 1tiB- ) 0otezilaitinI(CN 0tiB- ) 0otezilaitinI(CN niPl angiSe pyT. ytQn oitpircseD 61,51,21,11,6,3,2] 6...0[MARDSI 7 s tuptuOkcolCdereffuB 5N I_FUBI 1 t upnIreffuBkcolC 8A TADSO /I1 I rofataDlaireS 2 ecafretniC 9K LCSI 1 I rofkcolClaireS 2 ecafretniC 31,7,1V DD rewoP3 y lppuSrewoPV3.3 41,01,4V SS dnuorG3 d nuorG

1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 PI6C185-02B Precision 1-7 Clock Buffer lobmySr etemaraPn oitidnoCtseT. niM. pyT. xaMs tinU I DD tnerruCylppuSz HM0=NI_FUB3 AmI DD tnerruCylppuSz HM66.66=NI_FUB DBT I DD tnerruCylppuSz HM0.001=NI_FUB The I2C interface permits individual enable/disable of each clock output and test mode enable. The PI6C185-02B, a slave receiver device, cannot be read back. Sub addressing is not supported. To change one of the control bytes, all preceding bytes must be sent. Every byte put on the SDATA line must be 8-bits long (MSB first), followed by an acknowledge bit generated by the receiving device. During normal data transfers, SDATA changes only when SCLK is LOW. Exceptions: A HIGH to LOW transition on SDATA while SCLK is HIGH indicates a “start” condition; a LOW to HIGH transition on SDATA while SCLK is HIGH is a “stop” condition and indicates the end of a data transfer cycle. Each data transfer is initiated with a start condition and ended with a stop condition. The first byte after a start condition is always a 7-bit address byte followed by a read/write bit. (HIGH = read from addressed device, LOW = write to addressed device). If the device’s own address is detected, PI6C185-02B generates an acknowledge by pulling SDATA line LOW during ninth clock pulse, then accepts the following data bytes until another start or stop condition is detected. Following acknowledgement of the address byte (0D2H), two more bytes must be sent: 1. “Command Code” byte &2. “Byte Count” byte. Although the data bits on these two bytes are “don’t care,” they must be sent and acknowledged. 2-Wire I2C Control Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Supply Current (VDD = +3.465V, Cload = max) Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.)

1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 PI6C185-02B Precision 1-7 Clock Buffer SDRAM Clock Buffer Operating Specification AC Timing DC Operating Specifications (VDD = +3.3V ±5%, TA = 0°C –70°C) lobmySr etemaraPn oitidnoC. niM. pyT. xaMs tinU I NIMHO tnerrucpu-lluPV TUO V0.2=0 4– AmI XAMHO tnerrucpu-lluPV TUO V531.3=6 3 I NIMLO tnerrucnwod-lluPV TUO V0.1=0 4 I XAMLO tnerrucnwod-lluPV TUO V4.0=8 3 t HR MARDS etaregdeesirtuptuO ylnoMARDS %5–V3.3 V4.2-V4.0@ 5.14 sn/V t HF MARDS etaregdellaftuptuO ylnoMARDS %5–V3.3 V4.0-V4.2@ 5.14 lobmySr etemaraPn oitidnoC. niM. xaMs tinU egatloVtupnI V HI egatloVhgiHtupnIV DD 0.2V DD 3.0+ V V LI egatloVwoLtupnIV SS 3.0–8 .0 I LI tnerruCegakaeLtupnIV <0 NI V< DD 5-5 + mA V DD %5–V3.3= V HO egatloVhgiHtuptuOI HO Am1–=4 .2 V V LO egatloVwoLtuptuOI LO Am1=4 .0 C NI ecnaticapaCniPtupnI5 Fp C TUO ecnaticapaCsniptuptuO6 L NIP ecnatcudnIniP7 H n TA erutarepmeTtneibmAw olfriAoN0 0 7C ” lobmySr etemaraP zHM66z HM001z HM331 stinU snt HKDS emithgihKLCMARDS6 .53 .30 .1 t LKDS emitwolKLCMARDS3 .51 .30 .1 sn/V sn elcyCytuDV 5.1taderusaeM5 45 55 45 55 45 5% t WKSDS wekStuptuOottuptuOMARDS0 520 520 52s p

Figure 1. Clock Waveforms

  1. Maximum rise/fall times are guaranteed at maximum specified load.
  2. Minimum rise/fall times are guaranteed at minimum specified load.
  3. Rise/fall times are specified with pure capacitive load as shown.

Testing is done with an additional 500W resistor in parallel.

  1. Place RS series resistors and CI capacitors as close as possible to the respective clock pins. Typical

and fall time are still within the specified values.

  1. Minimize the number of “vias” of the clock traces.
  2. Route clock traces over a continuous ground plane or over a continuous power plane. Avoid routing

clock traces from plane to plane (refer to rule #2).

  1. Position clock signals away from signals that go to any cables or any external connectors.

1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 PI6C185-02B Precision 1-7 Clock Buffer Pericom Semiconductor Corporation 2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com 16-Pin TSSOP (L) Package

Ordering Information

Figure 2. Design Guidelines