PI6C185-00 PERICOM | Alldatasheet

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Technical content

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Pin ConfigurationBlock Diagram

Description

The PI6C185-00 is a high-speed low-noise 1-7 non-inverting buffer designed for SDRAM clock buffer applications. This buffer is intended to be used with the PI6C10X clock genera- tor for Intel Architecture-based Mobile systems. At power up all SDRAM output are enabled and active. The I 2C Serial control may be used to individually activate/deactivate any of the 7 output drivers. Note: Purchase of I 2C components from Pericom conveys a license to use them in an I2C system as defined by Philips. SDRAM6 SDRAM2 SDRAM1 SDRAM0 BUF_IN SDATA SCLOCK SDRAM3 I2C I/O Product Features

  • High-speed, low-noise non-inverting 1-7 buffer
  • Switching speed up to 140 MHz (PI6C185-00A)*
  • Supports up to three mobile SDRAM DIMMs
  • Low skew (<250ps) between any two output clocks
  • I2C Serial Configuration interface
  • Multiple VDD, VSS pins for noise reduction
  • 3.3V power supply voltage
  • 20-pin TSSOP (L) and QSOP (Q) packages 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1 2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 12345678901 2 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 Precision 1-7 Clock Buffer PI6C185-00 V SS 4 BUF_IN 5 SDRAM1 SDRAM2 7 VSS 8 VDD SDATA 10 VDD SDRAM5 VSS SDRAM4 SDRAM3 V SS VSS SCLK VDD SDRAM0 VDD VDD SDRAM6 20-Pin L, Q * Maximum Operating Frequencies: PI6C185-00 = 125 MHz; PI6C185-00A = 140 MHz.

Precision 1-7 Clock Buffer

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1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 Pin Description PI6C185-00 I2C Address Assignment PI6C185 Serial Configuration Map Byte0: SDRAM Active/Inactive Register (1 = enable, 0 = disable) Note: Inactive means outputs are held LOW and are disabled from switching 6A5 A4 A3 A2 A1 A0 AW /R 11010 0 1 0 tiB# niPn oitpircseD 7tiB5 1) evitcanI/evitcA(4MARDS 6tiB4 1) evitcanI/evitcA(3MARDS 5tiB- ) 0otezilaitinI(CN 4tiB7 ) evitcanI/evitcA(2MARDS 3tiB- ) 0otezilaitinI(CN 2tiB- ) 0otezilaitinI(CN 1tiB3 ) evitcanI/evitcA(1MARDS 0tiB2 ) evitcanI/evitcA(0MARDS Byte1: SDRAM Active/Inactive Register (1 = enable, 0 = disable) tiB# niPn oitpircseD 7tiB- ) 0otezilaitinI(CN 6tiB- ) 0otezilaitinI(CN 5tiB- ) 0otezilaitinI(CN 4tiB- ) 0otezilaitinI(CN 3tiB- ) 0otezilaitinI(CN 2tiB- ) 0otezilaitinI(CN 1tiB9 1) evitcanI/evitcA(6MARDS 0tiB8 1) evitcanI/evitcA(5MARDS niPl angiSe pyT. ytQn oitpircseD 91,81,51,41,7,3,2] 6.0[MARDSI 7 s tuptuOkcolCdereffuB 5N I_FUBI 1 t upnIreffuBkcolC 01A TADSO /I1 I rofataDlaireS 2 .pu-lluplanretni,ecafretniC 11K LCSI 1 I rofkcolClaireS 2 pu-lluplanretni,ecafretniC 02,61,9,6,1V DD rewoP5 y lppuSrewoPV3.3 71,31,21,8,4V SS dnuorG5d nuorG

Precision 1-7 Clock Buffer

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1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 2-Wire I2C Control The I2C interface permits individual enable/disable of each clock output and test mode enable. The PI6C185-00 is a slave receiver device. It can not be read back. Sub addressing is not supported. To change one of the control bytes, all preceding bytes must be sent. Every bite put on the SDATA line must be 8-bits long (MSB first), followed by an acknowledge bit generated by the receiving device. During normal data transfers SDATA changes only when SCLK is LOW. Exceptions: A HIGH to LOW transition on SDATA while SCLK is HIGH indicates a “start” condition. A LOW to HIGH transition on SDATA while SCLK is HIGH is a “stop” condition and indicates the end of a data transfer cycle. Each data transfer is initiated with a start condition and ended with a stop condition. The first byte after a start condition is always a 7-bit address byte followed by a read/write bit. (HIGH = read from addressed device, LOW = write to addressed device). If the device’s own address is detected, PI6C185-00 generates an acknowledge by pulling SDATA line LOW during ninth clock pulse, then accepts the following data bytes until another start or stop condition is detected. Following acknowledgement of the address byte (0D2H), two more bytes must be sent: 1. “Command Code” byte, and 2. “Byte Count” byte. Although the data bits on these two bytes are “don’t care,” they must be sent and acknowledged. Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Supply Current (VDD = +3.465V, CLOAD = Max.) lobmySr etemaraPn oitidnoCtseT. niM. pyT. xaMs tinU I DD tnerruCylppuSz HM0=NI_FUB3 Am I DD tnerruCylppuSz HM66.66=NI_FUB5 8 I DD tnerruCylppuSz HM0.001=NI_FUB0 31 I DD tnerruCylppuSz HM3.331=NI_FUB0 22 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.)

Precision 1-7 Clock Buffer

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1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 SDRAM Clock Buffer Operating Specification AC Timing DC Operating Specifications (VDD = +3.3V –5%, TA = 0°C - 70°C) lobmySr etemaraPn oitidnoCtseT. niM. xaMs tinU egatloVtupnI V HI egatlovhgihtupnIV DD 0.2V DD 3.0+ V V LI egatlovwoltupnIV SS 3.0-8 .0 I LI tnerrucegakaeltupnIV <0 NI V< DD 5-5 +A m V DD %5–V3.3=]9-0[ V HO egatlovhgihtuptuOI HO Am1–=4 .2 V V LO egatlovwoltuptuOI LO Am1=4 .0 C TUO ecnaticapacniptuptuO 6 Fp C NI ecnaticapacniptupnI 5 L NIP ecnatcudnIniP 7H n TA erutarepmeTtneibmAw olfriAoN0 0 7C ° lobmySr etemaraPs noitidnoCtseT. niM. pyT. xaMs tinU I NIMHO tnerrucpu-lluPV TUO V0.2=4 5– Am I XAMHO tnerrucpu-lluPV TUO V531.3=6 4- I NIMLO tnerrucnwod-lluPV TUO V0.1=4 5 I XAMLO tnerrucnwod-lluPV TUO V4.0=3 5 t hr MARDSy lnoMARDSetaregdeesirtuptuOV 4.2-V40@%5–V3.35 .14 sn/V t ht MARDSy lnoMARDSetaregdellaftuptuOV 4.0-V4.2@%5–V3.35 .14 lobmySr etemaraP zHM66z HM001z HM3.331 stinU snt HKDS emithgihKLCMARDS6 .53 .32 .2 t LKDS emitwolKLCMARDS3 .51 .30 .2 sn/V sn elcyCytuDV 5.1taderusaeM5 45 55 45 55 45 4% t WKSDS wekStuptuOottuptuOMARDS0 520 520 52s p

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Figure 1. Clock Waveforms

  1. Maximum rise/fall times are guaranteed at maximum specified load.
  2. Minimum rise/fall times are guaranteed at minimum specified load.
  3. Rise/fall times are specified with pure capacitive load as shown.

Testing is done with an additional 500Ω resistor in parallel.

  1. Place series R S resistors and CI capacitors as close as possible to the respective clock pins. Typical value

are still within the specified values.

  1. Minimize the number of “vias” of the clock traces.
  2. Route clock traces over a continuous ground plane or over a continuous power plane. Avoid routing clock

traces from plane to plane (refer to rule #2).

  1. Position clock signals away from signals that go to any cables or any external connectors.

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depending on actual PCB design and layout. Figure 2. Design Guidelines

Precision 1-7 Clock Buffer

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1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 .252 .260 .047 1.20 .002 .006 SEATING PLANE .0256 BSC .018 .030 .004 .008.238 .269 .169 .177 X.XX X.XX DENOTES CONTROLLING DIMENSIONS IN MILLIMETERS 0.05 0.15 6.1 6.7 0.45 0.75 0.09 0.20 4.3 4.5 6.4 6.6 0.65 0.19 0.30 .007 .012 Max Pericom Semiconductor Corporation 2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com 20-Pin TSSOP Package Mechanical (L) 20-Pin QSOP Package Mechanical (Q)

Ordering Information

N/P. qerF.xaMe gakcaP L00-581C6IPz HM521e gakcaPPOSSTniP-02 Q00-581C6IPz HM521e gakcaPPOSQniP-02 LA00-581C6IPz HM041e gakcaPPOSSTniP-02 QA00-581C6IPz HM041e gakcaPPOSQniP-02 .337 .344 .053 .069 .004 .010 SEATING PLANE .025 BSC .007 .010.228 .244 .150 .1571 .016 .050 X.XX X.XX DENOTES DIMENSIONS IN MILLIMETERS 0.635 8.56 8.74 1.35 1.75 5.79 6.19 0.41 1.27 0.101 0.254 .008 .012 0.203 0.305 3.81 3.99 0.178 0.254 .058 1.47 .015 x 45˚ 0.38 REF