PI6C184-02 PERICOM | Alldatasheet

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Technical content

Features

BUF_IN SDATA SCLOCK SDRAM3 I2C I/O VSS VDD SDRAM1 SDRAM3 VSS SDRAM2 SDRAM4 SDRAM5 SDRAM12 VDD SDATA VDD SDRAM10 VSS SDRAM9 SDRAM8 VSS VDD SDRAM7 SDRAM6 VSS VSS SCLK VDD SDRAM0 BUF_IN VDD SDRAM11 28-Pin H, S

12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 PI6C184-02 Precision 1-13 Clock Buffer Pin Description PI6C184-02 I2C Address Assignment A A A A A A A W R PI6C184 Serial Configuration Map Byte0: SDRAM Active/Inactive Register (1 = enable, 0 = disable) Note: Inactive means outputs are held LOW and are disabled from switching ni P lo b m y S e p y T y tit n a u Q n oit pir c s e D 1,0 1,7,6,3,2 5.0 M A R D S tu ptu o k c olc ety B M A R D S 2,6 2,3 2,2 2,9 1,8 1.6 M A R D S tu ptu o k c olc ety B M A R D S M A R D S tu ptu o k c olc ety B M A R D S N I F U B reffu b r of tu p n I A T A D S O I r of nip ata D k a s a H .yrtiu cric C r otsis er p u -llu p la n retn I K C O L C S O I r of nip k c ol C a s a H .yrtiu cric C r otsis er p u -llu p la n retn I k 2,4 2,0 2,3 1,5,1 V D D re w o P reffu b M A R D S r of ylp p u s re w o p V 3.3 2,1 2,7 1,6 1,8,4 V S S d n u o r G sreffu B M A R D S r of d n u o r G ti B ni P n oit pir c s e D ti B vitc a n I/e vitc A M A R D S ti B vitc a n I/e vitc A M A R D S ti B d e v re s e R ti B d e v re s e R ti B vitc a n I/e vitc A M A R D S ti B vitc a n I/e vitc A M A R D S ti B vitc a n I/e vitc A M A R D S ti B vitc a n I/e vitc A M A R D S

12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 PI6C184-02 Precision 1-13 Clock Buffer Byte1: SDRAM Active/Inactive Register (1 = enable, 0 = disable) Byte2: Optional Register for Possible Future Requirements (1 = enable, 0 = disable) The I2C interface permits individual enable/disable of each clock output and test mode enable. The PI6C184-02 is a slave receiver device. It can not be read back. Sub addressing is not supported. All preceding bytes must be sent in order to change one of the control bytes. Every bite put on the SDATA line must be 8-bits long (MSB first), followed by an acknowledge bit generated by the receiving device. During normal data transfers Sdata changes only when SCLK is LOW. Exceptions: A HIGH to LOW transition on SDATA while SCLK is HIGH indicates a “start” condition. A LOW to HIGH transition on SDATA while SCLK is HIGH is a “stop” condition and indicates the end of a data transfer cycle. Each data transfer is initiated with a start condition and ended with a stop condition. The first byte after a start condition is always a 7-bit address byte followed by a read/write bit. (HIGH = read from addressed device, LOW = write to addressed device). If the device’s own address is detected, PI6C184-02 generates an acknowledge by pulling SDATA line LOW during ninth clock pulse, then accepts the following data bytes until another start or stop condition is detected. Following acknowledgement of the address byte (D2), two more bytes must be sent: 1. “Command Code” byte, and 2. “Byte Count” byte. Although the data bits on these two bytes are “don’t care,” they must be sent and acknowledged. 2-Wire I2C Control Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for ex- tended periods may affect reliability. Supply Current (VDD = +3.465V, Cload = max) ti B ni P n oit pir c s e D ti B vitc a n I/e vitc A M A R D S ti B vitc a n I/e vitc A M A R D S ti B vitc a n I/e vitc A M A R D S ti B vitc a n I/e vitc A M A R D S ti B A N d e v re s e R ti B A N d e v re s e R ti B vitc a n I/e vitc A M A R D S ti B vitc a n I/e vitc A M A R D S ti B ni P n oit pir c s e D ti B A N d e v re s e R ti B vitc a n I/e vitc A M A R D S ti B A N d e v re s e R ti B A N d e v re s e R ti B A N d e v re s e R ti B A N d e v re s e R ti B A N d e v re s e R ti B A N d e v re s e R lo b m y S r et e m a r a P n oitid n o C ts e T .ni M y T x a M stin U I D D tn erru C ylp p u S z H M N I F U B A m I D D tn erru C ylp p u S z H M 6.6 N I F U B I D D tn erru C ylp p u S z H M 0.0 N I F U B

12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 PI6C184-02 Precision 1-13 Clock Buffer SDRAM Clock Buffer Operating Specification DC Operating Specifications (VDD = +3.3V ±5%, TA = 0°C - 70°C) lo b m y S r et e m a r a P n oitid n o C .ni M y T a M stin U I N I M H O tn erru c p u -llu P V T U O V 0.2 A m I X A M H O tn erru c p u -llu P V T U O V 1.3 I N I M L O tn erru c n w o d -llu P V T U O V 0.1 I X A M L O tn erru c n w o d -llu P V T U O V 4.0 t H R M A R D S etar e g d e e sir tu ptu O yln o M A R D S V 3.3 V 4.2 V 5.1 s V t H F M A R D S etar e g d e llaf tu ptu O yln o M A R D S V 3.3 V 4.0 V 4.2 5.1 lo b m y S r et e m a r a P n oitid n o C ts e T .ni M a M stin U V g a tlo V t u p n I E R O C D D V 3.3 V H I e g atlo V h gi H tu p n I V D D 0.2 V E R O C D D 3.0 V V L I e g atlo V w o L tu p n I V S S 3.0 8.0 I L I tn erru C e g a k a e L tu p n I V N I V D D V D D V 3.3 V H O e g atlo V h gi H tu ptu O I H O A m 4.2 V V L O e g atlo V w o L tu ptu O I L O A m 4.0 C N I e c n atic a p a C ni P tu p n I F p C T U O e c n atic a p a C s nip tu ptu O L N I P e c n atc u d n I ni P H n TA erutare p m e T tn eib m A w olfri A o N C º lo b m y S r et e m a r a P z H M z H M stin U .ni M a M .ni M a M P K D S t d oire p K L C M A R D S 0.5 5.5 0.0 5.0 s n H K D S t e m it h gih K L C M A R D S 6.5 3.3 L K D S t e m it w ol K L C M A R D S 3.5 1.3 E S I R D S t e m it e sir K L C M A R D S 5.1 0.4 5.1 0.4 s V L L A F D S t e m itllaf K L C M A R D S 5.1 0.4 5.1 0.4 H L pt y ale d p o r p H L reffu B M A R D S 0.1 0.5 0.1 0.5 s n L H pt y ale d p o r p L H reffu B M A R D S 0.1 0.5 0.1 0.5 H Z pt, L Z pt y ale d elb a n E reffu B M A R D S 0.1 0.8 0.1 0.8 Z H pt, Z L pt y ale d elb a si D reffu B M A R D S 0.1 0.8 0.1 0.8 elc y C ytu D V 5.1 ta d eru s a e M W K S D S t ot tu ptu O M A R D S w e k S tu ptu O s p AC Timing

Figure 1. Clock Waveforms

  1. Maximum rise/fall times are guaranteed at maximum specified load.
  2. Minimum rise/fall times are guaranteed at minimum specified load.
  3. Rise/fall times are specified with pure capacitive load as shown.

Testing is done with an additional 500Ω resistor in parallel.

  1. Place series resistors and CI capacitors as close as possible to the respective clock pins. Typical value

time are still within the specified values.

  1. Minimize the number of “vias” of the clock traces.
  2. Route clock traces over a continuous ground plane or over a continuous power plane. Avoid routing

clock traces from plane to plane (refer to rule #2).

  1. Position clock signals away from signals that go to any cables or any external connectors.

12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 PI6C184-02 Precision 1-13 Clock Buffer Pericom Semiconductor Corporation 2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com

Ordering Information

Figure 2. Design Guidelines