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Document overview

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Technical content

Features

  • High-speed, low-noise, non-inverting split 1-10 buffer Maximum Frequency up to 250 MHz
  • Low output skew 60ps (Bank 2.5V)
  • Low duty cycle distortion 200ps Low propagation delay 2.0ns (2.5V)
  • Choice of 1.2V, 1.5V, 1.8V or 2.5V supply voltage on Bank Bank Bank C
  • Industrial temperature range: 40°C to 85°C
  • Packages (Pb-free Green): 20-pin, TSSOP (L20) 20-pin, SSOP (H20) 20-pin, QSOP (Q20) 1.2V-2.5V , 250MHz, 1:10 Networking Clock Buffer PI6C10810

Description

The P I6C10810 i s a 1 .2V t o 2 .5V h igh-speed, l ow-noise 1-10 non-inverti ng clock buf fer. The key goal in designing the PI6C10810 is to tar get networking

applications

low-jitter, and high-frequency clock distribution. Providing output-to-output skew as low as 60ps, the PI6C10810 is an ideal clock distribution device for synchronous systems. Designing synchronous networking systems requires a tight level of skew from a large number of outputs. CLK0-4 operate from VDDA supply. CLK5-6 operate from VDDC supply. CLK7-9 operate from VDDB supply. VDDA 4 CLK1 5 CLK0 CLK2 7 VDDA 8 GND GND 10 VDDB CLK8 GND VDDC CLK6 GND CLK5 CLK4 BUF_IN GND CLK3 CLK7 CLK9 CLK2 CLK1 CLK0 BUF_IN CLK3 CLK4 CLK7 CLK6 CLK5 CLK8 CLK9 VDDA VDDC VDDB 11-0015

1.2V-2.5V , 250MHz, 1:10 Networking Clock Buffer Output V oltage (max. to VDD+0.5V Input V oltage (max to VDD+0.5V 2.5V Absolute Maximum Ratings (Above which the useful life may be impaired. For user guidelines only, not tested.) Note: Stresses g reater t han t hose l isted u nder M AXI- MUM R ATINGS m ay c ause p ermanent d amage t o t he device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is n ot i mplied. E xposure t o a bsolute m aximum r ating c onditions for extended periods may affect reliability. 2.5V AC Characteristics (Over Operating Range: VDDA, VDDB, VDDC = 2.5V ± 0.2V, TA = -40° to 85°C) Parameters Description Test Conditions(1) Min. Typ Max. Units FIN Input Frequency 0 250 MHz tPLH, tPHL(2) Propagation Delay BUF_IN to CLKn RL = 500-Ohm, CL = 3pF, 125 MHz Out- puts are measured VDD/2 1.0 1.5 2.0 tSK(O)(3) Output to Output Skew between any two outputs of the same device same transition Bank A (CLK0 - CLK4) –60 60 ps Bank C (CLK5 CLK6) –30 30 Bank B (CLK7 CLK9) –150 150 tSK(P)(3) Pulse Skew between opposite transitions (tPHL-tPLH) of the same output 100 200 tSK(T)(3)(5) Part to Part Skew between two identical outputs of dif- ferent parts on the same board(4) 300 tdc_in Duty Cycle In @ Ins edge rate 45 55 %tdc_out Duty Cycle Out 40 57.5 tj(5) Additive Jitter 50 ps tR(O) Output Rise T ime 20%-80% CLKn RL = 500-Ohm, CL = 3pF 0.5 0.7 nstF(O) Output Fall T ime 80%-20% CLKn 0.5 0.7 Notes: See test circuit and waveforms. Minimum limits are guaranteed but not tested on Propagation Delays. Skew measured at worst case temperature (max. temp). Identical conditions: loading, transitions, supply voltage, temperature, package type and speed grade. Guaranteed by design. 2.5V DC Characteristics (Over Operating Range: VDDA, VDDB, VDDC = 2.5V ± 0.2V, TA = -40° to 85°C) Parameters Description Test Conditions(1) Min. Typ. (2) Max. Units VDD Supply V oltage 2.3 2.5 2.7 VIH Input HIGH V oltage Logic HIGH level 1.7 3.6 VVIL Input LOW V oltage Logic LOW level -0.3 0.7 II Input Current V DD = Max, V in = VDD or GND I pin 15 µA VOH Output High V oltage VDD = Min., VIN = VIH or VIL IOH = -1mA 2.0 V IOH = -2mA 1.7 IOH = -8mA 1.7 VOL Output LOW V oltage VDD = Min., VIN - VIH or VIL IOL = 1mA 0.1 IOL = 2mA 0.2 IOL = 8mA 0.2 Notes: For Max. or Min. conditions, use appropriate operating range values. 2. Typical values are at VDD = 2.5V, +25°C ambient and maximum loading. 11-0015

1.2V-2.5V , 250MHz, 1:10 Networking Clock Buffer 1.8V AC Characteristics (Over Operating Range: VDDA, VDDB, VDDC = 1.8V ± 0.15V, TA = -40° to 85°C) Parameters Description Test Conditions(1) Min. Typ Max. Units FIN Input Frequency 0 200 MHz tPLH, tPHL(2) Propagation Delay BUF_IN to CLKn CL = 3pF, RL = 500-Ohm, 125 MHz Outputs are measured VDD/2 1.0 2.3 2.8 tSK(O)(3) Output to Output Skew between any two outputs of the same device same transition Bank A (CLK0 - CLK4) –60 60 ps Bank C (CLK5 CLK6) 30 30 Bank B (CLK7 CLK9) –200 200 tSK(P)(3) Pulse Skew between opposite transitions (tPHL-tPLH) of the same output 100 200 tSK(T)(3)(5) Part to Part Skew between two identical outputs of different parts on the same board(4) 300 tdc_in Duty Cycle In @ 1 ns edge rate 45 55 %tdc_out Duty Cycle Out 40 57.5 tj(5) Additive Jitter 50 ps tR(o) Output Rise T ime 20% - 80% CLKn 0.5 0.8 nstF(o) Output Fall T ime 80% - 20% CLKn 0.5 0.8 Notes: See test circuit and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. Skew measured at worst case temperature (max. temp). Identical conditions: loading, transitions, supply voltage, temperature, package type and speed grade. 5. Guaranteed by design. Output V oltage (max 2.5V) to VDD+0.5V Input V oltage (max 2.5V) to VDD+0.5V 1.8V Absolute Maximum Ratings (Above which the useful life may be impaired. For user guidelines only, not tested.) Note: Stresses greater than those listed under MAXI - MUM RA TINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating condi tions for extended periods may affect reliability. 1.8V DC Characteristics (Over Operating Range: VDDA, VDDB, VDDC = 1.8V ± 0.15V, TA = -40° to 85°C) Parameters Description Test Conditions(1) Min. Typ. (2) Max. Units VDD Supply V oltage 1.65 1.8 1.95 VIH Input HIGH V oltage Logic HIGH level 1.1 2.7 VVIL Input LOW V oltage Logic LOW level -0.3 0.35*VDD II Input Current(3) VDD = Max, V in VDD or GND I pin 15 µA VOH Output High V oltage VDD = Min., VIN = VIH or VIL IOH = -2mA 1.35 VIOH = -8mA 1.2 VOL Output LOW V oltage VDD = Min., VIN - VIH or VIL IOL = 2mA 0.1 IOL = 8mA 0.2 Notes: 1. For Max. or Min. conditions, use appropriate operating VDD and T a values. 2. Typical values are at VDD = 1.8V, +25°C ambient and maximum loading. This parameter is determined by device characterization but is not production tested. 11-0015

1.2V-2.5V , 250MHz, 1:10 Networking Clock Buffer Output V oltage (max. to VDD+0.5V Input V oltage (max to VDD+0.5V 1.5V Absolute Maximum Ratings (Above which the useful life may be impaired. For user guidelines only, not tested.) Note: Stresses g reater t han t hose l isted u nder M AXI- MUM R ATINGS m ay c ause p ermanent d amage t o t he device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is n ot i mplied. E xposure t o a bsolute m aximum r ating c onditions for extended periods may affect reliability. 1.5V AC Characteristics (Over Operating Range: VDDA, VDDB, VDDC = 1.5V ± 0.1V, TA = -40° to 85°C) Parameters Description Test Conditions(1) Min. Typ Max. Units FIN Input Frequency 0 200 MHz tR/tF CLKn Rise/Fall T ime 20% to 80% 1.0 ns tPLH, tPHL(2) Propagation Delay BUF_IN to CLKn CL = 3pF, RL = 500-Ohms, 125 MHz Outputs are measured VDD/2 2.0 2.8 3.5 ns tSK(O)(3) Output to Output Skew between any two outputs of the same device same transition Bank A (CLK0 - CLK4) –100 100 ps Bank C (CLK5 CLK6) –50 50 Bank B (CLK7 CLK9) –200 200 tSK(P)(3) Pulse Skew between opposite transitions (tPHL-tPLH) of the same output 100 200 tSK(T)(3)(5) Part to Part Skew between two identical outputs of dif ferent parts on the same board(4) 300 tdc_in Duty Cycle In @ Ins edge rate 45 55 %tdc_out(5) Duty Cycle Out 40 60 tj Additive Jitter 50 ps tR(o) Output Rise T ime 20% - 80% CLKn 0.6 0.9 nstF(o) Output Fall T ime 80% - 20% CLKn 0.6 0.9 Notes: 1. See test circuit and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. Skew measured at worst case temperature (max. temp). Identical conditions: loading, transitions, supply voltage, temperature, package type and speed grade. Guaranteed by design. 1.5V DC Characteristics (Over Operating Range: VDDA, VDDB, VDDC = 1.5V ± 0.1V, TA = -40° to 85°C) Parameters Description Test Conditions(1) Min. Typ. (2) Max. Units VDD Supply V oltage 1.4 1.5 1.6 VIH Input HIGH V oltage Logic HIGH level 0.65×VDD VDD VVIL Input LOW V oltage Logic LOW level -0.3 0.35×VDD II Input Current V DD = Max, V in = VDD or GND I pin 15 µA VOH Output High V oltage VDD = Min., VIN = VIH or VIL IOH = -2mA 1.05 VIOH = -8mA 1.75 VOL Output LOW V oltage VDD = Min., VIN - VIH or VIL IOL = 2mA 0.35 IOL = 8mA 0.65 Notes: For Max. or Min. conditions, use appropriate operating range values. 2. Typical values are at VDD = 1.5V, +25°C ambient and maximum loading. 11-0015

1.2V-2.5V , 250MHz, 1:10 Networking Clock Buffer Output V oltage (max. to VDD+0.5V Input V oltage (max to VDD+0.5V 1.2V Absolute Maximum Ratings (Above which the useful life may be impaired. For user guidelines only, not tested.) Note: Stresses g reater t han t hose l isted u nder M AXI- MUM R ATINGS m ay c ause p ermanent d amage t o t he device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is n ot i mplied. E xposure t o a bsolute m aximum r ating c onditions for extended periods may affect reliability. 1.2V AC Characteristics (Over Operating Range: VDDA, VDDB, VDDC = 1.2V ± 0.1V, TA = -40° to 85°C) Parameters Description Test Conditions(1) Min. Typ Max. Units FIN Input Frequency 0 150 MHz tPLH, tPHL(2) Propagation Delay BUF_IN to CLKn CL = 3pF, RL = 500-Ohm, 125 MHz Outputs are measured VDD/2 4 5 6 ns tSK(O)(3) Output to Output Skew between any two outputs of the same device same transition Bank A (CLK0 - CLK4) –150 150 ps Bank C (CLK5 CLK6) –50 50 Bank B (CLK7 CLK9) –300 300 tSK(P)(3) Pulse Skew between opposite transitions (tPHL-tPLH) of the same output 200 300 tSK(T)(3)(5) Part to Part Skew between two identical outputs of different parts on the same board(4) 300 tDC_IN Duty Cycle In @ 1ns edge rate 45 55 %tDC_OUT Duty Cycle Out 40 60 tj(5) Additive Jitter 50 ps tR(o) Output Rise T ime 20% - 80% CLKn 0.9 1 nstF(o) Output Fall T ime 80% - 20% CLKn 0.9 1 Notes: 1. See test circuit and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. Skew measured at worst case temperature (max. temp). Identical conditions: loading, transitions, supply voltage, temperature, package type and speed grade. Guaranteed by design. 1.2V DC Characteristics (Over Operating Range: VDDA, VDDB, VDDC = 1.2V ± 0.1V, TA = -40° to 85°C) Parameters Description Test Conditions(1) Min. Typ. (2) Max. Units VDD Supply V oltage 1.1 1.2 1.3 VIH Input HIGH V oltage Logic HIGH level 0.65×VDD VDD+0.3 VVIL Input LOW V oltage Logic LOW level -0.3 0.35×VDD II Input Current VDD = Max, V in = VDD or GND I pin 15 µA VOH Output High V oltage VDD = Min., VIN = VIH or VIL IOH = -2mA 1.05 VIOH = -8mA 1.75 VOL Output LOW V oltage VDD = Min., VIN - VIH or VIL IOL = 2mA 0.35 IOL = 8mA 0.65 Notes: For Max. or Min. conditions, use appropriate operating range values. 2. Typical values are at VDD = 1.2V, +25°C ambient and maximum loading. 11-0015

1.2V-2.5V , 250MHz, 1:10 Networking Clock Buffer Test Circuits for All Outputs Definitions: CL = Load capacitance: includes jig and probe capacitance. Capacitance (TA = 25°C, f = 1 MHz) Parameters(1) Description Test Conditions Typ Max. Units CIN Input Capacitance VIN = 0V 3.0 4 pFCOUT Output Capacitance VOUT = 0V — 6 Note: 1. This parameter is determined by device characterization but is not production tested. Pulse Generator f = 125MHz D.U.T. 50-Ohm CL 3pF VDD 500-Ohm Power Supply Characteristics Parameters Description Test Conditions(1) Min. Typ. (2) Max. Units IDDQ Quiescent Power Supply Current VDDA = VDDB = VDDC = 2.7V No Load. FIN = 40MHz (Bank Bank Bank C included) mA VDDA = VDDB = VDDC = 1.95V 12 VDDA = VDDB = VDDC = 1.6V 8 VDDA = VDDB = VDDC = 1.2V 8 IOS Short Circuit Current VDDA = VDDB = VDDC 2.7V 1.95V 1.6V 1.2V ±80 ±50 ±35 ±15 mA Notes: 1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics. 2. Typical values are at Per TTL driven input (VIN = VDD - 0.6V); all other inputs at VDD or GND. 11-0015

1.2V-2.5V , 250MHz, 1:10 Networking Clock Buffer Switching Waveforms Propagation Delay Package Skew – tSK(T) Pulse Skew – tSK(P) Output Skew – tSK(O) Input tPLHx VDD VDD/2 CLKx VOH VDD/2 VOL tPHLx tSK(O) CLKy VOH VDD/2 VOL tSK(O) tPLHy tPHLy tSK(O) = | tPLHy - tPLHx | or | tPHLy - tPHLx | Input tPLH1 VDD VDD/2 Part #1 Output VOH VDD/2 VOL tPHL1 tSK(T) Part #2 Output VOH VDD/2 VOL tSK(T) tPLH2 tPHL2 tSK(T) = | tPLH2 - tPLH1 | or | tPHL2 - tPHL1 | Input tPLH VIH VDD/2 VIL Output VOH VDD/2 VOL tPHL tR tF Input tPLH VDD VDD/2 Output VOH VDD/2 VOL tPHL tSK(P) = | tPLH - tPLH | 11-0015

1.2V-2.5V , 250MHz, 1:10 Networking Clock Buffer DESCRIPTION: 20-Pin, 173-Mil Wide, TSSOP PACKAGE CODE: L DOCUMENT CONTROL NO. PD - 1311 REVISION: E DATE: 03/09/05 Pericom Semiconductor Corporation 3545 N. 1st Street, San Jose, CA 95134 1-800-435-2336

  • www.pericom.com .252 .260 .047 1.20 .002 .006 SEATING PLANE .0256 BSC .018 .030 .004 .008 .238 .269 .169 .177 0.05 0.15 6.1 6.7 0.45 0.75 0.09 0.20 4.3 4.56.4 6.6 0.65 0.19 0.30 .007 .012 Max Note: 1. Package Outline Exclusive of Mold Flash and Metal Burr 2. Controlling dimentions in millimeters 3. Ref: JEDEC MO-153F/AC 11-0015

1.2V-2.5V , 250MHz, 1:10 Networking Clock Buffer : 20-Pin, 209-Mil Wide, SSOPN O I T P I R C S E D : E D O C E G A K C A P 1240 - D P : # L O R T N O C T N E M U C O D E : N O I S I V E R 8 0 / 0 1 / 4 0 : E T A D H20 08-0140 11-0015

1.2V-2.5V , 250MHz, 1:10 Networking Clock Buffer Ordering Information(1-3) Ordering Code Package Code Package Type PI6C10810LE L Pb-free Green, 20-pin 173-mil wide TSSOP PI6C10810HE H Pb-free Green, 20-pin 209-mil wide SSOP PI6C10810QE Q Pb-free Green, 20-pin 150-mil wide QSOP Notes: Thermal Characteristics can be found on the web at www.pericom.com/packaging/ E Lead-free and Green Adding an X suffix T ape/Reel Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com .337 .344 .053 .069 .004 .010 SEATING PLANE .025 BSC .007 .010 .228 .244 .150 .157 X.XX X.XX DENOTES DIMENSIONS IN MILLIMETERS 0.635 8.56 8.74 1.35 1.75 5.79 6.19 0.101 0.254 .008 .012 0.203 0.305 3.81 3.99 0.178 0.254 .058 1.47 .015 x 45˚ 0.38REF Detail A Detail A .008 0.20 MIN. Guage Plane .010 0.254 .041 1.04 REF .016 .035 0.41 0.89 0˚-6˚ .008 .013 0.20 0.33 DESCRIPTION: 20-Pin, 150-Mil Wide, QSOP PACKAGE CODE: Q DOCUMENT CONTROL NO. PD - 1202 REVISION: H DATE: 10/22/07 Note: 1) Controlling dimensions in inches. 2) Ref: JEDEC MO-137B/AD 3) Dimensions do not include mold flash, protrusions or gate burrs Pericom Semiconductor Corporation 3545 N. 1st Street, San Jose, CA 95134 1-800-435-2335

  • www.pericom.com 11-0015