PI6C104 PERICOM | Alldatasheet

Document overview

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  • PDF pages: 14

Technical content

Features

  • Up to 112 MHz operation
  • Spread Spectrum Modulation for CPUCLK, and PCICLK
  • Two copies of CPU clock with VDD of 2.5V –5%
  • Seven copies of PCI clock, (synchronous with CPU clock) 3.3V
  • One copy of Ref. clock @ 14.31818MHz (3.3VTTL)
  • 48MHz USB Clock, 24MHz Super I/O clock
  • I2C Serial Configuration Interface
  • Low cost 14.31818MHz crystal oscillator input
  • Power management control
  • Isolated core VDD, VSS pins for noise reduction
  • 28-pin SSOP (H) and SOIC package (S)

Description

The PI6C104 is a high-speed low-noise clock generator designed to work with the PI6C18X family of clock buffer to meet all clock needs for Desktop Intel Architecture platforms. CPU and chipset clock frequencies from 66.6 MHz to 112 MHz are supported. Split supplies of 3.3V and 2.5V are used. The 3.3V power supply powers a portion of the I/O and the core. The 2.5V is used to power the remaining outputs (CPU and APIC). 2.5V signaling follows JEDEC standard 8-X. Power sequencing of the 3.3V and 2.5V supplies is not required. An asynchronous PD# signal may be used to orderly power down (or up) the system during power on. 28-Pin H, S /K52/K45/K46/K31 /K41/K50/K49/K43 /K56/K44/K44/K52/K45/K46 /K56/K44/K44/K41/K50/K49/K43 /K50/K43/K49/K43/K4C/K4B/K5B/K31/K3A/K36/K5D /K43/K50/K55/K43/K4C/K4B/K5B/K30/K3A/K31/K5D /K52/K45/K46 /K4F/K53/K43 /K56/K44/K44/K43/K50/K55 /K32 /K36 /K56/K44/K44/K50/K43/K49/K30/K2C/K31 /K50/K43/K49/K43/K4C/K4B/K5F/K46 /K44/K69/K76 /K50/K4C/K4C/K31 /K53/K45/K4C /K58/K54/K41/K4C/K5F/K4F/K55/K54 /K58/K54/K41/K4C/K5F/K49/K4E /K53/K5B/K30/K2E/K2E/K32/K5D /K53/K44/K41/K54/K41 /K53/K43/K4C/K4F/K43/K4B/K49/K32/K43 /K50/K4C/K4C/K32 /K56/K44/K44/K50/K32 /K50/K49/K34 /K34/K38/K4D/K48/K7A /K32/K34/K4D/K48/K7A/K2F/K52/K45/K46/K4D/K55/K58

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610 SU P+I1 0 tibtceleSycneuqerF

71K LCSU P+I1 I rofkcolClaireS 2 ecafretniC 81A TADSU P+OI1 I rofataDlaireS 2 ecafretniC 22,12] 1:0[KLCUPCO 2 t uptuokcolcUPC 42C IPAO 1 . tuptuolatsyrCdereffuB 1FERO 1 . tuptuolatsyrCdereffuB 41P1 1 z HM42=1,1FER=0,tcelesedom41niP .esiwrehtotuptuo1FER,tupni41PsinipsihtpurewopgniruD 62,02,21,9V DD 4V 3.3.LLP,FER,eroC,ICProfylppusrewoP 52,32V 2DD 2V 5.2.skcolcUPC&CIPArofylppusrewoP 82,91,51,3V SS 4s dnuorG

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11 Z -iH

Byte 5 : PCI Clock Control (1 = Enabled, 0 = Disabled) #tiBp uP# niPe maNn oitpircseD DVSRd evreseR 21 1 2N E1UPCe lbanEsitluafeD,elbanE1KLCUPC 10~ D VSRd evreseR 012 2N E0UPCe lbanEsitluafeD,elbanE0KLCUPC #tiBp uP# niPe maNn oitpircseD 71 4 N EFICPe lbanEsitluafeD,elbanEF_ICP 60 1 1N E6ICPe lbanEsitluafeD,elbanE6ICP 51 0 1N E5ICPe lbanEsitluafeD,elbanE5ICP 40~ ~ d evreseR 8N E4ICPe lbanEsitluafeD,elbanE4ICP

27 N E3ICPe lbanEsitluafeD,elbanE3ICP

16 N E2ICPe lbanEsitluafeD,elbanE2ICP

05 N E1ICPe lbanEsitluafeD,elbanE1ICP

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11 Z -iHZ -iHZ -iHZ -iHZ -iHe tats-irT

Byte 6 : REF Clock Control (1 = Enabled, 0 = Disabled) #tiBp uP# niPe maNn oitpircseD ~D VSRd evreseR 6~ D VSRd evreseR 54 2N ECIPAe lbanEsitluafeD,elbanECIPA 4~ D VSRd evreseR ~D VSRd evreseR 16 21 NEFR1 elbanEevirdhgiH1FER 06 20 NEFR0 elbanEevirdhgiH1FER 0NEFR1NEFR evirDwoL1 0 tluafeD,evirDlamroN0 1 evirDhgiH1 1 Note: Outputs are disabled @ low state Notes: Bit 3 = Enable Software Frequency Select Bit 1 = Enable Software Frequency Select Bit 6 = Frequency Select 0 Bit 5 = Frequency Select 1 Bit 4 = Frequency Select 0

  1. Please note that all clocks can also be individually (asynchronously) enabled or stopped

via the 2-wire I2C control interface. In this case all clocks are stopped in the low state. Figure 1. PD# Timing Diagram 11 is input PD#. When MODE = 1, this function is not available). the power consumption. All clocks are stopped in the low state. outputs are either enabled or disabled. See Figure 1 below.

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1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1 2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 12345678901 2 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 PS8164B 03/15/99 PI6C104 Spread Spectrum Clock Synthesizer for Desktop Pentium II Pericom Semiconductor Corporation 2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com 28-Pin SSOP Package Data SEATING PLANE .050 BSC 0-8˚ .2914 .2992 X.XX X.XX DENOTES DIMENSIONS IN MILLIMETERS 7.40 7.60 .6969 .7125 17.70 18.10 1.27 .0926 .1043 2.35 2.65 .394 .419 10.00 10.65 .0040 .0118 0.10 0.30 .013 .020 0.33 0.51 .010 .029 0.254 0.737 .0091 .0125 0.23 0.32 0.41 1.27 .016 .050 x 45˚ .021 .031 0.533 0.787 REF 28-Pin SOIC Package Data

Ordering Information

H401C6IPe gakcaPPOSSnip-82 S401C6IPe gakcaPCIOSnip-82 /K2E/K33/K39/K30 /K2E/K34/K31/K33 /K2E/K30/K37/K38 /K2E/K30/K30/K32 /K53/K45/K41/K54/K49/K4E/K47 /K50/K4C/K41/K4E/K45 /K2E/K30/K30/K39/K38 /K4D/K61/K78/K2E /K2E/K30/K32/K35/K36 /K42/K53/K43 /K2E/K30/K32/K32 /K2E/K30/K33/K37 /K2E/K30/K30/K34 /K2E/K30/K30/K39 /K2E/K32/K39/K31 /K2E/K33/K32/K32 /K2E/K31/K39/K37 /K2E/K32/K32/K30 /K30/K2E/K32/K35 /K58/K2E/K58/K58 /K58/K2E/K58/K58 /K44/K45/K4E/K4F/K54/K45/K53 /K44/K49/K4D/K45/K4E/K53/K49/K4F/K4E/K53 /K49/K4E /K4D/K49/K4C/K4C/K49/K4D/K45/K54/K45/K52/K53 /K30/K2E/K30/K35/K30 /K37/K2E/K34/K30 /K38/K2E/K32/K30 /K30/K2E/K35/K35 /K30/K2E/K39/K35 /K30/K2E/K30/K39 /K30/K2E/K32/K35 /K35/K2E/K30/K30 /K35/K2E/K36/K30 /K32/K2E/K30 /K39/K2E/K39/K30 /K31/K30/K2E/K35/K30 /K30/K2E/K36/K35 /K4D/K61/K78 /K4D/K69/K6E