PI6C100

PI6C100 PERICOM | Alldatasheet

Document overview

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• PDF pages: 13

Technical content

Features

• Four copies of CPU clock with VDD of 2.5V + 5% • 100 MHz or 66 MHz operation • Eight copies of PCI clock, (synchronous with CPU clock) 3.3V • Two copies of IO APIC clock @14.31818 MHz • Two copies of 48 MHz clock • Three copies of Ref. clock @14.31818 MHz (3.3V TTL) • Low cost 14.31818 MHz crystal oscillator input • Spread spectrum modulation of CPU and PCI clocks for reduced EMI • Power management control • Isolated core VDD, VSS pins for noise reduction • 48-pin SSOP package (V48)

Description

The PI6C100 is a high-speed low-noise clock generator designed to work with the PI6C180 clock buffer to meet all clock needs for Intel Architecture platforms. CPU and chipset clock frequencies of 66.6 MHz and 100 MHz are supported. Split supplies of 3.3V and 2.5V are used. The 3.3V power supply powers a portion of the I/O and the core. The 2.5V is used to power the remaining outputs. 2.5V signaling follows JEDEC standard 8-X. Power sequencing of the 3.3V and 2.5V supplies is not required. An asynchronous PWRDWN# signal may be used to orderly power down (or up) the system. 48-Pin V48 /K50/K43/K49/K43/K4C/K4B/K5B/K31/K3A/K37/K5D /K43/K50/K55/K43/K4C/K4B/K5B/K30/K3A/K33/K5D /K52/K45/K46/K5B/K30/K3A/K32/K5D /K56/K44/K44/K52/K45/K46 /K56/K44/K44/K41/K50/K49/K43 /K33 /K41/K50/K49/K43/K30/K2C/K31 /K52/K45/K46 /K4F/K53/K43 /K56/K44/K44/K43/K50/K55 /K30/K2C/K31 /K43/K50/K55/K53/K54/K4F/K50/K23 /K34 /K37 /K56/K44/K44/K50/K43/K49 /K30/K2C/K31 /K50/K43/K49/K43/K4C/K4B/K5F/K46 /K50/K43/K49/K53/K54/K4F/K50/K23 /KF7/K32 /K50/K4C/K4C/K31 /K56/K44/K44/K34/K38/K4D/K48/K7A /K32/K34/K38/K4D/K48/K7A/K50/K4C/K4C/K32 /K53/K45/K4C/K30/K2C/K31 /K53/K50/K52/K45/K41/K44/K23 /K58/K54/K41/K4C/K5F/K4F/K55/K54 /K58/K54/K41/K4C/K5F/K49/K4E /K42/K75/K66/K66/K65/K72/K73 /K32 /K53/K45/K4C/K31/K30/K30/K2F/K36/K36/K23

1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 PS8142A 10/13/98 PI6C100 Precision Clock Synthesizer for Desktop PC’s Pin Description niPe maNlangiSe pyT. ytQn oitpircseD 74,2,1] 2:0[FERO 3 . tuptuokcolczHM813.41 3V FERSS dnuorg1 s tuptuo]2:0[FERrofdnuorG 84V FERDD rewop1 s tuptuo]2:0[FERrofrewoP 4N I_LATXI 1 . tupnilatsyrczHM813.41 5T UO_LATXO 1 . tuptuolatsyrczHM813.41 81,21,6V ICPSS ]2:0[d nuorg3 s tuptuokcolcICProfdnuorG 7F _KLCICPO 1 t uptuokcolcICPgninnureerF 51,9V ICPDD ]1:0[r ewop2 s tuptuokcolcICProfrewoP ,31,11,01,8 71,61,41 ]7:1[KLCICPO 7 LTT,stuptuokcolcICP V3.3elbitapmoc 33,91V EROCDD ]1:0[r ewop2 e rocrofrewopdetalosI 23,02V EROCSS ]1:0[d nuorg2 e rocrofdnuorgdetalosI 12V DD zHM84r ewop1 s tuptuozHM84rofrewopdetalosI 42V SS zHM84d nuorg1 s tuptuozHM84rofdnuorgdetalosI 32,22z HM84O 2 s tuptuozHM84 72,62] 1:0[LES1 2 s levelLTTVL.sniptcelescigoL 52# 66/001LESI 1 zHM66rozHM001gnilbanerofniptceleS zHM66=L.zHM001=H 92# NWDRWPI 1 W OLdlehnehwecivednwodsrewoP 03# POTSUPCI W OLdlehfiWOLskcolcUPCspotS 13# POTS_ICPI 1 W OLdlehfiWOLskcolcICPspotS 14,73V UPCDD ]1:0[r ewop2 s tuptuoUPCrofrewoP 83,43V UCPSS ]:0[d nuorg2 s tuptuoUPCrofdnuorG 04,93,63,53] 3:0[KLCUPCO 4 V 5.2stuptuokcolctsoHdnaUPC 34V CIPASS dnuorg1 s tuptuoCIPArofdnuorG 64V CIPADD rewop1 s tuptuoCIPArofrewoP 54,44] 1:0[CIPAO 2 z HM81813.41.V5.2@stuptuoCIPA 82# DAERPSI 1 W OLnehwerutaefmurtcepSdaerpSselbanE 24C N— 1 n oitacifidomerutufrofdevreseR

1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 PS8142A 10/13/98 PI6C100 Precision Clock Synthesizer for Desktop PC’s Select Functions Note: TCLK is a test clock over driven on the XTAL_IN input during test mode. noitcnuF noitpircseD stuptuO UPCF ICP,ICPz HM84] 2:0[FERC IPAOI Z-iHZ -iHZ -iHZ -iHZ -iHZ -iH edoMtseT2 /KLCT6 /KLCT2 /KLCTK LCTK LCT Clock Enable Configuration #66/001LES1 LES0 LESn oitcnuF 00 0 Z -iH 00 1 d evreseR 01 0 d evreseR 01 1 e vitcazHM66 10 0 e domtseT 10 1 d evreseR 11 0 d evreseR 11 1 e vitcazHM001 #POTS_UPC# POTS_ICP# NWD_RWPK LCUPCK LCICP rehtO skcolC latsyrCs ’OCV XX0 w olw old eppotSf fof fo 001 w olw olg ninnurg ninnurg ninnur 01 1 w olz HM33g ninnurg ninnurg ninnur 101 66/001 zHM wolg ninnurg ninnurg ninnur 111 66/001 zHM zHM33g ninnurg ninnurg ninnur

1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 PS8142A 10/13/98 PI6C100 Precision Clock Synthesizer for Desktop PC’s Power Management Timing Notes: 1. Clock on/off latency is defined as the number of rising edges of free running PCICLKs between when the clock disable goes low/high to when the first valid clock comes out of the device. 2. Power up latency is from when PWR_DWN# goes inactive (high) to when the first valid clocks are driven from the device. CPU_STOP# is an input signal used to turn off the CPU clocks for low power operation. CPU_STOP# is asserted asynchronously by the external clock control logic with the rising edge of free running PCI clock and is internally synchronized to the external PCICLK_F output. CPU_STOP# Timing Diagram Notes: 1. All timing is referenced to the CPUCLK. 2. The Internal label means inside the chip and is a reference only. 3 CPU_STOP# is an input signal that is made synchronous to the free running PCICLK_F. 4. ON/OFF latency shown is 2 CPU clocks. langiSe tatSlangiS ycnetaL KLCICPgninnureerffosegdegnisirfo.oN #POTS_UPC) delbasid(01 )delbane(11 #POTS_ICP) delbasid(01 )delbane(11 #NWD_RWP) noitarepolamron(1s m3 nwodrewop(0. xam2 All other clocks continue to run while the CPU clocks are disabled. The CPU clocks are always stopped in a low state and started guaranteeing that the high pulse width is a full pulse. CPU clock on latency is 2 or 3 CPU clocks and CPU clock off latency is 2 or 3 CPU clocks. /K43/K50/K55/K43/K4C/K4B /K28/K49/K6E/K74/K65/K72/K6E/K61/K6C/K29 /K43/K50/K55/K43/K4C/K4B /K28/K49/K6E/K74/K65/K72/K6E/K61/K6C/K29 /K50/K43/K49/K43/K4C/K4B/K5F/K46 /K28/K46/K72/K65/K65/K2D/K72/K75/K6E/K6E/K69/K6E/K67/K29 /K43/K50/K55/K5F/K53/K54/K4F/K50/K23 /K50/K43/K49/K5F/K53/K54/K4F/K50/K23 /K50/K57/K52/K5F/K44/K57/K4E/K23 /K43/K50/K55/K43/K4C/K4B /K28/K45/K78/K74/K65/K72/K6E/K61/K6C/K29

1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 PS8142A 10/13/98 PI6C100 Precision Clock Synthesizer for Desktop PC’s PCI_STOP# is an input signal used to turn off the PCI clocks for low power operation. PCI clocks are stopped in the low state and started with a guaranteed full high pulse width. There is ONLY one rising edge of external PCICLK after the clock control logic. Notes: 1. All timing is referenced to the CPUCLK. 2. The Internal label means inside the chip and is a reference only. PCI_STOP# Timing Diagram Notes: 1. All timing is referenced to the CPUCLK. 2. The Internal label means inside the chip and is a reference only. 3. PWR_DWN# is an asynchronous input and metastable conditions could exist. The signal is synchronized inside the part. 4. The shaded sections on the VCO and the Crystal signals indicate an active clock. PWR_DWN# Timing Diagram The PWR_DWN# is used to place the device in a very low power state. PWR_DWN# is an asynchronous active low input. Internal clocks are stopped after the device is put in power down mode. The power on latency is less than 3ms. PCI_STOP# and CPU_STOP# are “don’t cares” during the power down operations. The REF0 clock is stopped in the LOW state as soon as possible. /K43/K50/K55/K43/K4C/K4B /K28/K49/K6E/K74/K65/K72/K6E/K61/K6C/K29 /K50/K43/K49/K43/K4C/K4B /K28/K49/K6E/K74/K65/K72/K6E/K61/K6C/K29 /K50/K43/K49/K43/K4C/K4B/K5F/K46 /K28/K46/K72/K65/K65/K2D/K72/K75/K6E/K6E/K69/K6E/K67/K29 /K43/K50/K55/K5F/K53/K54/K4F/K50/K23 /K50/K43/K49/K5F/K53/K54/K4F/K50/K23 /K50/K57/K52/K5F/K44/K57/K4E/K23 /K50/K43/K49/K43/K4C/K4B /K28/K45/K78/K74/K65/K72/K6E/K61/K6C/K29 /K43/K50/K55/K43/K4C/K4B /K28/K49/K6E/K74/K65/K72/K6E/K61/K6C/K29 /K50/K43/K49/K43/K4C/K4B /K28/K49/K6E/K74/K65/K72/K6E/K61/K6C/K29 /K56/K43/K4F /K50/K57/K52/K5F/K44/K57/K4E/K23 /K43/K50/K55/K43/K4C/K4B /K28/K45/K78/K74/K65/K72/K6E/K61/K6C/K29 /K50/K43/K49/K43/K4C/K4B /K28/K45/K78/K74/K65/K72/K6E/K61/K6C/K29 /K43/K72/K79/K73/K74/K61/K6C

1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 PS8142A 10/13/98 PI6C100 Precision Clock Synthesizer for Desktop PC’s Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) sretemaraPn oitpircseDs noitidnoCtseT. niM. pyT. xaMs tinU I LI tnerruCegakaeLtupnIV <V0 NI V< DD 5-5 + mA V LI egatloVwoLtupnIV SS 3.0-8 .0 V V HI egatloVhgiHtupnIV @ DD 0.2+V DD 3.0+ V LO egatloVwoLtuptuOI LO V,Am1= DD .niM=4 .0 V HO egatloVhgiHtuptuOI LO V,Am1-= DD .niM=2 I 2QDD tnerruCylppuSV5.2 V 2QDD 0=#NWDRWP,V526.2= C DAOL .xaM= 001 mA I 2QDD V 2QDD zHM66.66@V526.2= C DAOL .xaM= 27 Am I 2QDD V 2QDD zHM001@V526.2= C DAOL .xaM= 001 I 3QDD tnerruCylppuSV3.3 V 3QDD 0=#NWDRWP,V564.3= C DAOL .xaM= 005 mA I 3QDD V 3QDD zHM66.66,V564.3= C DAOL .xaM= 071 Am I 3QDD V 3QDD zHM001,V564.3= C DAOL .xaM= 071 C NI ecnaticapaCtupnI 5 Fp C TUO ecnaticapaCtuptuO 6 L NIP ecnatcudnoCniP 7H n TA erutarepmeTtneibmAw olfriAoN0 0 7C °

1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 PS8142A 10/13/98 PI6C100 Precision Clock Synthesizer for Desktop PC’s DC Operating Specifications lobmySs retemaraPs noitidnoC. niM. xaMs tinU V,egatloVtupnI EROCDD ]1-0[% 5–V3.3= V 3HI egatlovhgihtupnIV EROCDD 0.2V EROCDD 3.0+ V V 3LI egatlovwoltupnIV SS 3.0-8 .0 I LI tnerrucegakaeltupnIV <0 NI V< EROCDD 5-5 + mA V%5–V5.2=egatloVtuptuO CIPADD ,V UPCDD ]1-0[ V 2HO egatlovhgihtuptuOI HO Am1-=0 .2 V V 2LO egatlovwoltuptuOI LO Am1=4 .0 V%5–V3.3=egatloVtuptuO FERDD V 3HO egatlovhgihtuptuOI HO Am1-=4 .2 V V 3LO egatlovwoltuptuOI LO Am1=4 .0 V%5–V3.3=egatloVtuptuO IPCDD ]1-0[ V HOP egatlovhgihtuptuosuBICPI HO Am1-=4 .2 V V LOP egatlovwoltuptuosuBICPI LO Am1=5 5.0 C NI ecnaticapacniptupnI5 FpC LATX X LAT ecnaticapacsnip5 .310 .815 .22 C TUO ecnaticapacniptuptuO6 L NIP ecnatcudnIniP7 H n TA erutarepmeTtneibmAw olfriaoN0 0 7C °

1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 PS8142A 10/13/98 PI6C100 Precision Clock Synthesizer for Desktop PC’s Type 1: CPU Clock Buffers (2.5V) lobmySs retemaraPs noitidnoC. niM. pyT. xaMs tinU I NIMHO tnerrucpu-lluPV TUO V4.1=6 3- Am I XAMHO tnerrucpu-lluPV TUO V5.2=1 2- I NIMLO tnerrucnwod-lluPV TUO V0.1=6 3 I XAMLO tnerrucnwod-lluPV TUO V2.0=1 3 t HR etaregdeesirtuptuo2epyTV5.2V 0.2-V4.0@%5–V5.21 4 sn/V t HF etaregdellaftuptuo2epyTV5.2V 4.0-V0.2@%5–V5.21 4 lobmySs retemaraPs noitidnoC. niM. pyT. xaMs tinU I NIMHO tnerrucpu-lluPV TUO V0.1=7 2- Am I XAMHO tnerrucpu-lluPV TUO V573.2=7 2- I NIMLO tnerrucnwod-lluPV TUO V2.1=7 2 I XAMLO tnerrucnwod-lluPV TUO V3.0=0 3 t HR etaregdeesirtuptuo1epyTV5.2V 0.2-V4.0@%5-/+V5.21 4 sn/V t HF etaregdellaftuptuo1epyTV5.2V 4.0-V0.2@%5-/+V5.21 4 Type 2: APIC Buffers (2.5V) Type 3: 48MHz, REF Buffers (3.3V) lobmySs retemaraPs noitidnoC. niM. pyT. xaMs tinU I NIMHO tnerrucpu-lluPV TUO V0.1=9 2- Am I XAMHO tnerrucpu-lluPV TUO V531.3=3 2- I NIMLO tnerrucnwod-lluPV TUO V59.1=9 2 I XAMLO tnerrucnwod-lluPV TUO V4.0=7 2 sn/V Buffer Specifications emaNreffuBV DD )V(egnaR( ecnadepmI WWWWW )e pyTreffuB UPC5 26.2-573.25 4-5.311 epyT CIPA5 26.2-573.20 3-92 epyT FER,zHM845 64.3-531.30 6-023 epyT ICP5 64.3-531.35 5-214 epyT

1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 PS8142A 10/13/98 PI6C100 Precision Clock Synthesizer for Desktop PC’s AC Timing otkcolCtsoH.1erugiF tesffOKLCICP sretemaraP zHM66z HM001 stinU .niM. xaM. niM. xaM sn t HKH )V5.2(e mithgihKLCtsoH2 .50 .3 t LKH )V5.2(e mitwolKLCtsoH0 .58 .2 t RETTIJ )V5.2(r ettiJKLCtsoH0 520 52s p )V5.2(elcyCytuDV 52.1taderusaeM5 45 55 45 5% t WKSH )V5.2(w ekSKLCsuBtsoH5 715 71 sp t WKSOI wekSKLCsuBCIPAOI0 520 52 t LZP t, HZP yaledelbanetuptuO0 .10 .80 .10 .8 sn t ZLP t, ZHP yaledelbasidtuptuO0 .10 .80 .10 .8 t BTSH pu-rewopmorfnoitazilibatSKLCtsoH3 3 s m t PKP doirepKLCICP0 .03 µ 0.03 µ sn t SPKP ytilibatsdoirepKLCICP0 050 05s p t HKP emithgihKLCICP0 .210 .21 sn t LKP emitwolKLCICP0 .210 .21 t WKSP wekSKLCsuBICP0 050 05s p t TESFFOPH tesffOkcolCICPottsoH5 .10 .45 .10 .4s n t BTSP pu-rewopmorfnoitazilibatSKLCICP3 3 s m lobmySs retemaraPs noitidnoC. niM. pyT. xaMs tinU I NIMHO tnerrucpu-lluPV TUO V0.1=3 3- Am I XAMHO tnerrucpu-lluPV TUO V531.3=3 3- I NIMLO tnerrucnwod-lluPV TUO V59.1=0 3 I XAMLO tnerrucnwod-lluPV TUO V4.0=8 3 t HR etaregdeesirtuptuo4epyTV3.3V 4.2-V4.0@%5–V3.31 4 sn/V t HF etaregdellaftuptuo4epyTV3.3V 4.0-V4.2@%5–V3.31 4 Type 4: PCI Clock Buffers (3.3V)

1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 PS8142A 10/13/98 PI6C100 Precision Clock Synthesizer for Desktop PC’s kcolCd aoL.niMd aoL.xaMs tinUs etoN )KLCH(skcolCUPC0 10 2 Fp sdaol2elbissop,daolecived1 )KLCP(skcolCICP0 30 3s tnemeriuqer1.2ICPsteeM kcolCzHM840 10 2d aolecived1 FER0 10 2d aolecived1 CIPA0 10 2s daolecived2 Minimum and Maximum Expected Capacitive Loads Notes: 1. Maximum rise/fall times are guaranteed at maximum specified load for each type of output buffer. 2. Minimum rise/fall times are guaranteed at minimum specified load for each type of output buffer. 3. Rise/fall times are specified with pure capacitive load as shown. Testing is done with an additional 500W resistor in parallel. Design Guidelines to Reduce EMI 1. Place series resistors and CI capacitors as close as possible to the respective clock pins. Typical value for CI is 10pF. Series resistor value can be increased to reduce EMI provided that the rise and fall time are still within the specified values. 2. Minimize the number of “vias” of the clock traces. 3. Route clock traces over a continuous ground plane or over a continuous power plane. Avoid routing clock traces from plane to plane (refer to rule #2). 4. Position clock signals away from signals that go to any cables or any external connectors. /K43/K50/K55/K43/K4C/K4B /K50/K43/K49/K43/K4C/K4B /K52/K45/K46 /K41/K50/K49/K43 /K34/K38/K4D/K48/K5A /K33/K33W /K33/K33W /K32/K32W /K2F/K33/K33W /K33/K33W /K32/K32W /K34 /K38 /K33 /K32 /K32 /K43/K4C /K43/K4C /K43/K4C /K43/K4C /K43/K4C /K50/K49/K36/K43/K31/K30/K30 /K31 /K44/K65/K76/K69/K63/K65 /K6C/K6F/K61/K64 /K4D/K65/K65/K74/K73 /K50/K43/K49/K32/K2E/K31 /K52/K65/K71/K2E /K31 /K44/K65/K76/K69/K63/K65 /K6C/K6F/K61/K64 /K32 /K44/K65/K76/K69/K63/K65 /K6C/K6F/K61/K64/K73 /K31 /K44/K65/K76/K69/K63/K65 /K6C/K6F/K61/K64

1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 PS8142A 10/13/98 PI6C100 Precision Clock Synthesizer for Desktop PC’s PCB Layout Suggestion Note: This is only a suggested layout. There may be alternate solutions depending on actual PCB design and layout. As a general rule, C2-C11 should be placed as close as possible to their respective V DD. Recommended capacitor values: /K43/K32 /K43/K33 /K43/K34 /K43/K35 /K43/K36 /K46/K42/K32 /K43/K31/K30 /K43/K39 /K43/K38 /K43/K37 /K43/K31/K31 /K56/K43/K43 /K28/K43/K50/K55/K29 /K43/K31/K32 /K32/K32/K75/K46 /K56/K69/K61 /K74/K6F /K56/K44/K44 /K50/K6C/K61/K6E/K65 /K56/K69/K61 /K74/K6F /K47/K4E/K44 /K50/K6C/K61/K6E/K65 /K56/K6F/K69/K64 /K69/K6E /K50/K6F/K77/K65/K72 /K50/K6C/K61/K6E/K65 /K31 /K32 /K33 /K34 /K35 /K36 /K37 /K38 /K39 /K31/K30 /K31/K31 /K31/K32 /K31/K33 /K31/K34 /K31/K35 /K31/K36 /K31/K37 /K31/K38 /K31/K39 /K32/K30 /K32/K31 /K32/K32 /K32/K33 /K32/K34 /K34/K38 /K34/K37 /K34/K36 /K34/K35 /K34/K34 /K34/K33 /K34/K32 /K34/K31 /K34/K30 /K33/K39 /K33/K38 /K33/K37 /K33/K36 /K33/K35 /K33/K34 /K33/K33 /K33/K32 /K33/K31 /K33/K30 /K32/K39 /K32/K38 /K32/K37 /K32/K36 /K32/K35 /K56/K53/K53 /K56/K53/K53 /K56/K44/K44 /K56/K53/K53 /K56/K44/K44 /K56/K53/K53 /K56/K44/K44 /K56/K53/K53 /K56/K53/K53 /K56/K44/K44 /K56/K44/K44 /K56/K44/K44 /K56/K44/K44 /K56/K44/K44 /K56/K53/K53 /K56/K53/K53 /K56/K44/K44 /K56/K53/K53 /K56/K53/K53 /K46/K42/K31 /K56/K43/K43 /K43/K31 /K32/K32/K75/K46

1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 PS8142A 10/13/98 PI6C100 Precision Clock Synthesizer for Desktop PC’s Pericom Semiconductor Corporation 2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com 48-Pin SSOP Package Data Table of Dimensions ydoB) htdiW(E) htgneL(D) thgieH(A) hctipniP-ot-niP(e )lim003(. xaM9 92.00 36.00 11.0-

Ordering Information

V001C6IPe gakcaPPOSSnip-84 7.39 7.59 0.20 0.51 1.01 0.25 0.381 0.635 .008 .008 .0160-8˚ 0.20 0.40 .1102.79 .010 Gauge Plane .02 .04 .015 .025 x 45˚ X.XX X.XX DENOTES DIMENSIONS IN MILLIMETERS .025 BSC 0.635 .291 .299 X.XX X.XX DENOTES DIMENSIONS IN MILLIMETERS .395 .420 10.03 10.67 .620 .630 15.75 16.00 .008 .0135 0.20 0.34 Nom. Max