PI5USB2544A PERICOM | Alldatasheet
Document overview
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Technical content
Features
Two separate current limiting channels Supports CDP/DCP Modes per USB Battery Charging Specification 1.2 Supports Shorted Mode per Chinese Telecommunication Industry Standard YD/T1591-2009 Supports non-BC1.2 Charging Modes by Automatic Selection Divider-1A mode Divider-2A mode Divider-2.4A mode DCP-1.2V mode Supports Sleep-Mode Charging and Mouse/Keyboard Wake up Automatic SDP/CDP Switching for Devices that do not request for the CDP Ports Load Detection for Power Supply Control in S4/S5 Charging and Port Power Management in all Charge Modes Compatible with USB 2.0/3.0 Power Switch requirements Integrated 73-mΩ (Typ.) High-Side MOSFET Adjustable Current-Limit up to 3A(Typ.) Operating Range:4.5V to 5.5V Max Device Current 2μA at Device Disabled 270μA at Device Enabled Device Package: TQFN 3.0x3.0-16L
Description
The PI5USB 2544A/2546A series is a USB charging port controller and power switch with an integrated USB 2.0 high - speed data line (D+/D –) switch. PI5USB 2544A/2546A provides the electrical signatures on D+/D – to support charging schemes listed under device feature section. This series is compatible with both popular BC1.2 compliant and non-BC1.2 compliant devices. System wake up (from S3) with a mouse/keyboard (both low speed and full speed) is fully supported in the PI5USB2544A/2546A. Additionally, PI5USB2546A supports two distinct power management features , namely, power wake and port power management (PPM) through /STATUS pin. Power wake allows for power supply control in S4/S5 charging and PPM manage s port power in a multi - port application. The PI5USB2544A/2546A series 73-mΩ power -distribution switch is intended for applications where heavy capacitive loads and short -circuits are likely to be encountered. Two programmable current thresholds provide flexibility for setting current limits and load detect thresholds
Applications
USB Ports (Host and Hubs) Notebook and Desktop PCs Universal Wall Charging Adapters Pin Configuration (TQFN-16L, ZH) PI5USB2544A PI5USB2546A
2015-08-0012 PT0513-3 8/31/15 PI5USB2544A, PI5USB2546A USB Charging Port Controller and Load Detection Power Switch Pin Description Pin # Name Type Description 1 IN P Input voltage and supply voltage; connect 0.1μF or greater ceramic capacitor from IN to GND as close to the device as possible 2 DM_OUT I/O D- Data line to USB host controller. 3 DP_OUT I/O D+ data line to USB host controller.
4 ILIM_SEL I
Logic-level input signal used to control the charging mode, current limit threshold, and load detection, see the control truth table. Can be tied directly to IN or GND without pull-up or pull-down resistor.
5 EN I
Logic-level input for turning the power switch and the signal switches on/off, logic low turns off the signal and power switches and holds OUT in discharger. Can be tied directly to IN or GND without pull-up or pull-down resistor.
6 CTL1 I
Logic-level inputs used to control the charging mode and signal switches; see the control truth table. Can be tied directly to IN or GND without pull-up or pull-down resistor.
7 CTL2 I
8 CTL3 I
O Active-low open-drain output, asserted in load detection conditions (PI5USB2546A). NC -- Connect to GND or leave open (PI5USB2544A). 10 DP_IN I/O D+ data line to downstream connector. 11 DM_IN I/O D- data line to downstream connector.
12 OUT P Power-switch output
FAULT O Active-low open -drain output, asserted when over-temperature or current limit conditions 14 GND G Ground connection.
15 ILIM_LO I
External resistor connection used to set the low current-limit threshold and the load detection current threshold. A resistor to ILIM_L O is optional; see Current -Limit Settings. 16 ILIM_HI I External resistor connection used to set the high current-limit threshold. NA Exposed PAD G Internally connected to GND. Thermal pad to heat-sink the part to the circuit board. * I = Input; O = Output; P = Power; G = Ground PI5USB2544A/2546A series Charging Detection Supports Table Part Number Non- BC1.2 Charging Mode Load Detection DCP-1.2V Divider-1A Divider-2A Divider-2.4A
2015-08-0012 PT0513-3 8/31/15 PI5USB2544A, PI5USB2546A USB Charging Port Controller and Load Detection Power Switch Maximum Ratings Continuous current in SDP or CDP mode Recommended Operating Conditions Symbol Parameter Min. Typ. Max. Unit VIN Input Voltage, IN 4.5 - 5.5 V Input Voltage, logic-level EN, CTL1, CTL2, CTL3, ILIM_SEL inputs 0 - 5.5 V Input Voltage, data line inputs, DP_IN, DM_IN, DP_OUT, DM_OUT 0 - VIN V VIH High-level input voltage, EN, CTL1, CTL2, CTL3, ILIM_SEL 1.8 - - V VIL Low-level input voltage, EN, CTL1, CTL2, CTL3, ILIM_SEL - - 0.8 V VIH High-level input voltage 3.5 - - V VIL Low-level input voltage - - 0.8 V Continuous current data line inputs, SDP or CDP mode, DP_IN to DP_OUT or DM_IN to DM_OUT - - ± 30 mA Continuous current data line inputs, BC1.2 DCP mode, DP_IN to DM_IN - - ± 15 mA IOUT Continuous output current, OUT 0 - 2.5 A Continuous output sink current, /FAULT, /STATUS (PI5USB2546A) 0 - 10 mA RILI M_XX Current-limit set resistor 16.9 - 750 kΩ TA Ambient Temperature Range -40 - 85 ºC TJ Operating Virtual Junction Temperature Range -40 - 125 ºC Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of thi s specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2015-08-0012 PT0513-3 8/31/15 PI5USB2544A, PI5USB2546A USB Charging Port Controller and Load Detection Power Switch
Electrical Characteristics
4.5V≤VIN≤5.5V; TJ=-40°C to +125°C; VEN =VIN, VILIM_SEL=VIN, VCTL1= VCTL2= VCTL3=VIN, R/FAULT=R/STATUS=10kΩ, RILIM_HI=20kΩ, Symbol Parameter Test Conditions Min Typ. Max Unit Power Switch RDS(on) On Resistance(1) TJ = 25oC, IOUT = 2A 73 84 mΩ -40oC ≤ TJ ≤ 85oC, IOUT = 2A 73 105 -40oC ≤ TJ ≤ 125oC, IOUT = 2A 73 120 tr OUT voltage rise time VIN = 5V, CL = 1μF, RL = 100Ω 0.7 1.0 1.60 ms tf OUT voltage fall time 0.2 0.35 0.5 ton OUT voltage turn-on time VIN = 5V, CL = 1μF, RL = 100Ω 2.7 4 ms toff OUT voltage turn-off time 1.7 3 IREV Reverse leakage current VOUT = 5.5V, VIN = VEN = 0V, -40oC ≤ TJ ≤ 85oC, Measure IOUT 2 μA Discharge RDCHG OUT discharge resistance VOUT = 4V, VEN = 0V 400 500 630 Ω tDCHG OUT discharge hold time Time VOUT< 0.7V 1.30 2.0 2.9 s EN, ILIM_SEL, CTL1,CTL2, CTL3, inputs Input pin rising logic threshold voltage - 1 1.35 1.70 V Input pin falling logic threshold voltage - 0.85 1.15 1.45 V Hysteresis(2) - - 200 - mV Input current Pin voltage= 0V to 5.5V -0.5 - 0.5 µA (1) Pulse-testing techniques maintain junction temperature close to ambient temperature; Thermal effects must be taken into account separately (2) These parameters are provided for reference only and do not constitute part of Pericom's published device specifications for purposes of Pericom's product warranty
2015-08-0012 PT0513-3 8/31/15 PI5USB2544A, PI5USB2546A USB Charging Port Controller and Load Detection Power Switch 4.5V≤VIN≤5.5V; TJ=-40°C to +125°C; VEN =VIN, VILIM_SEL=VIN, VCTL1= VCTL2= VCTL3=VIN, R/FAULT=R/STATUS=10kΩ, RILIM_HI=20kΩ, Symbol Description Test Conditions Min. Typ. Max. Unit ILIM_SEL Current Limit IOS OUT Current-limit(2) VILIM_SEL= 0 V RILIM_LO=210kΩ 205 240 275 mA VILIM_SEL= 0 V RILIM_LO=80.6kΩ 575 625 680 VILIM_SEL= 0 V RILIM_LO=22.1kΩ 2120 2275 2430 VILIM_SEL= VIN RILIM_HI=20kΩ 2340 2510 2685 VILIM_SEL= VIN RILIM_HI=16.9kΩ 2770 2970 3170 tIOS Response time to OUT short circuit(1) VIN = 5.0V, R=0.1Ω, lead length=2” - 1.5 - s Supply Current IIN_OFF Disabled IN supply current VEN=0V, VOUT=0V, TJ =-40°C to +125°C - 0.1 2 IIN_ON Enable IN supply current VCTL1=VCTL2= VIN, VCTL3= 0V VILIM_SEL = 0V - 165 220 VCTL1 = VCTL2 = VCTL3 = VIN, VILIM_SEL = 0V - 175 230 VCTL1 = VCTL2 = VIN, VCTL3 = 0V, VILIM_SEL = VIN - 185 240 VCTL1 = VCTL2 = VCTL3 = VIN, VILIM_SEL = VIN - 195 250 VCTL1 = 0V, VCTL2 = VCTL3 = VIN, VILIM_SEL = 0V - 215 270 VCTL1 = 0V, VCTL2 = VCTL3 = VIN, VILIM_SEL = VIN - 240 290 Undervoltage Lockout VUVLO IN rising UVLO threshold voltage - 3.9 4.1 4.3 V Hysteresis(1) - - 100 - mV /FAULT VOL Output low voltage I/FAULT = 1mA - - 100 mV IOFF Off-state leakage current V/FAULT = 5.5V - - 1 A TD Over current /FAULT rising and falling deglitch - 5 8.2 12 ms /STATUS (PI5USB2546A) VOL Output low voltage I/STATUS = 1mA - - 100 mV IOFF Off-state leakage V/STATUS = 5.5V - - 1 A Thermal Shutdown OTSD Thermal shutdown threshold - 170 - °C Hysteresis(1) - - 20 - Note: (1) These parameters are provided for reference only and do not constitute part of Pericom's published device specifications for purposes of Pericom's product warranty (2) Pulse-testing techniques maintain junction temperature close to ambient temperature; current limit value tested at 80% output voltage. Thermal effects must be taken into account separately.
2015-08-0012 PT0513-3 8/31/15 PI5USB2544A, PI5USB2546A USB Charging Port Controller and Load Detection Power Switch Electrical Characteristics, High-bandwidth Switch 4.5V≤VIN≤5.5V; TJ=-40°C to +125°C; VEN =VIN, VILIM_SEL=VIN, VCTL1= VCTL2= VCTL3=VIN, R/FAULT=R/STATUS=10kΩ RILIM_HI=20kΩ, Symbol Description Test Conditions Min. Typ. Max. Unit HIGH_BANDWIDTH ANALOG SWITCH DP/DM switch on resistance VDP/DM_OUT= 0V, IDP/DM_IN= 30mA - 2 4 Ω VDP/DM_OUT= 2.4V, IDP/DM_IN= -15mA - 3 6 Ω Switch resistance mismatch between DP/DM channels VDP/DM_OUT= 0V, IDP/DM_IN= 30mA - 0.05 0.15 Ω VDP/DM_OUT= 2.4V, IDP/DM_IN= -15mA - 0.05 0.15 Ω DP/DM switch off-state capacitance(1) VEN=0V, VDP/DM_IN= 0.3V, Vac= 0.6VPK-PK, f=1MHz - 4.5 - pF DP/DM switch on-state capacitance(2) VDP/DM_IN= 0.3V,Vac= 0.6VPK-PK, f = 1MHz - 5.4 6.2 pF OIRR Off-state isolation(3) VEN = 0V, f = 250MHz - 33 - dB XTALK Off-state cross channel isolation(3) f = 250MHz - 52 - dB IOFF Off-state leakage current VEN = 0V, VDP/DM_IN = 3.6V, VDP/DM_OUT = 0V, measure IDP/DM_OUT - 0.1 1.5 A BW Bandwidth(-3dB)(3) RL =50Ω - 2.0 - GHz tpd Propagation delay(3) - - 0.25 - ns tSK Skew between opposite transitions of the same port(tPHL – tPLH) - - 0.1 0.2 ns Note: (1) The resistance in series with the parasitic capacitance to GND is typically 250 Ω. (2) The resistance in series with the parasitic capacitance to GND is typically 150 Ω. (3) These parameters are provided for reference only and do not constitute part of Pericom's published device specifications for purposes of Pericom's product warranty.
2015-08-0012 PT0513-3 8/31/15 PI5USB2544A, PI5USB2546A USB Charging Port Controller and Load Detection Power Switch Electrical Characteristics, Charging Controller 4.5V≤VIN≤5.5V; TJ=-40°C to +125°C; VEN =VIN, VILIM_SEL=VIN, VCTL1= VCTL2= VCTL3=VIN, R/FAULT=R/STATUS=10kΩ RILIM_HI=20kΩ, Symbol Description Test Conditions Min. Typ. Max. Unit SHORTED MODE (BC1.2 DCP) DP_IN/DM_IN shorting resistance VCTL1= VIN; VCTL2= VCTL3= 0V - 125 200 Ω DCP-1.2V MODE DP_IN/DM_IN output voltage VCTL1= 0V; VCTL2= VCTL3= VIN, Apply 3V on DP_IN for 0.5s and measure the D+/D- voltage within the 2s 1.19 1.25 1.31 V DP_IN/DM_IN output impedance 60 75 94 kΩ DIVIDER-1A MODE DP_IN Divider-1A output voltage VCTL1= 0V; VCTL2= VCTL3= VIN, 1.9 2.0 2.1 V DM_IN Divider-1A output voltage 2.57 2.7 2.84 V DP_IN/DM_IN output impedance 7.5 10.5 16 kΩ DIVIDER-2A MODE DP_IN Divider-2A output voltage VCTL1= 0V; VCTL2= VCTL3= VIN; IOUT= 1A 2.57 2.7 2.84 V DM_IN Divider-2A output voltage 1.9 2.0 2.1 V DP_IN/DM_IN output impedance 7.5 10.5 16 kΩ DIVIDER-2.4A MODE DP_IN/DM_IN output voltage VCTL1= 0V; VCTL2= VCTL3= VIN; IOUT = 1.7A 2.57 2.7 2.84 V DP_IN/DM_IN output impedance 7.5 10.5 16 kΩ CHARGING DOWNSTREAM PORT VDM_SRC DP_IN CDP output voltage VCTL1= VCTL2= VCTL3= VIN, VIN =0.6V, -250μA ≤ IDM_IN ≤ 0μA 0.5 0.6 0.7 V VDAT_REF DP_IN rising lower window threshold for VDM_SRC activation VCTL1= VCTL2= VCTL3= VIN 0.25 - 0.4 V Hysteresis(1) - 50 - mV VLGC_REF DP_IN rising upper window threshold for VDM_SRC de-activation 0.8 - 1.5 V Hysteresis(1) - 100 - mV LOAD DETECT- NON POWER WAKE ILD IOUT rising load detect current threshold VCTL1= VCTL2= VCTL3= VIN 550 650 765 mA Hysteresis(1) - 50 - mA tLD_SET Load detect set time 140 200 275 ms Load detect reset time 1.9 3 4.2 s Note: (1) These parameters are provided for reference only and do not constitute part of Pericom's published device specifications for purposes of Pericom's product warranty.
2015-08-0012 PT0513-3 8/31/15 PI5USB2544A, PI5USB2546A USB Charging Port Controller and Load Detection Power Switch Electrical Characteristics, Charging Controller 4.5V≤VIN≤5.5V; TJ=-40°C to +125°C; VEN =VIN, VILIM_SEL=VIN, VCTL1= VCTL2= VCTL3=VIN, R/FAULT=R/STATUS=10kΩ RILIM_HI=20kΩ, Symbol Description Test Conditions Min. Typ. Max. Unit LOAD DETECT- POWER WAKE IOS_PW Power wake short circuit current limit VCTL1= VCTL2= 0V, VCTL3= VIN 20 55 90 mA IOUT falling power wake reset current threshold 10 45 85 mA Reset current hysteresis(1) - 5 - mA Power wake reset time 10.7 15 20.6 s Note: (1) These parameters are provided for reference only and do not constitute part of Pericom's published device specifications for purposes of Pericom's product warranty.
2015-08-0012 PT0513-3 8/31/15 PI5USB2544A, PI5USB2546A USB Charging Port Controller and Load Detection Power Switch Functional Description PI5USB2546A Block Diagram IN ILIM_HI ILIM_LO Current Limit Select Current Limit Charger Pump UVLO 8ms- Deglitch ILIM_SEL EN Discharge OC Thermal Sense 8ms-Deglitch (Falling edge) OTSD Disable+UVLO+ Discharger OUT GND Logic Control DM_OUT DP_OUT DP_IN DM_IN CDP Detection DCP Detection Divider Modes Auto Detection Discharge OC Load Detection Discharge Load Detection CTL1 CTL2 CTL3 STATUS FAULT Driver
2015-08-0012 PT0513-3 8/31/15 PI5USB2544A, PI5USB2546A USB Charging Port Controller and Load Detection Power Switch PI5USB2544A Block Diagram IN ILIM_HI ILIM_LO Current Limit Select Current Limit Charger Pump UVLO 8ms- Deglitch ILIM_SEL EN Discharge OC Thermal Sense 8ms-Deglitch (Falling edge) OTSD Disable+UVLO+ Discharger OUT GND Logic Control DM_OUT DP_OUT DP_IN DM_IN CDP Detection DCP Detection Divider Modes Auto Detection Discharge OC Discharge CTL1 CTL2 CTL3 FAULT Driver
source to charge its batteries. USB ports are a convenient location for charging because of an available 5V power source. current of 900mA to downstream client-side devices. personal media players which need a higher charging rate. Wall adapters can provide much more current than 500mA/900mA. YD/T 1591-2009 is a subset of BC1.2 spec. supported by vast majority of devices that implement USB cha rging. Table 1 shows the differences between these ports. Table 1. Operation Modes
2015-08-0012 PT0513-3 8/31/15 PI5USB2544A, PI5USB2546A USB Charging Port Controller and Load Detection Power Switch Standard Downstream Port (SDP) USB 2.0/USB 3.0 An SDP is a traditional USB port that follows USB 2.0/3.0 protocol and supplies a minimum of 500mA/900mA per port. USB 2.0/3.0 communications is supported, and the host controller must be active to allow charging. PI5USB2544A/2546A supports SDP mode in system power state S0 when system is completely powered ON and fully operational. For more details on control pin (CTL1, CTL2, CTL3 and ILIM_SEL) settings to program this state please refer to device truth table. Charging Downstream Port (CDP) A CDP is a USB port that follows USB BC1.2 and supplies a minimum of 1.5A per port. It provides power and meets USB 2.0 requirements for device enumeration. USB 2.0 communications is supported and the host controller must be active to allow charging. What separates a CDP from an SDP is the host -charge handshaking logic that identifies this port as a CDP. A CDP is identifiable by a compliant BC1.2 client device and allows for additional current draw by the client device. The CDP hand-shaking process is done in two steps. During step one the portable equipment outputs a nominal 0.6V output on its D+ line and reads the voltage input on its D - line. The portable device concludes it is connected to an SDP if the voltage is less than the nominal data detect voltage of 0.3V. The portable device concludes that it is connected to a Charging Port if the D - voltage is greater than the nominal data detect voltage of 0.3V and optionally less than 0.8V. The second step is necessary for portable equipment to determine if it is connected to CDP or DCP. The portable device outputs a nominal 0.6V output on its D - line and reads the voltage input on its D+ line. The portable device concludes it is connected to a CDP if the data line being read remains less than th e nominal data detection voltage of 0.3V. The portable device concludes it is connected to a DCP if the data line being read is greater than the nominal data detect voltage of 0.3V. PI5USB2544A/2546A series supports CDP mode in system power state S0 when s ystem is completely powered ON and fully operational. For more details on control pin (CTL1, CTL2, CTL3 and ILIM_SEL) settings to program this state please refer to device truth table. Dedicated Charging Port (DCP) A DCP only provides power but does not support data connection to an upstream port. As shown in following sections, a DCP is identified by the electrical characteristics of its data lines. The PI5USB2544A/2546A series emulates DCP in two charging states, namely DCP Forced and DCP Auto as shown in Figure 4. In DCP Forced state the device will support one of the two DCP charging schemes, namely Divider -1A or DCP_Shorted. In the DCP Auto state, the device charge detection state machine is activated to selectively implement charging schemes involved with the Shorted DCP mode, Divider -1A, Divider -2A, Divider-2.4A and DCP -1.2V modes. Shorted DCP mode complies with BC1.2 and Chinese Telecommunications Industry Standard YD/T 1591 -2009, while the Divider -1A, Divider -2A, Divider -2.4A and DCP -1.2V modes are employed to charge devices that do not comply with BC1.2 DCP standard. DCP BC1.2 and YD/T 1591-2009 Both standards define that the D+ and D - data lines should be shorted together with a maximum series impedance of 200 Ω. This is shown as Figure 1. Figure 1, DCP mode GND USB Connector 2.0V 1.2V 2.7V CDP Detect Auto Detect D- OUT D+OUT PI5USB2544A/2546A VBUS USB Host/Hub 200Ω
2015-08-0012 PT0513-3 8/31/15 PI5USB2544A, PI5USB2546A USB Charging Port Controller and Load Detection Power Switch DCP Forced Shorted / DCP Forced Divider-1A In this mode the device is permanently set to one of the DCP schemes (BC1.2/ YD/T 1591-2009 or Divider-1A) as commanded by its control pin setting per device truth table. High-Bandwidth Data Line Switch The PI5USB2544A/2546A series passes the D+ and D - data lines through the devi ce to enable monitoring and handshaking while supporting charging operation. A wide bandwidth signal switch is used, allowing data to pass through the device without corrupting signal integrity. The data line switches are turned on in any of CDP or SDP ope rating modes. The EN input also needs to be at logic High for the data line switches to be enabled. NOTE: 1. Under CDP mode, the data switches are ON even while CDP handshaking is occurring. 2. The data line switches are OFF if EN or all CTL pins are held low, or if in DCP mode. They are not automatically turned off if the power switch (IN to OUT) is in current limit. 3. The data switches are for USB 2.0 differential pair only. In the case of a USB 3.0 host, the super speed differential pairs must be routed directly to the USB connector without passing through the PI5USB2544A/2546A series. 4. Data switches are OFF during OUT (VBUS) discharge
2015-08-0012 PT0513-3 8/31/15 PI5USB2544A, PI5USB2546A USB Charging Port Controller and Load Detection Power Switch Device Operation Please refer to the simplified device state diagram below. Power-on-reset (POR) holds device in initial state while output is held in discharge mode. Any POR event will take the device back to initial state. After POR clears, device goes to the next state depending on the CTL1, CTL2, CTL3 and ILIM_SEL lines as shown Figure 5. Figure 5, PI5USB2544A/2546A Charging States Output Discharge To allow a charging port to renegotiate current with a portable device, PI5USB2544A/2546A uses the OUT discharge function. It proceeds by turning off the power switch while discharging OUT, then turning back on the power switch to reassert the OUT voltage. This discharge function is automatically applied as shown in device state diagram. DCP Forced (DCP Shorted or Divider- 1A) Sample CTL PinsDisc Reset Discharge SDP1 CDP SDP2 SDP2 (1110) DCH Not SDP1 CDP (1111) SDP1 (111x/ 010x) CDP (1111) SDP2 (1110) DCH Done DCP_Short Divider-1A DCH/SDP/CDP DCP Auto (DCP Shorted /DCP-1.2V / Divider-1A/2A/2.4A) DCP_Shorted/ Divider-1A DCP_Auto DCH/SDP/CDP Note: 1) All shaded boxed are device charging modes. 2) See below table for CTL settings corresponding to flow line conditions Device Control Pins Flow Line Condition CTL1 CTL2 CTL3 ILIM_SEL DCH(Discharge) 0 0 0 x CDP 1 1 1 1 SDP2(No Discharge from/to CDP) 1 1 1 0 SDP1(Discharge from/to any charging state including CDP) 1 1 0 x 0 1 0 x DCP_Short 1 0 0 x DCP/Divider-1A 1 0 1 x DCP_Auto 0 1 1 x 0 0 1 x DCP_Auto Not SDP2 or CDP
2015-08-0012 PT0513-3 8/31/15 PI5USB2544A, PI5USB2546A USB Charging Port Controller and Load Detection Power Switch Wake on USB Feature (Mouse/Keyboard Wake Feature) USB 2.0 Background Information The PI5USB2544A/2546A data lines interface with USB 2.0 devices. USB 2.0 defines three types of devices according to data rate. These devices and their characteristics relevant to PI5USB2544A/2546A series Wake on USB operation are shown below: Low-speed USB devices 1.5 Mb/s Wired mice and keyboards are examples No devices that need battery charging All signaling performed at 2.0V and 0.8V hi/lo logic levels D- high to signal connect and when placed into suspend D- high when not transmitting data packets Full-speed USB devices 12 Mb/s Wireless mice and keyboards are examples Legacy phones and music players are examples Some legacy devices that need battery charging All signaling performed at 2.0V and 0.8V hi/lo logic levels D+ high to signal connect and when placed into suspend D+ high when not transmitting data packets High-speed USB devices 480 Mb/s Tablets, phones and music players are examples Many devices that need battery charging Connect and suspend signaling performed at 2.0V and 0.8V hi/lo logic levels Data packet signaling performed a logic levels below 0.8V D+ high to signal connect and when placed into suspend (same as a full-speed device) D+ and D- low when not transmitting data packets Wake On USB Wake on USB is the ability of a wake configured USB device to wake a computer system from its S3 sleep state back to its S0 working state. Wake on USB requires the data lines to be connected to the system USB host before the system is placed into it s S3 sleep state and remain continuously connected until they are used to wake the system. The PI5USB2544A/2546A supports low and full speed HID (human interface device like mouse/key board) wake function. There are two scenarios under which wake on mouse are supported by the PI5USB2544A/2546A series. The specific CTL pin changes that the PI5USB2544A/2546A will override are shown below. The informa tion is presented as CTL1 , CTL2 and CTL3.The ILIM_SEL pin plays no role 1. 111 (CDP/SDP2) to 011 (DCP-Auto) 2. 110/010 (SDP1) to 011 (DCP-Auto)
2015-08-0012 PT0513-3 8/31/15 PI5USB2544A, PI5USB2546A USB Charging Port Controller and Load Detection Power Switch USB Low-Speed / Full-Speed Device Recognition PI5USB2544A/2546A series is capable of detecting LS or FS device attachment when PI5USB2544A/2546A is in SDP or CDP mode. Per USB spec when no device is attached, the D+ and D - lines are near ground level. When a low speed compliant device is attached to the PI5USB2544A/2546A charging port, D - line will be pulled high in its idle state (mouse/keyboard not activated). However when a FS device is attached the opposite is true in its idle state, i.e. D+ is pulled high and D- remains at ground level. PI5USB2544A/2546A monitors both D+ and D- lines while CTL pin settings are in CDP or SDP mode to detect LS or FS HID device attachment. To support HID sleep wake, PI5USB2544A/2546A must first determine that it is attached to a LS or FS device when system is in S0 power state. PI5USB2544A/2546A does this as described above. While supporting a LS HID wake is straight forward, supporting FS HID requires making a distinction between a FS and a HS device. This is because a high speed device will always present itself initially as a full speed device (by a 1.5K pull up resistor on D+). The negotiation for high speed then makes the distinction whereby the 1.5K pull up resistor gets removed. PI5USB2544A/2546A handles the distinction between a FS and HS de vice at connect by memorizing if the D+ line goes low after connect. A HS device after connect will always undergo negotiation for HS which will require the 1.5K Ω resistor pull-up on D+ to be removed. To memorize a FS device, PI5USB2544A/2546A requires the device to remain connected for at least 11 sec while system is in S0 mode before placing it in sleep or S3 mode. If system is placed i n sleep mode earlier than the 11 sec window, a FS device may not get recognized and hence could fail to wake system from S3. This requirement does not apply for LS device. No CTL Pin Timing Requirement after Wake Event and Transition from S3 to S0 There is no CTL pin timing requirement for the PI5USB2544A/2546A when the wake configured US B device wakes the system from S3 back to S0.
2015-08-0012 PT0513-3 8/31/15 PI5USB2544A, PI5USB2546A USB Charging Port Controller and Load Detection Power Switch Device Control Pins Truth Table Device Control Pins Table lists all valid bias combinations for the four control pins CTL1, CTL2, CTL3 and ILIM_SEL pins and their corresponding charging mode. It is important to note that the Device Control Pins Table purposely omits matching charging modes of the PI5USB2544A/2546A with global power states (S0 -S5) as device is agnostic to system power states. The PI5USB2544A/2546A monitors its CTL inputs and will transition to whatever charging state it is commanded to go to (except when LS/FS HID device is detected). For example if sleep charging is desired when system is in standby or hibernate state then user must set PI5USB2544A/2546A control pins to correspond to DCP_Auto charging mode per below table. When system is put back to operation mode then set control pins to correspond to SDP or CDP mode and so on. PI5USB2546A Device Control Pins Truth Table CTL1 CTL2 CTL3 ILIM_SEL MODE Current Limit Setting /STATUS Output (Active low) Comment 0 0 0 0 Discharge NA OFF OUT held low 0 0 0 1 Discharge NA OFF 0 0 1 0 DCP_Auto ILIM_HI OFF Data lines disconnected 0 0 1 1 DCP_Auto IOS_PW & ILIM_HI(1) DCP load present(2) Data lines disconnected and load detect function active 0 1 0 0 SDP1 ILIM_LO OFF Data lines connected 0 1 0 1 SDP1 ILIM_HI OFF 0 1 1 0 DCP_Auto ILIM_HI OFF Data lines disconnected 0 1 1 1 DCP_Auto ILIM_HI DCP load present(3) Data lines disconnected and load detect function active 1 0 0 0 DCP_Shorted ILIM_LO OFF Device forced to stay in DCP BC1.2 charging mode 1 0 0 1 DCP_Shorted ILIM_HI OFF 1 0 1 0 Divider-1A ILIM_LO OFF Device forced to stay in Divider-1A charging mode 1 0 1 1 Divider-1A ILIM_HI OFF 1 1 0 0 SDP1 ILIM_LO OFF Data lines connected 1 1 0 1 SDP1 ILIM_HI OFF 1 1 1 0 SDP2(4) ILIM_LO OFF 1 1 1 1 CDP(4) ILIM_HI CDP load present(5) Data lines connected and load detect active Note: (1) PI5USB2546A: Current limit (IOS) is automatically switched between IOS_PW and the value set by ILIM_HI according to the Load Detect –Power Wake functionality. (2) DCP Load present governed by the “Load Detection – Power Wake” limits. (3) DCP Load present governed by the “Load Detection – Non Power Wake” limits. (4) No OUT discharge when changing between 1111 and 1110. (5) CDP Load present governed by the “Load Detection – Non Power Wake” limits and BC1.2 primary detection.
2015-08-0012 PT0513-3 8/31/15 PI5USB2544A, PI5USB2546A USB Charging Port Controller and Load Detection Power Switch PI5USB2544A Device Control Pins Truth Table CTL1 CTL2 CTL3 ILIM_SEL MODE Current Limit Setting Comment 0 0 0 0 Discharge NA OUT held low 0 0 0 1 Discharge NA 0 x 1 x DCP_Auto ILIM_HI Data lines disconnected 0 1 0 0 SDP1 ILIM_LO Data lines connected 0 1 0 1 SDP1 ILIM_HI 0 1 1 0 DCP_Auto ILIM_HI Data lines disconnected 0 1 1 1 DCP_Auto ILIM_HI Data lines disconnected 1 0 0 0 DCP_Shorted ILIM_LO Device forced to stay in DCP BC1.2 charging mode 1 0 0 1 DCP_Shorted ILIM_HI 1 0 1 0 Divider-1A ILIM_LO Device forced to stay in Divider-1A charging mode 1 0 1 1 Divider-1A ILIM_HI 1 1 0 0 SDP1 ILIM_LO Data lines connected 1 1 0 1 SDP1 ILIM_HI 1 1 1 0 SDP2(1) ILIM_LO 1 1 1 1 CDP(1) ILIM_HI Data lines connected Note: (1) No OUT discharge when changing between 1111 and 1110. Below table s can be used as an aid to program the PI5USB2544A/2546A per system states however not restricted to below settings only. PI5USB2546A Control Pin Setting Matched to System Power States System Global Power State Charging Mode CTL1 CTL2 CTL3 ILIM_SEL Current Limit Setting S0 SDP1 1 1 0 1 or 0 ILIM_HI/ILIM_LO S0 SDP2, no discharge to/from CDP 1 1 1 0 ILIM_LO CDP, load detection with ILIM_LO + 25mA thresholds or if a BC1.2 primary detection occurs 1 1 1 1 ILIM_HI S4/S5 Auto mode, load detection with power wake thresholds 0 0 1 1 ILIM_HI S3/S4/S5 Auto mode, no load detection 0 0 1 0 ILIM_HI Auto mode, keyboard/mouse wake up, load detection with ILIM_LO + 25mA thresholds 0 1 1 1 ILIM_HI S3 Auto mode, keyboard/mouse wake up, no load detection 0 1 1 0 ILIM_HI S3 SDP1, keyboard/mouse wake up 0 1 0 1 or 0 ILIM_HI/ILIM_LO
2015-08-0012 PT0513-3 8/31/15 PI5USB2544A, PI5USB2546A USB Charging Port Controller and Load Detection Power Switch PI5USB2544A Control Pin Setting Matched to System Power States System Global Power State Charging Mode CTL1 CTL2 CTL3 ILIM_SEL Current Limit Setting S0 SDP1 1 1 0 1 or 0 ILIM_HI/ILIM_LO S0 SDP2, no discharge to/from CDP 1 1 1 0 ILIM_LO S0 CDP 1 1 1 1 ILIM_HI S3/S4/S5 Auto mode 0 0 1 0 ILIM_HI S3 Auto mode, keyboard/mouse wake up, no load detection 0 1 1 0 ILIM_HI S3 SDP1, keyboard/mouse wake up 0 1 0 1 or 0 ILIM_HI/ILIM_LO Load Detect (PI5USB2546A) PI5USB2546A offer system designers unique power management strategy not available in the industry from similar devices. There are two power management schemes supported by the PI5USB2546A via the /STATUS pin, they are: 1. Power Wake (PW) 2. Port Power Management (PPM) Either feature may be implemented in a system depending on power savings goals for the system. In general Power Wake feature is used mainly in mobile systems like a notebook where it is imperative to save battery power when system is in deep sleep (S4/S5) st ate. On the other hand Port Power Management feature would be implemented where multiple charging ports are supported in the same system and system power rating is not capable of supporting high current charging on multiple ports simultaneously. Power Wake (PI5USB2546A) Goal of power wake feature is to save system power when system is in S4/S5 state. In S4/S5 state system is in deep sleep and typically running of the battery; so every “mW” in system power savings will translate to extending battery life. In this state the PI5USB2546A will monitor charging current at the OUT pin and provide a mechanism via the /STATUS pin to switch out the high power DC-DC controller and switch in a low power LDO when charging current requirement is <45mA (typ.). This would be the case when no peripheral device is connected at the charging port or if a device has attained its full battery charge and draws <45mA. Power wake flow chart and description is shown as Figure 6.
2015-08-0012 PT0513-3 8/31/15 PI5USB2544A, PI5USB2546A USB Charging Port Controller and Load Detection Power Switch Figure 6, PI5USB2546A Power Wake flow chart Load being Charged PI5USB2546A is asserting power wake System power is at its full capability Load can charge at high current PI5USB2546A monitors port to detect when charging load is done charging or removed Charging Load Detected PI5USB2546A is asserting power wake System power turns on to its full power State Load Vbus is held low for 2s to give the power system time to turn on before the load tries to pull charging current again. Charging Load Not Detected PI5USB2546A is not asserting power wake System power is in a low power state to save energy. PI5USB2546A monitors port to detect when charging load is attached and tries to charge Case 1 Load Detected Power Wake Asserted /STATUS=0 Current Limit=ILMI_HI setting OUT Discharge OUT Discharge Power Wake Asserted /STATUS=0 Current Limit=55mA Case 2A&2B (No Load Detected) Power Wake D-asserted /STATUS=1 Current Limit=55mA Load Current<45mA for 15s (Not Charging) Load Current>55mA (Charging Current Detected) Discharge >2s
2015-08-0012 PT0513-3 8/31/15 PI5USB2544A, PI5USB2546A USB Charging Port Controller and Load Detection Power Switch Implementing Power Wake in Notebook System An implementation of power wake in notebook platforms with the PI5USB2546A is shown as below. Power wake function is used to select between a high power DC -DC converter and low power LDO (100mA) based on charging requirements. System power saving is achieved when under no charging conditions (the connected device is fully charge d or no device is connected) the DC-DC converter is turned -off (to save power since it is less efficient in low power operating region) and the low power LDO supplies standby power to the charging port. Power wake is activated in S4/S5 mode (0011 setting, see device truth table), PI5PI5USB2546A is charging connected device as shown as case 1 , /STATUS is pulled LO (Case 1) which switches -out the LDO and switches -in the DC -DC converter to handle high current charging. Figure 7, Case 1: System in S4/S5, Device Charging As shown in Case 2A (Figure 8) and Case 2B (Figure 9), when connected device is fully charged or gets disconnected from the charging port, the charging current will fall. If charging current falls to <45mA and stays below this threshold for over 15s , PI5USB2546A automatically sets a 55mA internal current limit and /STATUS is de -asserted (pulled HI). As shown in Case 2A and Case 2B. This results in DC -DC converter turning off and the LDO turning on. Current limit of 55mA is set to prevent the low power LDO o utput voltage from collapsing in case there is a spike in current draw due to device attachment or other activity such as display panel LED turning ON in connected device. Following Power Wake flow chart when a device is attached and draws >55mA of chargi ng current the PI5USB2546A will hit its internal current limit. This will trigger the device to assert /STATUS (LO) and turn on the DC -DC converter and turn off the LDO. PI5USB2544A/2546A will discharge OUT for > 2s (typ.) to allow the main power supply to turn on. After the discharge the device will turn back on with current limit set by ILIM_HI (Case 1, Figure 7) Peripheral Device ChargingDr LDO Disconnected/Shut-Down DC-DC Switch-In Note: DC/DC and LDO switch based on STATUS. Power Block 19V EN EN 5V DC/DC 5V LDO IN System Controller DM DP OC I/O_EN USB Host Controller STATUS EN FAULT DM_OUT OTSD DP_OUT EN CTL1 CTL2 CTL3 ILIM_SEL PI5USB2546A /PI5USB2546A OUT DM_IN DP_IN GND ILIM_LO ILIM_HI VBUS GND 0011 1DM Ilimit set by Divider Modes
2015-08-0012 PT0513-3 8/31/15 PI5USB2544A, PI5USB2546A USB Charging Port Controller and Load Detection Power Switch Port Power Management (PPM) PPM is the intelligent and dynamic allocation of power. It is for systems that have multiple charging ports but cannot power them all simultaneously. Goal of this feature are: 1. Enhances user experience since user does not have to search for charging port 2. Power supply only has to be designed for a reasonable charging load Initially all ports are allowed to broadcast high current charging, charging current limit is based on ILIM_HI resistor setting. System monitors /STATUS to see when high current loads are present. Once allowed number of ports assert /STATUS, remaining ports are toggled to a non -charging port. Non-charging ports are SDP ports with current limit based on ILIM_LO . PI5USB2546A allows for a system to toggle between charging and non -charging ports either with an OUT discharge or without an OUT discharge. Benefits of PPM
- Delivers better user experience
- Prevents overloading of system's power supply
- Allows for dynamic power limits based on system state
- Allows every port to potentially be a high power charging port
- Allows for smaller power supply capacity since the loading is controlled PPM Details All ports are allowed to broadcast high current charging – CDP or DCP. Current limit is based on ILIM_HI and system monitors /STATUS pin to see when high current loads are present. Once allowed n umber of ports assert /STATUS, remaining ports are toggled to a SDP non -charging port. SDP current limit is based on ILIM_LO setting. SDP ports are automatically toggled back to CDP or DCP mode when a charging port de-asserts /STATUS. Based on CTL setting s there is a provision for a port to toggle between charging and non -charging ports either with a V BUS discharge or without a V BUS discharge. For example when a port is in SDP2 mode (1110) and its ILIM_SEL pin is toggled to 1 due to another port releasing its high current requirements. The SDP2 port will automatically revert to CDP mode (1111) without a discharge event. This is desirable if this port was connected to a media device where it was syncing data from the SDP2 port; a discharge event would mess-up the syncing activity on the port and cause user confusion. /STATUS trip point is based on the programmable ILIM_LO current limit set point . This does not mean /STATUS is a current limit – the port itself is using the ILIM_HI current limit. Since ILIM_LO defines the current limit for a SDP port, it works well to use the ILIM_LO value to define a high current load. /STATUS asserts in CDP and DCP when load current is above ILIM_LO+25mA for 200ms. /STATUS de-asserts in CDP and DCP when load current is below ILIM_LO-25mA for 3s.
2015-08-0012 PT0513-3 8/31/15 PI5USB2544A, PI5USB2546A USB Charging Port Controller and Load Detection Power Switch Implementing PPM in a System with Two Charging Ports Below shows the implementation of two charging ports and each port with its own PI5USB2546A. In this example 5V power supply for the two charging ports is rated at <3A or < 15W max. Both devices have RLIM chosen to correspond to the low (0.9A) and high (1.5A) current limit setting for the port. In this implementation the system can support only one of the two ports a t 1.5A charging current while the other port is set to SDP mode and ILIMIT corresponding to 0.9A. Figure 10, Implementing Port Power Management in a System Supporting Two Charging Ports IN STATUS FAULT EN CTL1 CTL2 CTL3 ILIM_SEL PI5USB2546A OUT DM_IN DP_IN GND ILIM_LO ILIM_HI S0-S3 69.8k (0.6A) 29.4k (1.5A) IN STATUS FAULT EN CTL1 CTL2 CTL3 ILIM_SEL OUT DM_IN DP_IN GND ILIM_LO ILIM_HI 69.8k (0.6A) 29.4k (1.5A) USBPort 1 USBPort 2 100k 100k EN 1 FAULT 1 EN 2 FAULT 2
2015-08-0012 PT0513-3 8/31/15 PI5USB2544A, PI5USB2546A USB Charging Port Controller and Load Detection Power Switch CDP/SDP Auto Switch PI5USB2544A/2546A series is equipped with a CDP/SDP auto-switch feature to support some popular phones in the market that are not compliant to the BC1.2 specification, as they fail to establish data connection in CDP mode. These phones use primary detection (used to distinguish between an SDP and different types of Charging Ports) to only identify ports as SDP (data / no charge) or DCP (no data / charge). They do not recognize CDP (data /charge) ports. When connected to a CDP port, these phones classify the port as a DCP and will only charge. Since charging ports are configured as CDP when the computer is in S0, users do not get the expected data connection. To remedy this problem PI5USB2544A/2546A series employs a CDP/SDP Auto Switch scheme to ensure these BC1.2 non- compliant phones will establish data connection by following below steps: The PI5USB2544A/2546A will determine when a non-compliant phone has wrongly classified a CDP port as a DCP port and has not made a data connection The PI5USB2544A/2546A will then automatically do a OUT (VBUS) discharge and reconfigure the port as an SDP This allows the phone to discover it is now connected to an SDP and establish a data connection The PI5USB2544A/2546A will then switch automatically back to CDP without doing an OUT (VBUS) discharge The phone will continue to operate like it is connected to a SDP since OUT (VBUS) was not interrupted The port is now ready in CDP if a new device is attached Over-Current Protection When an over -current condition is detected, the device maintains a constant output current and reduces the output voltage accordingly. Two possible overload conditions can occur. In the first condition, the output has been shorted before the devic e is enabled or before VIN has been applied. The PI5USB2544A/2546A senses the short and immediately switches into a constant - current output. In the second condition, a short or an overload occurs while the device is enabled. At the instant the overlo ad occurs, high currents may flow for nominally one to two microseconds before the current -limit circuit can react. The device operates in constant -current mode after the current-limit circuit has responded. Complete shutdown occurs only if the fault is presented long en ough to activate thermal limiting. The device will remain off until the junction temperature cools approximately 20° C and will then re-start. The device will continue to cycle on/off until the over-current condition is removed.
2015-08-0012 PT0513-3 8/31/15 PI5USB2544A, PI5USB2546A USB Charging Port Controller and Load Detection Power Switch Current-Limit Settings The PI5USB2544A/2546A series have two independent current limit settings that are each programmed externally with a resistor. The ILIM_HI setting is programmed with R ILIM_HI connected between ILIM_HI and GND. The ILIM_LO setting is programmed with R ILIM_LO connected between ILIM_LO and GND. Consult the Device Truth Table to see when each current limit is used. Both settings have the same relation between the current limit and the programming resistor. RILIM_LO is optional and the ILIM_LO pin may be left unconnected if the following conditions are met: 1. ILIM_SEL is always set high 2. Load Detection - Port Power Management is not used The following equation programs the typical current limit: IOS_TYP (mA)=50250/RLIM_xx (kΩ) RILIM_XX corresponds to either RILIM_HI or RILIM_LO as appropriate. Many applications require that the current limit meet specific tolerance limits. When designing to these tolerance limits, both the tolerance of the PI5USB2544A/2546A current limit and the tolerance of the external programmin g resistor must be taken into account. The following equations approximate the PI5USB2544A/2546A minimum / maximum current limits to within a few mA and are appropriate for design purposes. These equations assume an ideal – no variation - external programm ing resistor. To take resistor tolerance into account, first determine the minimum /maximum resistor values based on its toleranc e specifications and use these values in the equations. Because of the inverse relation between the current limit and the programming resistor, use the maximum resistor value in the IOS_MIN equation and the minimum resistor value in the I OS_MAX equation. IOS_MIN (mA)=45271/(RLIM_xx (kΩ))0.98437-30 IOS_MAX (mA) =55325/ (RLIM_xx (kΩ)) 1.0139+30 The traces routing the R ILIM_XX resistors should be a sufficiently low resistance as to not affect the current -limit accuracy. The ground connection for the R ILIM_XX resistors is also very important. The resistors need to reference back to the PI5USB2544A/2546A GND pin. Follow ing normal board layout practices to ensure that current flow from other parts of the board does not impact the ground potential between the resistors and the PI5USB2544A/2546A GND pin. /FAULT Response The /FAULT open -drain output is asserted (active low) when an over -temperature or current limit condition. The output remains asserted until the fault condition is removed. The PI5USB2544A/2546A series is designed to eliminate false /FAULT reporting by using an internal deglitch circuit for current limit condit ions without the need for external circuitry. This ensures that /FAULT is not accidentally asserted due to normal operation such as starting into a heavy capacitive load. Over - temperature conditions are not deglitched and assert the /FAULT signal immediately. Undervoltage Lockout (UVLO) The undervoltage lockout (UVLO) circuit disables the power switch until the input voltage reaches the UVLO turn on threshold. Built-in hysteresis prevents unwanted oscillations on the output due to input voltage drop from large current surges. Thermal Sense The PI5USB2544A/2546A series protects itself with thermal sensing circuit that monitor the operating temperature of the power distribution switch and disables operation if the temperature exceeds recommended operating conditions. The device operates in constant-current mode during an over -current condition, which increases the voltage drop across power switch. The power dissipation in the package is proportional to the voltage drop across the power switch, so the junctio n temperature rises during an over -current condition. The thermal sensor turns off the power switch when the die temperature exceeds 1 70° C regardless of whether the power switch is in current limit. Hysteresis is built into thermal sensor, and the switch t urns on after the device has cooled by approximately 20° C. The switch continues to cycle off and on until the fault is removed. The open - drain false reporting output /FAULT is asserted (active low) when an over-temperature shutdown condition.
2015-08-0012 PT0513-3 8/31/15 PI5USB2544A, PI5USB2546A USB Charging Port Controller and Load Detection Power Switch
Application Information
Input and Output Capacitance Input and output capacitance improves the performance of the device; the actual capacitance should be optimized for the particular application. For all applications, a 0.1uF or greater ceramic bypass capacitor between IN and GND is recommended as close to the device as possible for local noise decoupling. This precaution reduces ringing on the input due to power -supply transients. Additional input capacitance may be needed on the input to reduce voltage overshoo t from exceeding the absolute -maximum voltage of the device during heavy transient conditions or output shorting. This is especially important during bench testing when long inductive cables are used to connect the evaluation board to the bench power suppl y. Normally suggested the distance between IC and DC supply is less than 15cm. Output capacitance also needs to be close to IC as possible. W hen large transient currents are expected on the output , placing a high-value electrolytic capacitor on the output pin is recommended. Layout Design Guideline 1. The PCB is suggested to use at least 4 layers 2. The high speed differential pair should be maintain 90Ω 3. Do not route the high speed signal over any split plane 4. Minimized the number of vias and corners on the high speed trace for reducing the signal reflections and impedance changes 5. If it’s necessary to turn 90°, use two 45° turns or an arc instead of making a single 90° turn. This can reduces reflections on the signal by minimizing impedance discontinuities. 6. The high speed trace should be routed symmetrically and parallelism (including the test points on the high speed trace). The non-parallelism trace will cause the impedance discontinuities and affect the signal quality 7. Avoid any unnecessary stubs on the differential pair. The stubs will introduce the signal reflections which affect the signal quality 8. Avoid routing the high speed differential pair under the crystal, oscillator, clock synthesizer, magnetic devices or ICs to cause the interference. 9. Avoid anti-etch on the GND plane Typical Application Circuit PI5USB2544A Typical Application Circuit ILIM_SEL EN USB Host NC VBUS_OUT 80.6k 18k PI5USB2544AZHE@TQFN16 IN1 DM_OUT2
3 DP_OUT
ILIM_SEL4 EN5 CTL16 CTL27 CTL38 NC 9 DP_IN 10 DM_IN 11 OUT 12 FAULT# 13 GND 14 ILIM_LO 15 ILIM_HI 16 Exp_Pad NA USB Connector NC pin connect to GND or leave open Differential 0.1uF 10k 120uF 10uF VBUS_IN VBUS GND DC Power BUS FAULT# uP
2015-08-0012 PT0513-3 8/31/15 PI5USB2544A, PI5USB2546A USB Charging Port Controller and Load Detection Power Switch PI5USB2546A Typical Application Circuit ILIM_SEL EN STATUS# FAULT# USB Host VBUS_OUT 80.6k 18k PI5USB2546AZHE@TQFN16 IN1 DM_OUT2 ILIM_SEL4 EN5 CTL16 CTL27 CTL38 STATUS# 9 DP_IN 10 DM_IN 11 OUT 12 FAULT# 13 GND 14 ILIM_LO 15 ILIM_HI 16 Exp_Pad NA USB Connector Differential 0.1uF 10k 120uF 10uF VBUS_IN VBUS GND DC Power BUS 10k uP
2015-08-0012 PT0513-3 8/31/15 PI5USB2544A, PI5USB2546A USB Charging Port Controller and Load Detection Power Switch Mechanical Information TQFN 3.0x3.0-16L
Ordering Information
Part No. Package Code Package PI5USB2544AZHEX ZH Lead free and Green 16-pin TQFN3.0x3.0, Tape & Reel PI5USB2546AZHEX ZH Lead free and Green 16-pin TQFN3.0x3.0, Tape & Reel Note: E = Pb-free and Green Adding X Suffix= Tape/Reel Pericom Semiconductor Corporation 1-800-435-2336 www.pericom.com Pericom reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. Pericom does not assume any responsibility for use of any circuitry described other than the circuitry embodied in Pericom product. The company makes no representations that circuitry described herein is free from patent infringement or other rights, of Pericom.