PI4IOE5V9570 PERICOM | Alldatasheet
Document overview
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Technical content
Features
Operation power supply voltage from 2.3V to 5.5V 4-bit I2C-bus GPO 1 MHz I2C-bus interface with 30 mA SDA sink capability for 4000pF Latched outputs with 25mA capability for directly driving LEDs Software Reset; Power-on reset Low standby current ESD protection (4KV HBM and 1KV CDM) Offered in two different packages:UQFN 1.6x1.6- 8,MSOP-8 Pin Configuration
Description
The PI4IOE5V9570 is a CMOS device that provides 4bits of General Purpose parallel Output (GPO) expansion in low voltage proc essor and handheld battery powered mobile applications. It operates at 1 MHz I 2C-bus speeds while maintaining backward compatibility to Fast -mode (400 kHz) and Standard-mode (100 kHz). The PI4IOE5V9570 is a streamlined GPO that consists of 4 -bit push -pull outputs that offer low current consumption, small packaging options The PI4IOE5V9570 output expander provides a simple solution when additional outputs are needed while keeping interconnections and floor space to a minimum, for example, in battery powered mobile applications where PCBs are crowded for interfacing to sensors, push buttons, etc. The PI4IOE5V9570 contains an internal Power-On Reset (POR) and a Software Reset feature that initializes the device to its default state. Figure1 : MSOP-8 Figure2 : UQFN 1.6x1.6-8
Table 1. Pin configuration
2015-07-0044 PT0559 08/05/15 PI4IOE5V9570 4-bit general purpose outputs for 1MHz I2C bus Maximum Ratings Static characteristics VCC =2.3 V to 5.5V; GND = 0 V; Tamb= -40 ° C to +85 ° C; unless otherwise specified. Table 2: Static characteristics Symbol Parameter Conditions Min. Typ. Max. Unit Power supply VCC Supply voltage 2.3 - 5.5 V IDD Supply current Operating mode; no load; VI = VCC or GND; fSCL = 1 MHz; - 200 500 μA Istb Standby current Standby mode; VCC = 5.5 V; no load; VI = VCC; fSCL= 0 kHz; I/O = inputs - 4.5 10 uA VPOR Power-on reset voltage[1] Standby mode; no load; VI = VCC or GND; fSCL = 0 kHz - 1.16 1.41 V Input SCL, input/output SDA VIL Low level input voltage -0.5 0.3VCC V VIH High level input voltage 0.7VCC 5.5 V IOL Low level output current VOL = 0.4 V; VCC = 2.3 V 20 35 - mA VOL = 0.4 V; VCC = 3.0 V 25 44 VOL = 0.4 V; VCC = 4.5 V 30 57 IL Leakage current VI=VCC=GND -1 - 1 μA Ci Input capacitance VI =GND - 5 10 pF Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above t hose indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2015-07-0044 PT0559 08/05/15 PI4IOE5V9570 4-bit general purpose outputs for 1MHz I2C bus Symbol Parameter Conditions Min. Typ. Max. Unit I/Os VIL LOW-level input voltage -0.5 0.81 V VIH HIGH-level input voltage 1.8 5.5 V IOL Low level output current VCC = 2.3 V; VOL = 0.5 V[2] 12 26 mA VCC =3.0V; VOL = 0.5 V[2] 17 33 mA VCC =4.5V; VOL = 0.5 V[2] 25 40 mA IOL(tot) total LOW-level output current VOL=0.5V;VCC=4.5V 200 mA IOH HIGH-level output current VOH = GND -30 -359 -480 uA Itrt(pu) transient boosted pull-up current VOH= GND -0.5 -1.0 mA Ci Input capacitance - 2.1 10 pF Co Output capacitance - 2.1 10 pF Note: [1]: VCC must be lowered to 0.2 V for at least 5 us in order to reset part. [2]: Each I/O must be externally limited to a maximum of 25 mA and the total package limited to 100 mA due to internal busing limits. [3]: The value is not tested, but verified on sampling basis.
2015-07-0044 PT0559 08/05/15 PI4IOE5V9570 4-bit general purpose outputs for 1MHz I2C bus Dymaic Characteristics Table 3: Dynamic characteristics Symbol Parameter Test Conditions Standard mode I2C Fast mode I2C 1 MHz I2C-bus Unit Min Max Min Max Min Max fSCL SCL clock frequency 0 100 0 400 0 1000 kHz tBUF bus free time between a STOP and START condition 4.7 - 1.3 - 0.5 μs tHD;STA hold time (repeated) START condition 4.0 - 0.6 - 0.26 μs tSU;STA set-up time for a repeated START condition 4.7 - 0.6 - 0.26 μs tSU;STO set-up time for STOP condition 4.0 - 0.6 - 0.26 μs tVD;ACK [1] data valid acknowledge time - 3.45 - 0.9 0.45 μs tHD;DAT data hold time 0 0 ns tVD;DAT [2] data valid time 3.45 - 0.9 0.45 us tSU;DAT data set-up time 250 - 100 - 50 ns tLOW LOW period of the SCL clock 4.7 - 1.3 - 0.5 μs tHIGH HIGH period of the SCL clock 4.0 - 0.6 - 0.26 μs tf fall time of both SDA and SCL signals - 300 - 300 - 120 ns tr rise time of both SDA and SCL signals - 1000 - 300 - 120 ns tSP [3] pulse width of spikes that must be suppressed by the input filter - 50 - 50 - 50 ns Port timing tv(Q) Data output valid time 200 200 200 ns Note: [1] tVD;ACK = time for Acknowledgement signal from SCL LOW to SDA (out) LOW. [2] tVD;DAT = minimum time for SDA data out to be valid following SCL LOW. [3] Input filters on the SDA and SCL inputs suppress noise spikes less than 50 ns.
2015-07-0044 PT0559 08/05/15 PI4IOE5V9570 4-bit general purpose outputs for 1MHz I2C bus PI4IOE5V9570 Block Diagram Details Description a. Device Address b7(MSB) b6 b5 b4 b3 b2 b1 b0 Address Byte 0 1 0 0 1 0 0 R/W b. Software Reset Call General Call address: allows resetting the device through the I2C-bus upon reception of the right I2C-bus sequence. b7(MSB) b6 b5 b4 b3 b2 b1 b0 General Call Address 0 0 0 0 0 0 0 0 c. Software Reset The Software Reset Call allows all the devices in the I2C-bus to be reset to the power-up state value through a specific formatted I2C-bus command. To be performed correctly, it implies that the I2C-bus is functional and that there is no device hanging the bus. The Software Reset sequence is defined as following: 1. A START command is sent by the I2C-bus master. 2. The reserved General Call I2C-bus address ‘0000 000’ with the R/W bit set to 0 (write) is sent by the I 2C-bus master. 3. The device acknowledges after seeing the General Call address ‘0000 0000’ (00h) only. If the R/W bit is set to 1 (read), no acknowledge is returned to the I2C-bus master. 4. Once the General Call address has been sent and acknowledged, the master sends 1 byte. The value of the byte must be equal to 06h. a. The device acknowledges this value only. If the byte is not equal to 06h, the dev ice does not acknowledge it. Fig 3: Block diagram of PI4IOE5V9570
2015-07-0044 PT0559 08/05/15 PI4IOE5V9570 4-bit general purpose outputs for 1MHz I2C bus I/O expander applications Bellow figure shows a 4-bit output expander application. The desired HIGH or LOW logic levels are controlled by the master with speeds of up to 1 MHz .This allows the host processor to control various functions quickly and with very low overhead. The port read function of the device enables the host processor to poll the status of the output port pins. This is useful for system recovery operations or debugging. Figure 8: Application
2015-07-0044 PT0559 08/05/15 PI4IOE5V9570 4-bit general purpose outputs for 1MHz I2C bus Mechanical Information MSOP-8(U)
2015-07-0044 PT0559 08/05/15 PI4IOE5V9570 4-bit general purpose outputs for 1MHz I2C bus UQFN-8(XT)
Ordering Information
Part No. Package Code Package PI4IOEV9570UE U 8-Pin, Mini Small Outline Package(MSOP) PI4IOE5V9570UE U 8-Pin, Mini Small Outline Package(MSOP), Tape & Reel PI4IOE5V9570XTEX XT 8-pin UQFN 1.6x1.6, Tape & Reel Note: E = Pb-free and Green Adding X Suffix= Tape/Reel Pericom Semiconductor Corporation 1-800-435-2336 www.pericom.com Pericom reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. Pericom does not assume any responsibility for use of any circuitry described other than the circuitry embodied in Pericom product. The company makes no representations that circuitry described herein is free from patent infringement or other rights, of Pericom.