PI4IOE5V9521 PERICOM | Alldatasheet
Document overview
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Technical content
Features
Operation power supply voltage from 2.3V to 5.5V 2-bit I2C-bus GPIO with interrupt and reset 5V tolerant I/Os Active Low interrupt output Active Low reset input Polarity inversion register Low current consumption 0Hz to 1MHz clock frequency Noise filter on SCL/SDA inputs Power-on reset ESD protection (4KV HBM and 1KV CDM) Package offered :UQFN 1.6x1.6-8 Pin Configuration
Description
The PI4IOE5V9521 provides 2 bits of General Purpose parallel Input/Output (GPIO) expansion for I2C-bus/ SMBus applications. It includes the features such as higher driving capability, 5V tolerance, lower power supply, individual I/O configuration, and smaller packaging. It provides a simple solution when additional I/O is needed for ACPI power switches, sensors, push buttons, LEDs, fans, etc. The PI4IOE5V9521 consists of a 2-bit configuration register to configure the I/Os as either inputs or outputs, and a 2-bit polarity register to change the polarity of the input port register data. The data for each input or output is kept in the corresponding Input port or Output port register. All registers can be read by the system master. The PI4IOE5V 9521 open-drain interrupt output (INT) is activated when any input state is differed from its corresponding Input Port r egister and is used to indicate the system master that an input state has changed. The power -on reset sets the registers to their default values and initializes the device state machine. The Reset pin (Reset) causes the same reset/initialization to occur without de -powering the device. Figure 1. UQFN 1.6 x 1.6-8
Table 1. Pin description
1 P0 I/O Input/Output 0
2 P1 I/O Input/Output1
3 GND G Supply ground
4 RESET I Reset pin
5 INT O Interrupt output (open-drain)
6 SCL I Serial clock line
7 SDA I/O Serial data line
8 VCC P Power supply
2016-02-0002 PT0564-1 03/29/16 PI4IOE5V9521 2-bit I2C-bus and SMBus low power I/O port with interrupt and reset Maximum Ratings Static characteristics VCC = 2.3 V to 5.5 V; GND = 0 V; Tamb = -40 ° C to +85 ° C; unless otherwise specified. Table 2: Static characteristics Symbol Parameter Conditions Min. Typ. Max. Unit Power supply VCC Supply voltage 2.3 - 5.5 V ICC Supply current Operating mode; VCC = 5.5 V; no load; fSCL= 100 kHz - 104 175 μA Istb Standby current Standby mode; VCC = 5.5 V; no load; VI = GND; fSCL= 0 kHz; I/O = inputs - 0.25 1 μA Standby mode; VCC = 5.5 V; no load; VI = VCC; fSCL= 0 kHz; I/O = inputs 0.25 1 μA VPOR Power-on reset voltage[1] - 1.16 1.41 V Input SCL, input/output SDA VIL Low level input voltage -0.5 - +0.3VCC V VIH High level input voltage 0.7VCC - 5.5 V IOL Low level output current VOL = 0.4V 20 - - mA IL Leakage current VI = VCC = GND -1 - 1 μA Ci Input capacitance VI = GND - 5 10 pF Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at thes e or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2016-02-0002 PT0564-1 03/29/16 PI4IOE5V9521 2-bit I2C-bus and SMBus low power I/O port with interrupt and reset Symbol Parameter Conditions Min. Typ. Max. Unit I/Os VIL Low level input voltage -0.5 - +0.81 V VIH High level input voltage +1.8 - 5.5 V IOL Low level output current VCC = 2.3 V; VOL = 0.5 V[2] 8 10 - mA VCC = 2.3 V; VOL = 0.7 V[2] 10 13 - mA VCC = 3.0 V; VOL = 0.5 V[2] 8 14 - mA VCC = 3.0 V; VOL = 0.7 V[2] 10 19 - mA VCC = 4.5 V; VOL = 0.5 V[2] 8 17 - mA VCC = 4.5 V; VOL = 0.7 V[2] 10 24 - mA VOH High level output voltage IOH = -8mA; VCC = 2.3V[3] 1.8 - - V IOH = -10mA; VCC = 2.3V[3] 1.7 - - V IOH = -8mA; VCC = 3.0V[3] 2.6 - - V IOH = -10mA; VCC = 3.0V[3] 2.5 - - V IOH = -8mA; VCC = 4.75V[3] 4.1 - - V IOH = -10mA; VCC = 4.75V[3] 4.0 - - V IL Input leakage current VCC = 3.6V; VI = VCC = GND -1 - 1 μA Ci Input capacitance - 3.7 10 pF Interrupt INT IOL Low level output current VOL = 0.4V 3 13 - mA IOH High level output current VOL = 0.4V -1 +1 uA Reset RESET VIL Low level input voltage -0.5 - +0.81 V VIH High level input voltage +1.8 - 5.5 V IL Input leakage current VI = VCC = GND -1 1 μA Note: [1]: VCC must be lowered to 0.2 V for at least 5 us in order to reset part. [2]: Each I/O must be externally limited to a maximum of 25 mA and the device must be limited to a maximum current of 50 mA. [3]: The total current sourced by all I/Os must be limited to 40 mA.
2016-02-0002 PT0564-1 03/29/16 PI4IOE5V9521 2-bit I2C-bus and SMBus low power I/O port with interrupt and reset Dynamic characteristics Table 3: Dynamic characteristics Symbol Parameter Conditions Standard mode I2C Fast mode I2C Fast mode Plus I2C Unit Min Max Min Max Min Max fSCL SCL clock frequency 0 100 0 400 0 1000 kHz tBUF Bus free time between a STOP and START condition 4.7 - 1.3 - 0.5 - μs tHD;STA Hold time (repeated) START condition 4.0 - 0.6 - 0.26 - μs tSU;STA Set-up time for a repeated START condition 4.7 - 0.6 - 0.26 - μs tSU;STO Set-up time for STOP condition 4.0 - 0.6 - 0.26 - μs tVD;ACK [1] Data valid acknowledge time - 3.45 - 0.9 - 0.45 μs tHD;DAT [2] Data hold time 0 - 0 - 0 - ns tVD;DAT Data valid time - 3.45 - 0.9 - 0.45 us tSU;DAT Data set-up time 250 - 100 - 50 - ns tLOW LOW period of the SCL clock 4.7 - 1.3 - 0.5 - μs tHIGH HIGH period of the SCL clock 4.0 - 0.6 - 0.26 - μs tf Fall time of both SDA and SCL signals - 300 - 300 - 120 ns tr Rise time of both SDA and SCL signals - 1000 - 300 - 120 ns tSP Pulse width of spikes that must be suppressed by the input filter - 50 - 50 50 ns Port timing tv(Q) Data output valid time[3] - 200 - 200 - 200 ns tsu(D) Data input set-up time 100 - 100 - 100 - ns th(D) Data input hold time 1 - 1 - 1 - μs Interrupt timing tv(INT) Valid time on pin INT - 4 - 4 - 4 μs trst(INT) Reset time on pin INT - 4 - 4 - 4 μs
2016-02-0002 PT0564-1 03/29/16 PI4IOE5V9521 2-bit I2C-bus and SMBus low power I/O port with interrupt and reset Symbol Parameter Conditions Standard mode I2C Fast mode I2C Fast mode Plus I2C Unit Min Max Min Max Min Max Reset timing tw(rst) Reset pulse width 25 - 25 - 25 - ns trec(rst) Reset recovery time[4] 0 - 0 - 0 - ns trst Reset time 1 - 1 - 1 - us Note: [1]: tVD;ACK = time for acknowledgement signal from SCL LOW to SDA (out) LOW. [2]: tVD;DAT = minimum time for SDA data out to be valid following SCL LOW. [3]: tv(Q)measured from 0.7VCC on SCL to 50% I/O output. [4]: To reset the device while actively communicating on the bus may cause glitches or errant STOP conditions. Upon reset, the full delay will be the sum of trst and RC time constant of SDA bus. Figure 2: Timing diagram for INT timing and Port timing
2016-02-0002 PT0564-1 03/29/16 PI4IOE5V9521 2-bit I2C-bus and SMBus low power I/O port with interrupt and reset PI4IOE5V9521 Block Diagram Details Description a. Device address Table 4: Device address b7(MSB) b6 b5 b4 b3 b2 b1 b0 Address Byte 1 0 0 1 0 0 1 R/W Note: Read “1”, Write “0” b. Registers i. Command byte The command byte is the first byte to follow the address byte during a write transmission. It is used as a pointer to determine which of the following registers will be written or read. Table 5: Command byte Command Register
0 Input port register
1 Output port register
2 Polarity inversion register
3 Configuration register
Figure 3: Block diagram of PI4IOE5V9521 Note: All I/Os are set to inputs at reset.
2016-02-0002 PT0564-1 03/29/16 PI4IOE5V9521 2-bit I2C-bus and SMBus low power I/O port with interrupt and reset ii. Register 0 : Input Port register This register is a read -only port. It reflects the incoming logic levels of the pins, regardless of whether the pin is defined as an input or an output by Register 2. Writes to this register have no effect. The default value ‘X’ is determined by the externally applied logic level. Table 6: Register 0 – Description of Input Port register bit Bit 7 6 5 4 3 2 1 0 Symbol I7 I6 I5 I4 I3 I2 I1 I0 Default 1 1 1 1 1 1 X X iii. Register 1 : Output Port register This register is an output-only port. It reflects the outgoing logic levels of the pins defined as outputs by Registers 3. Bit values in this register have no effect on pins defined as inputs. In turn, reads from this registe r reflect the value that is in the flip -flop controlling the output selection, not the actual pin value. Table 7: Register 1 – Description of Output Port register bit Bit 7 6 5 4 3 2 1 0 Symbol O7 O6 O5 O4 O3 O2 O1 O0 Default 1 1 1 1 1 1 1 1 iv. Register 2 : Polarity Inversion register This register allows the user to invert the polarity of the Input port register data. If a bit in this register is set (written with ‘1’), the Input port data polarity is inverted. If a bit in this register is cleared (writ ten with a ‘0’), the Input port data polarity is retained. Table 8: Register 2 – Description of Polarity Inversion register bit Bit 7 6 5 4 3 2 1 0 Symbol N7 N6 N5 N4 N3 N2 N1 N0 Default 0 0 0 0 0 0 0 0 v. Register 3 : Configuration register This register configures the directions of the I/O pins. If a bit in this register is set (written with ‘1’), the corresponding port pin is enabled as an input with high-impedance output driver. If a bit in this register is cleared (written with ‘0’), the correspondin g port pin is enabled as an output. At reset, the IOs are configured as inputs. Table 9: Register 3 – Description of Configuration register bit Bit 7 6 5 4 3 2 1 0 Symbol C7 C6 C5 C4 C3 C2 C1 C0 Default 1 1 1 1 1 1 1 1
2016-02-0002 PT0564-1 03/29/16 PI4IOE5V9521 2-bit I2C-bus and SMBus low power I/O port with interrupt and reset c. Power-on reset When power is appl ied to VCC, an internal power -on reset holds the PI4IOE5V9521 in a reset condition until VCC has reached V POR. At that point, the reset condition is released and the PI4IOE5V9521 registers and SMBus state machine will initialize to their default states. Th ereafter, VCC must be lowered below 0.2 V to reset the device. For a power reset cycle, VCC must be lowered below 0.2 V and then restored to the operating voltage. d. Interrupt output (INT) The open-drain interrupt output (INT) is activated when one of the port pins changes state and the pin is configured as an input. The interrupt is de-activated when the input returns to its previous state or the Input Port register is read. Note that changing an I/O from an output to an input may cause a false interrupt to occur if the state of the pin does not match the contents of the input Port register. e. RESET input A reset can be accomplished by holding the RESET pin LOW for a minimum of tw(rst). The PI4IOE5V9521 registers and I2C- bus state machine will be held in their default state until the RESET input is once again HIGH. f. I/O port When an I/O is configured as an input, FETs Q1 and Q2 are off, creating a high-impedance input. The input voltage may be raised above VCC to a maximum of 5.5 V. If the I/O is configured as an output, then either Q1 or Q2 is on, depending on the state of the Output Port register. Care should be exercised if an external voltage is applied to an I/O configured as an output because of the low -impedance path that exists between the pin and either VCC or GND. Figure 4: Simplified schematic of I/Os After power-on reset, all registers return to default values.
2016-02-0002 PT0564-1 03/29/16 PI4IOE5V9521 2-bit I2C-bus and SMBus low power I/O port with interrupt and reset Mechanical Information UQFN-8 (XT) Figure 12. Package outline UQFN-8 (XT)
Ordering Information
Part No. Package Code Package PI4IOE5V9521XTEX XT 8-pin UQFN 1.6x1.6, Tape & Reel Note: E = Pb-free and Green Adding X Suffix= Tape/Reel Pericom Semiconductor Corporation 1-800-435-2336 www.pericom.com Pericom reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. Pericom does not assume any responsibility for use of any circuitry described other than the circuitry embodied in Pericom product. The company makes no representations that circuitry described herein is free from patent infringement or other rights, of Pericom.