PI49FCT3802 PERICOM | Alldatasheet

Document overview

  • PDF pages: 6

Technical content

Features

  • High Frequency >156 MHz
  • High-speed, low-noise, non-inverting buffer - PI49FCT3802 is 1:5 buffer - PI49FCT3803 is 1:7 buffer
  • Low-skew (<250ps) between any two output clocks
  • Low duty cycle distortion <250ps
  • Low propagation delay <2.5ns
  • 5V Tolerant input
  • Multiple VDD, GND pins for noise reduction
  • 3.3V supply voltage
  • Packaging (Pb-free & Green available): - 16-pin TSSOP (L) - 16-pin QSOP (Q) 1:5/1:7 Clock Buffer for Networking Applications PI49FCT3802/PI49FCT3803

Description

The PI49FCT380x is a 3.3V compatible, high-speed, low-noise non-inverting clock buffer. The key goal in designing the PI6C380x is to target networking applications that require low- skew, low-jitter, and high-frequency clock distribution. Providing output-to-output skew as low as 250ps, the PI49FCT380x is an ideal clock distribution device for synchronous systems. Designing synchronous networking systems requires a tight level of skew from a large number of outputs. CLK4 CLK2 CLK1 CLK0 BUF_IN CLK3 VDD 4 CLK1 5 CLK0 NC 7 VDD 8 GND VDD CLK3 GND VDD NC GND BUF_IN GND CLK2 CLK4 Pin Configuration (PI49FCT3802) 16-Pin L, Q Block Diagram (PI49FCT3803) CLK6 CLK2 CLK1 CLK0 BUF_IN CLK3 VDD 4 CLK1 5 CLK0 CLK2 7 VDD 8 GND VDD CLK5 GND VDD CLK3 GND BUF_IN GND CLK4 CLK6 Pin Configuration (PI49FCT3803) 16-Pin L, Q Pin Description Pin Name Description3802 3803 BUF_IN CLK[0:4] GND VDD BUF_IN CLK[0:4] GND VDD Input Outputs GND Power

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1:5/1:7 Clock Buffers for Networking Applications Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional op- eration of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Notes: 1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VDD = 3.3V , +25°C ambient and maximum loading. 3. VOH = VDD– 0.6V at rated current. 4. This parameter is determined by device characterization but is not production tested. 5. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. Operating Range Parameters Description Test Conditions(1) Min. Typ.(2) Max. Units VIH Input HIGH V oltage Guaranteed Logic HIGH Level (Input Pins) 2.0 5.5 VVIL Input LOW V oltage Guaranteed Logic LOW Level (Input Pins) -0.5 0.8 IIH Input HIGH Current VDD = Max. VIN = VDD 1 µAIIL Input LOW Current VDD = Max. VIN = GND -1 VIK Clamp Diode V oltage VDD = Min., IIN = –18mA -0.7 -1.2 VVOH Output HIGH V oltage VCC = Min., VIN = VIH or VIL IOH = –0.1mA VDD-0.2 VOL Output LOW V oltage VCC = Min., VIN = VIH or VIL IOH = 0.1mA 0.2 IOH = 12mA 0.3 0.5 IOH Output HIGH Current VDD = 3.0V , VIN = VIH OR VIL, VOUT = 1.5V(4) -45 -75 -180 mAIOL Output LOWCurrent VDD = 3.0V , VIN = VIH OR VIL, VOUT = 1.5V(4) 50 92 200

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1:5/1:7 Clock Buffers for Networking Applications Notes: 1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device. 2. Typical values are at VDD = 3.3V , +25°C ambient. 3. Per TTL driven input (VIN = VDD – 0.6V); all other inputs at VDD or GND. Capacitance (TA = 25°C, f = 1 MHz) Parameters(1) Description Test Conditions Typ Max. Units CIN Input Capacitance VIN = 0V 3.0 4 pFCOUT Output Capacitance VOUT = 0V — 6 Note: 1. This parameter is determined by device characterization but is not production tested. Power Supply Characteristics Parameters Description Test Conditions Min. Typ.(2) Max. Units IDDQ Quiescent Power Supply Current VDD = Max. VIN = GND or VDD 0.1 30 µA ∆IDD Supply Current per Inputs @ TTL High VDD = Max. VIN = VDD -0.6V(3) 47 300 IDD Dynamic Supply Current VDD = 3.6V , No load

50 MHz 43

67 MHz 56

80 MHz 66

100 MHz 81

125 MHz 97

156 Mhz 121

Notes: 1. See test circuit and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. Skew measured at worse cast temperature (max. temp). 4. Identical conditions: loading, transitions, supply voltage, temperature, package type and speed grade. Switching Characteristics (VDD = 3.3V ± 0.3V , TA = 85°C) Parameters Desciription Test Conditions Min. Typ. Max. Units tR/tF CLKn Rise/Fall Time 0.8V ~ 2.0V CL = 15pF,

125 Mhz

0.7 1.0 nstPLH tPHL Propagation Delay BUF_IN to CLKn 1.0 2.2 2.5 tsk(o)(3) Skew between two outputs of the same package (same transition) 110 250 ps tsk(p)(3) Skew between opposite transitions (tPHL - tPLH) of the same output 200 250 tsk(t)(3) Skew between two outputs of different packages(4) 0.55 ns

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1:5/1:7 Clock Buffers for Networking Applications Switching Waveforms Propagation Delay Package Skew – tSK(T) Pulse Skew – tSK(P) Output Skew – tSK(O) Input tPLH 1.5V Output VOH 1.5V VOL tPHL 2.0V 0.8V tR tF Input tPLH 1.5V Output VOH 1.5V VOL tPHL tSK(p) = | tPHL – tPLH | Input tPLHx 1.5V CLKx VOH 1.5V VOL tPHLx tSK(o) CLKy VOH 1.5V VOL tSK(o) tPLHy tPHLy tSK(o) =  tPLHy – tPLHx  or  tPHLy – tPHLx  Input tPLH1 1.5V Package 1 Output VOH 1.5V VOL tPHL1 tSK(t) Package 2 Output VOH 1.5V VOL tSK(t) tPLH2 tPHL2 tSK(t) =  tPLH2 – tPLH1  or  tPHL2 – tPHL1  Test Circuits for All Outputs Definitions: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance, should be equal to Zout of the Pulse Generator. Pulse Generator D.U.T. VIN VOUT CL VDD

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1:5/1:7 Clock Buffers for Networking Applications .189 .197 .053 .069 .004 .010 SEATING PLANE .025 BSC .007 .010 .228 .244 .150 .157 .016 .050 X.XX X.XX DENOTES DIMENSIONS IN MILLIMETERS 0.635 4.80 5.00 1.35 1.75 5.79 6.19 0.101 0.254.008 .012 0.203 0.305 3.81 3.99 0.178 0.254 0.38 0.41 1.27 .008 0.203 .015 x 45° REF Detail A Detail A .008 0.20 MIN. Guage Plane .010 0.254 .041 1.04 REF .016 .035 0.41 0.89 0˚-6˚ .008 .013 0.20 0.33 .193 .201 .047 max. .002 .006 SEATING PLANE .0256 BSC .018 .030 .004 .008 .252 BSC .169 .177 0.05 0.15 6.4 0.45 0.75 0.09 0.20 4.3 4.5 1.20 4.9 5.1 0.65 0.19 0.30 .007 .012 Packaging Mechanical: 16-Pin QSOP (Q) Packaging Mechanical: 16-Pin TSSOP (L)

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1:5/1:7 Clock Buffers for Networking Applications Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com

Ordering Information

Ordering Code Package Code Package Description PI49FCT3802L L 16-pin TSSOP PI49FCT3802LE L Pb-free & Green, 16-pin TSSOP PI49FCT3802Q Q 16-pin QSOP PI49FCT3802QE Q Pb-free & Green, 16-pin QSOP PI49FCT3803L L 16-pin TSSOP PI49FCT3803LE L Pb-free & Green, 16-pin TSSOP PI49FCT3803Q Q 16-pin QSOP PI49FCT3803QE Q Pb-free & Green, 16-pin QSOP Notes: 1. Thermal characteristics can be found on the web at www.pericom.com/packaging/