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Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 7
Technical content
Features
- High Frequency >150 MHz
- High-speed, low-noise, non-inverting clock buffer – PI49FCT20802 is a 1:5 buffer – PI49FCT20803 is a 1:7 buffer
- Low skew < 150ps
- Low duty cycle distortion < 300ps
- Low propagation delay < 3.5ns
- Multiple V DD, GND pins for noise reduction
- 2.5V supply voltage and 3V tolerant input
- Packages: - 16-pin TSSOP (L) - 16-pin QSOP (Q) 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1:5/1:7 2.5V Clock Buffer for Networking Applications PI49FCT20802/ PI49FCT20803
Description
The PI49FCT2080x is 2.5V, high-speed, low noise, non-inverting clock buffer. It is designed to target networking applications that require low-skew, low-jitter, and high-frequency clock distribution. It provides output-to-output skew as low as 150ps, and is an ideal clock distribution device for synchronous systems. PI49FCT2080x is a clock buffer from a single input that produces five outputs on PI49FCT20802 and seven outputs on PI49FCT20803. PI49FCT2080x is characterized for operation from –40 °C to 85°C. VDD 4 CLK1 5 CLK0 NC 7 VDD 8 GND VDD CLK3 GND VDD NC GND BUF_IN GND CLK2 CLK4 CLK4 CLK2 CLK1 CLK0 BUF_IN CLK3 Pin Configuration (PI49FCT20803) VDD 4 CLK1 5 CLK0 CLK2 7 VDD 8 GND VDD CLK5 GND VDD CLK3 GND BUF_IN GND CLK4 CLK6 CLK6 CLK2 CLK1 CLK0 BUF_IN CLK3 . . . Block Diagram (PI49FCT20802) Block Diagram (PI49FCT20803)
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1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 PI49FCT20802/PI49FCT20803 1:5/1:7 2.5V Clock Buffer for Networking Applications Notes: 4. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device. 5. Typical values are at V DD = 2.5V, +25°C ambient and maximum loading. 6. Per TTL driven input (VIN = VDD – 0.6V); all other inputs at VDD or GND. Capacitance (TA = 25°C, f = 1 MHz) Note: 7. This parameter is determined by device characterization but is not production tested. sretemaraPn oitpircseDs noitidnoCtseT )4( .niM. pyT )5( .xaMs tinU I QDD tnerruCylppuSrewoPtnecseiuQV NI Vro0= DD 1.00 2 Aµ ∆ I DD stupnIreptnerruCylppuSV NI V= DD V6.0– )6( 740 03 I DD )1hparGeeS(tnerruCylppuScimanyDV DD ,daolmho-33&Fp51,V7.2= zHM051=f 631A m Power Supply Characteristics Graph 1. Dynamic Current vs. Clock Frequency 160 140 120 100 Clock Frequency [MHz] Dynamic Current - IDD [mA] 0 50 100 150 200 Load = 15pF & 33 ohms Load = 0 sretemaraPn oitpircseDs noitidnoCtseTp yT )7( .xaMs tinU C NI ecnaticapaCtupnIV NI V0=3 4 Fp C TUO ecnaticapaCtuptuOV TUO V0=6
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1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 PI49FCT20802/PI49FCT20803 1:5/1:7 2.5V Clock Buffer for Networking Applications Switching Waveforms Propagation Delay Package Skew – tSK(T) Pulse Skew – tSK(P) Output Skew – tSK(O) Input tPLHx 1.5V CLKx VOH 1.5V VOL tPHLx tSK(o) CLKy VOH 1.5V VOL tSK(o) tPLHy tPHLy tSK(o) = tPLHy – tPLHx or tPHLy – tPHLx Input tPLH1 1.5V Package 1 Output VOH 1.5V VOL tPHL1 tSK(t) Package 2 Output VOH 1.5V VOL tSK(t) tPLH2 tPHL2 tSK(t) = tPLH2 – tPLH1 or tPHL2 – tPHL1 Input tPLH 1.25V Output VOH 1.25V VOL tPHL 2.0V 0.6V tR tF Input tPLH 1.5V Output VOH 1.5V VOL tPHL tSK(p) = | tPHL – tPLH |
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1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 PI49FCT20802/PI49FCT20803 1:5/1:7 2.5V Clock Buffer for Networking Applications .193 .201 .047 max. .002 .006 SEATING PLANE.0256 BSC .018 .030 .004 .008 .252 BSC .169 .177 X.XX X.XX DENOTES CONTROLLING DIMENSIONS IN MILLIMETERS 0.05 0.15 6.4 0.45 0.75 0.09 0.20 4.3 4.5 1.20 4.9 5.1 0.65 0.19 0.30 .007 .012 .189 .197 .053 .069 .004 .010 SEATING PLANE .025 BSC .007 .010.228 .244 .150 .157 .016 .050 X.XX X.XX DENOTES DIMENSIONS IN MILLIMETERS 0.635 4.80 5.00 1.35 1.75 5.79 6.19 0.101 0.254 .008 .012 0.203 0.305 3.81 3.99 0.178 0.254 0.38 0.41 1.27 .008 0.203 .015 x 45° REF Detail A Detail A .008 0.20 MIN. Guage Plane .010 0.254 .041 1.04 REF .016 .035 0.41 0.89 0˚-6˚ .008 .013 0.20 0.33 Packaging Mechanical: 16-Pin TSSOP (L) Packaging Mechanical: 16-Pin QSOP (Q)
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Ordering Information
Ordering Code Package Code Package Description PI49FCT20802Q Q 16- pin 150-mil wide QSOP PI49FCT20802QE Q Pb-free & Green, 16-pin 150-mil wide QSOP PI49FCT20802L L 16-pin 173-mil wide TSSOP PI49FCT20802LE L Pb- free & Green, 16-pin 173-mil wide TSSOP PI49FCT20803Q Q 16- pin 150-mil wide QSOP PI49FCT20803QE Q Pb-free & Green, 16-pin 150-mil wide QSOP PI49FCT20803L L 16-pin 173-mil wide TSSOP PI49FCT20803LE L Pb- free & Green, 16-pin 173-mil wide TSSOP Notes: 1. Thermal characteristics can be found on the company web site at www.pericom.com/packaging/