PI3WVR31212A

DATASHEET SEARCH SITE | WWW.ALLDATASHEET.COM

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 25

Technical content

Features

Î Î DP/HDMI 1:2 De-multiplexer switch with 4 high speed differential channel and AUX/DDC, HPD and CAB_DET signal channels Î ÎOne passive output ports for DP1.2 at 5.4Gbps Î ÎOne active output port with integrated DP to HDMI re- driver (level shifter) supports HDMI 1.4 at 3.4Gbps Î Î Pin control mode supports auto port priority selection Î Î Pin control mode supports port2 with DDC bi-direction buffer switch only Î Î I2C control mode supports auto port priority selection Î Î I2C control mode supports port2 with 8 levels equalization and 5 levels pre-emphasis Î Î I2C control mode supports port2 with either DDC bi- direction buffer switch or DDC passive switch Î Î Very low operating power when passive port1 is selected Î Î 3.3V power supply Î Î 2KV HBM ESD protection for all I/O pins of port1 and all control pins Î Î 8kV contact ESD (IEC61000-4-2) protection for all output pins in port2 Î Î Packaging: 0 pin TQFN package (5x9mm, 0.4mm pitch) Î ÎSupport Type 2 cable ID register

Description

PI3WVR31212A has one passive output port1, one active (DP to HDMI) output port2. Passive output supports DP1.2 at 5.4Gbps in I2C mode. Active port2 supports HDMI1.4b at 3.4Gbps.All two output ports support auto port priority selection. Input port accepts DP1.2 and DP++ signals associated with output ports as described above. Application Î ÎNotebook and dongle PI3WVR31212A DP/HDMI 1:2 De-multiplexer switches Pin Configuration: TQFN-60 52 51 22 23 24 25 2621 27 30 29 28 54 5356 5558 5760 59 Center Pad TQFN-60 5x9 mm OEB SCL SDA VDD HPD_SRC CAB_SRC D0P D0N D1P D1N D2P D2N D3P D3N SDA_CTL/PRI_SEL SCL_CTL/EQ I2C_A1/PRE_EMP I2C_A2/ROUT_SEL HPD2 GND CLKN2 CLKP2 VDD D0N2 D0P2 D1N2 D1P2 VDD D2N2 D2P2 VDD D0P1 D0N1 D1P1 D1N1 D2P1 D2N1 D3P1 D3N1 GND NC NC NC GND NC NC GND CEXT HPD1 MS AUXN AUXP SCL2 SDA2 GND GND NC AUX1P/SCL1 AUX1N/SDA1 CAB_1 15-0163

DP/HDMI 1:2 De-multiplexer switches www.pericom.com 12/15/15 All trademarks are property of their respective owners. Block Diagram VDD LDO CEXT CAB_SRC HPD_SRC 120K/uni03A9 120K/uni03A9 HPD1 HPD2 CAB_1 100K/uni03A9 pull High AUXP AUXN SDA SCL AUX1P/SCL1 AUX1N/SDA1 SDA2 SCL2 D[0:3]P1 D[0:3]N1 D[0:3]P D[0:3]N D[0:3]P2 D[0:3]N2 GND Rpd Rpd RT RT 0//VDD VDD ROUT ROUT Port select OEB MS PRI_SEL EQ PRE_EMP ROUT_SEL Control & Status Register I2C Controller SDA_CTL SCL_CTL (share pins) I2C_A1, A2 (share pins) Cable ID 15-0163

DP/HDMI 1:2 De-multiplexer switches www.pericom.com 12/15/15 All trademarks are property of their respective owners. Pin# Pin Name Signal Type Description D0P D1P D2P D3P D0N D1N D2N D3N IO 4 differential pair input (DP) D0P1 D1P1 D2P1 D3P1 D0N1 D1N1 D2N1 D3N1 IO 4 differential pair output (DP) for port 1 D0P2 D1P2 D2P2 CLKP2 D0N2 D1N2 D2N2 CLKN2 IO 4 differential pair output (HDMI) for port 2 AUX1N/SDA1 AUX1P/SCL1 SDA2 SCL2 IO AUX (DP) or DDC (HDMI) to two ports AUXN AUXP IO AUX to DP-source SDA SCL IO DDC to DP-source HPD1 HPD2 HPD_SRC I I O HPD1-2 for port1-2; HPD_SRC to DP-source. Pin Description 15-0163

DP/HDMI 1:2 De-multiplexer switches www.pericom.com 12/15/15 All trademarks are property of their respective owners. Pin# Pin Name Signal Type Description CAB_1 CAB_SRC IO CAB_1: CAB_DET to port1 CAB_SRC: CAB_DET to DP-source No CAB_DET for HDMI port2

1 OEB I OEB=0, device active; OEB=1, device shut down

15 SDA_CTL/PRI_SE I

MS=0, PRI_SEL selects priority in pin control mode; MS=1, SDA_CTL as SDA in I2C control mode

16 SCL_CTL/EQ IO

MS=0, EQ selects equalization in pin control mode; MS=1, SCL_CTL as SCL in I2C control mode

17 I2C_A1/PRE_EMP I

MS=0, PRE_EMP selects Pre-emphasis in pin control mode; MS=1, I2C_A1 as I2C address A1 in I2C control mode

18 I2C_A2/ROUT_SEL I

MS=0, ROUT_SEL selects source termination in pin control mode; MS=1, I2C_A2 as I2C address A2 in I2C control mode

31 MS I

Mode Select: MS=0 for pin control mode MS=1 for I2C control mode 33 CEXT O Internal LDO bypass capacitance, 4.7uf to GND 4, 23, 28, 50 VDD Power 3.3V VDD Center Pad GND Ground Bottom GND EPAD 35, 36, 38, 39, 40, 54 NC NC Not Connected 15-0163

DP/HDMI 1:2 De-multiplexer switches www.pericom.com 12/15/15 All trademarks are property of their respective owners. Pin mapping for dual mode DP source DEMUX to DP output DP mode HDMI/DVI mode WVR31212A input pins WVR31212A port1 output WVR31212A port2 output ML_lan0(P) TX2+ D0P D0P1 D2P2 ML_lan0(N) TX2- D0N D0N1 D2N2 ML _lan1(P) TX1+ D1P D1P1 D1P2 ML_lan1(N) TX1- D1N D1N1 D1N2 ML_lan2(P) TX0+ D2P D2P1 D0P2 ML_lan2(N) TX0- D2N D2N1 D0N2 ML_lan3(P) TXC+ D3P D3P1 CLKP2 ML_lan3(N) TXC- D3N D3N1 CLKN2 Function Description The MS pin selects I2C or pin control mode. Pin control mode has only automatic port selection. I2C control mode has automatic port selection. In auto port selection, when only one HPD high detected, the port with HPD high will be selected. When multiple HPD high detected, the PRI_SEL pin (priority select) will determine the priority of the 2 ports. See priority selection table When PRI_SEL=low or High, the port-priority will be port1-port2 from high to low; when PRI_SEL=M (open as not connected), the port priority will be port2-por1 from high to low. When port 1 is selected and CAB_1 is low as in DP mode, the AUX/DDC channels will work as AUX channels. AUXP shall have 100Kohm external resistor to GND and AUXN shall have 100Kohm external resistor to VDD. The data rate of AUX channels will be >720Mbps.The internal DDC switch will be off. When port 1 is selected and CAB_1 is high when DP to HDMI adapter plugged, the AUX/DDC channels will work as DDC channels. The internal DDC channels are on and the AUX channels are off. The input of DDC channels can tolerate 5V input and voltage of DDC to source will be limited about 3.3V or below. When port 1 is selected (passive ports), port2 with HDMI re-driver will shut down. When port 2 is selected, the internal DP to HDMI level shifter will be enabled. There will be 3 EQ and 3 Pre-emphasis settings in pin control mode, 8 EQ and 5 Pre-emphasis settings in I2C control mode. When port 2 is selected, HDMI output can be standard TMDS-open-drain source, as well to be selected with internal source termina- tion as 50 ohm pull up to 3.3V VDD, using ROUT_SEL pin control or I2C control. When port 2 is active as DP to HDMP level shifter, the DDC channel can be selected between bi-direction DDC buffer and passive DDC switch in I2C mode. HPD1, HPD2 are with internal CMOS buffers and can support 3.3V and 5V HPD inputs. Squelch Mode Squelch function will disable HDMI data output (as high impedance)when the voltage and frequency of input clock (TMDS) are below squelch threshold, which will prevent random noise presenting in HDMI data output, thereby prevent noise on sink display. Squelch function will enable-resume HDMI data output when input clock signals are above squelch threshold. 15-0163

DP/HDMI 1:2 De-multiplexer switches www.pericom.com 12/15/15 All trademarks are property of their respective owners. Truth Table for TMDS port2 EQ Equalization value 0 1.5dB open 4.0dB 1 6.5dB EQ – three level pin control P RE-EMP – three level pin control PRE_EMP TX pre-emphasis 0 0dB open 1.5dB 1 2.5dB ROUT_SEL Pull-Up Resistors on port2 D[0:2]P2/N2, CLKP2/N2

0 No Pull-up resistors

1 50Ω Pull-up resistors to VDD 1 6.5dB ROUT_SEL Truth Table for AUX and DDC PORT DP/HDMI CAB_1 AUXP AUXN SCL SDA When Port1 Selected DP Mode 0 AUX1P AUX1N Hi-Z Hi-Z DP Mode 1 Hi-Z Hi-Z SCL1 SDA1 Priority Selection Table PRI_SEL (Priority order) HPD1 HPD2 HPD_SRC CAB_SRC AUXP/AUXN SDA/SCL 0 or 1 0 0 Hi-Z Hi-Z Hi-Z Hi-Z 0 or 1 1 x HPD1 CAB1 AUX1P/AUX1N SDA1/SCL1 0 or 1 0 1 HPD2 High Hi-Z SDA2/SCL2 M 0 0 Hi-Z Hi-Z Hi-Z Hi-Z M 1 0 HPD1 CAB1 AUX1P/AUX1N SDA1/SCL1 M x 1 HPD2 High Hi-Z SDA2/SCL2 Note: M=internal half VDD when input=HiZ PRI_SEL (Priority order) HPD1 HPD2 D0P D1P D2P D3P D0N D1N D2N D3N 0 or 1 0 0 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z 0 or 1 1 x D0P1 D1P1 D2P1 D3P1 D0N1 D1N1 D2N1 D3N1 0 or 1 0 1 D2P2 D1P2 D0P2 CLKP2 D2N2 D1N2 D0N2 CLKN2 M 0 0 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z M 1 0 D0P1 D1P1 D2P1 D3P1 D0N1 D1N1 D2N1 D3N1 M x 1 D2P2 D1P2 D0P2 CLKP2 D2N2 D1N2 D0N2 CLKN2 Note: M=internal half VDD when input=HiZ MS Pin mode/type cable ID

0 Pin mode for Type 2 ID

M(0.5*vdd) Pin mode for Type 1 ID

1 I2C mode

MS – three level pin control 15-0163

DP/HDMI 1:2 De-multiplexer switches www.pericom.com 12/15/15 All trademarks are property of their respective owners.

Electrical Characteristics

Recommended Operation Conditions VDD = 3.3V ±10%, Min and Max apply for TA between -40oC to 85oC Typical values are referenced to TA = 25oC Parameter Description Test Conditions Min. Ty p. Max. Unit VDD Operating Voltage 3.0 3.3 3.6 V IDD VDD supply current (Port1 active) VDD=3.3V 1 1.8 mA VDD Supply Current (Port2 active) Output Enable ( open drain 500mv signal-end 0dB pre-emphasis, not including 40mA current to source) 80 100 mA Output Enable ( double termination, 500mv signal-end 0dB pre-empha- sis, not including 40mA current to source) 160 200 mA I DDQ VDD Quiescent Supply Current (port2 active w/o TMDS input) TMDS Output Disable, 3.5 5 mA Istb Standby mode by I2C VDD=3.6V, OEB = Low, Port1/2 selection, HPD_1,2=0, MS=1 0.6 1.2 mA Isd1 Supply shut down current when OEB disable (MS=0) V DD=3. 6 V,OE B =h ig h 0.1 0.2 uA Isd2 Supply shut down current when OEB disable (MS=1) V DD=3. 6 V,OE B =h ig h 0.6 1.2 mA High Speed Channel Input Voltage (DP Mode) DDC and HPD channels Input Voltage DC Output Current Power Dissipation Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indi - cated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Maximum Ratings (Above which useful life may be impaired. For user guidelines, not tested.) 15-0163

DP/HDMI 1:2 De-multiplexer switches www.pericom.com 12/15/15 All trademarks are property of their respective owners. Parameter Description Test Conditions Min. Ty p. Max. Unit OEB,MS,ROUT_SEL IIH High level digital input current V IH =VDD -10 40 μA IIL Low level digital input current V IL = GND -10 10 μA VIH High level digital input voltage 2.0 V VIL Low level digital input voltage 0 0.8 V HPD_SRC VOL_HPD_SRC Buffer Output Low Voltage I OL = 4 mA 0.4 V VOH_HPD_SRC Buffer Output Low Voltage I OH = 4 mA 2.4 V HPD_sink IIH High level digital input current(1) V IH =VDD -10 40 μA IIL Low level digital input current(1) V IL = GND -10 10 μA VIH High level digital input voltage V DD=3.3V 2.0 V VIL Low level digital input voltage 0 0.8 V CAB ILK Input leakage current Switch is off, Vin=5.5v -50 50 uA CIO Input/Output capacitance when- passive switch on 10 pF RON Passive Switch resistance IO = 3mA, VO = 0.4V 25 50 Ω Vpass Switch Output voltage VI=3. 3V, II=100uA 1.5 3.0 3.3 V CI(source) Source side CAB capacitance VI peak-peak = 1V, 100 KHz 3.5 pF CI(sink) Sink side CAB capacitance when 6.5 pF SDA/SCL, SDA1/SCL1 ILK Input leakage current DDC switch is off, Vin=5.5V -50 50 uA CIO Input/Output capacitance when passive switch on V I peak-peak = 1V, 100 KHz 8 pF RON Passive Switch resistance IO = 3mA, VO = 0.4V 25 50 Ω Vpass Switch Output voltage VI=5.0V, II=100uA VDD=3.3V 1.5 3.0 3.6 V CI(source) Source side DDC capacitance ( passive switch off. ) V I peak-peak = 1V, 100 KHz 2.5 pF CI(sink) Sink side DDC capacitance ( pas- sive switch off. ) V I peak-peak = 1V, 100 KHz 5 pF SDA2/SCL2 ( DDC buffer of port2 active) VIH High level input voltage VDD=3.3V 2.0 V VIL Low level input voltage 0 0.8 V ILK Input leakage current DDC switch is off, Vin = 5.5V -10 10 uA 15-0163

DP/HDMI 1:2 De-multiplexer switches www.pericom.com 12/15/15 All trademarks are property of their respective owners. Parameter Description Test Conditions Min. Ty p. Max. Unit IIL Low level input current VIL = 0.2V -10 10 μA VOL Low level output voltage IOL = 4mA 0.2 V ILOH HIGH-level output leakage cur- rent VO=3.6V 10 μA CIO Input/output capacitance VI = 3 V or 0 V; VCC = 3.3 V or 0V 4 pF SDA/SCL (DDC buffer of port2 active) VIH High level input voltage VDD=3.3V 2.0 V VIL Low level input voltage 0 0.4 V ILK Input leakage current DDC switch is off, Vin = 5.5V -10 10 uA IIL Low level input current VIL = 0.2V -10 10 μA VOL Low level output voltage IOL = 4mA 0.47 0.52 0.6 V ILOH HIGH-level output leakage cur- rent VO=3.6V 5 10 μA CIO Input/output capacitance VI = 3 V or 0 V; VCC = 3.3 V or 0V 8 pF AUXP ,AUXN, AUXnP/SCLn, AUXnN/SDAn ILK Input leakage current DDC switch is off, Vin=5.5V -50 50 uA CIO Input/Output capacitance when passive switch on VI peak-peak = 1V, 100 KHz 6 pF RON Passive Switch resistance IO = 3mA, VO = 0.3V 5 Ω IO = 3mA, VO = 3.0V 10 Ω Vpass Switch Output voltage VI=5. 5 V, II=100uA VDD=3.3V 3.8 4 V CI(source) Source side capacitance ( passive switch off. ) V I peak-peak = 1V, 100 KHz 2.5 pF CI(sink) Sink side capacitance ( passive switch off. ) V I peak-peak = 1V, 100 KHz 3.5 pF High Speed Channel (D[0:3]P/N – D[0:3]P1N1) VIK Clamp Diode Voltage (HS Chan- nel) V DD = Max., IIN = –18mA –1.6 –1.8 V IIH Input HIGH Current VDD = Max., VIN = VDD ±10 µA IIL Input LOW Current VDD = Max., VIN = GND ±10 RON_HS On resistance between input to out- put for high speed signals V INPUT,cm = 0V to 1.8V, VINPUT,diff < 1.0Vp-p, diff, VDD = 3.0V, IINPUT =

8 Ohm

VINPUT,cm = 2.2V to 3.1V, VINPUT,diff < 1.2Vp-p, diff, VDD = 3.0V, IINPUT = 20mA

DP/HDMI 1:2 De-multiplexer switches www.pericom.com 12/15/15 All trademarks are property of their respective owners. Parameter Description Test Conditions Min. Ty p. Max. Unit High Speed Channel (D[0:3]P/N – D[0:2]P2/N2; CLKP2/N2) VI(open) Single-ended input voltage under high impedance input or open input I L=10uA VDD-10 VDD+10 mV RT Input termination resistance VIN=2.9V 45 50 66 ohm IOZ Leakage current resistance V DD=3. 6 V, OE B =H ig h 30 100 uA Ioff Power off leakage current V DD=0, VIN=3.6V -50 50 uA Dynamic Electrical Characteristics over Operating Range (TA = -40º to +105ºC, VDD = 3.3V ±10%) Parameter Description Test Conditions Min. Ty p. Max. Unit TMDS Differential Pins tpd Propagation delay VDD = 3.3V, Rout = 50Ω off, open drain, 0dB pre-emphasis 2000 ps tr Differential output signal rise time (20% - 80%) 120 tf Differential output signal fall time (20% - 80%) 120 t sk(p) Pulse skew 15 50 tsk(D) Intra-pair differential skew 25 50 tsk(o) Inter-pair differential skew(2) 100 Tjit_clk (pp) Peak-to-peak output jitter CLK residual jitter Data Input = 3.4 Gbps HDMI data pattern from signal generation, short trace. CLK Input = 340 MHz clock 15 40 T jit_dat(pp) Peak-to-peak output jitter DATA Residual Jitter 25 50 ten Enable time 10 us tdis Disable time 50 SCL,SDA channel, AUX channel , CAB channel : passive switches tpd(DDC) Propagation delay from SCLn/ SDAn to SCL/SDA or SCL/SDA to SCLn/SDAn In passive SW on. C L = 10pF, in passive switch 5 ns SCL2,SDA2- SCL,SDA channel : buffers tPLH LOW-to-HIGH propagation delay SCL/SDA to SCL2/SDA2 50 100 150 ns tPHL HIGH-to-LOW propagation delay SCL/SDA to SCL2/SDA2 10 20 40 ns tPLH LOW-to-HIGH propagation delay SCL2/SDA2 to SCL/SDA 50 100 150 ns tPHL HIGH-to-LOW propagation delay SCL2/SDA2 to SCL/SDA 10 20 40 ns 15-0163

DP/HDMI 1:2 De-multiplexer switches www.pericom.com 12/15/15 All trademarks are property of their respective owners. Parameter Description Test Conditions Min. Ty p. Max. Unit Control and Status Pins (HPDn, HPD_SRC) tpd(HPD) Propagation delay (from HPDx to the active port of HPD_SRC, high to low) CL = 10pF 2 4 us tsx(HPD) Switch time (from port select to the latest HPD , manual selection mode) 2 4 us Dynamic Electrical Characteristics Parameter Description Test Conditions Min. Ty p. Max. Unit High Speed Channel (D[0:3]P/N – D[0:3]P1/N1) XTALK Crosstalk on High Speed Channels See Fig. 1 for Measurement Setup f= 2.7 GHz -32 -30 dB O IRR OFF Isolation on High Speed Channels See Fig. 2 for Measurement Setup f= 2.7 GHz -19 -17 I LOSS Differential Insertion Loss on High Speed Channels @2.7GHZ (see figure 3) -1.7 -1.5 dB Rloss Differential Return Loss on High Speed Channels @ 2.7GHz (5.4Gbps) -18.0 -16.0 dB BW_Dx± Bandwidth -3dB for Main high speed path (Dx±) See figure 3 5.1 5.6 GHz BW_AUX Bandwidth -3dB for AUX See figure 3 1.2 1.5 GHz Tstartup V DD valid to channel enable 250 us Twa keup Enabling output by changing OEB from High to Low 250 us T pd Propagation delay (input pin to output pin) on all channels 80 ps t b-b Bit-to-bit skew within the same differential pair of Dx± channels 5 7 ps t ch-ch Channel-to-channel skew of Dx± channels 35 ps 15-0163

DP/HDMI 1:2 De-multiplexer switches www.pericom.com 12/15/15 All trademarks are property of their respective owners. Fig 1. Crosstalk Setup Fig 2. Off-isolation setup BALANCED PORT1 DUT BALANCED PORT2 BALANCED PORT1 BALANCED PORT2 DUT BALANCED PORT1 BALANCED PORT2 DUT Fig 3. Differential Insertion Loss Differential Off Isolation , Vdd=3.3V, 25C 15-0163

DP/HDMI 1:2 De-multiplexer switches www.pericom.com 12/15/15 All trademarks are property of their respective owners. D0 to D02 Channel D0 to D01 Channel Differential Insertion Loss , Vdd=3.3V, 25C 15-0163

DP/HDMI 1:2 De-multiplexer switches www.pericom.com 12/15/15 All trademarks are property of their respective owners. Differential Return Loss , Vdd=3.3V, 25C D0 to D01 Channel D0 to D02 Channel 15-0163

DP/HDMI 1:2 De-multiplexer switches www.pericom.com 12/15/15 All trademarks are property of their respective owners. HPD auto selection timing waveform HPD from selected-active port HPD_SRC t1 (<2ms) t1 is the IRQ-HPD (sink) from selected-active port Priority Setting HPD_SRC t3 (250ms) All Channels Hi-Z Event of priority setting change Low for HPDs other than HPDx. HPDx is the HPD of the only port with plugging-in HPDx HPD_SRC All Channels Hi-Z HPDx port is active Selected port is active Selected port is active Selected port is active Selected port is active t1 (<2ms) New selected port is active t3 (250ms) All Channels Hi-Z Fig 4. HPD timing t1. HPD_SRC low and the active of selected port will follow t1, if t1 further extended less than t2 (125ms) Fig 5. HPD timing t3. All channels include DP-HDMI data, AUX, DDC, HPD and CAB_DET Fig 6. HPD timing t3 15-0163

DP/HDMI 1:2 De-multiplexer switches www.pericom.com 12/15/15 All trademarks are property of their respective owners. t2 (125ms) t3 (250ms) All Channels Hi-Z New selected port is active HPD_SRC HPD from selected-active Port HPD-high for at least one other port HPD_SRC All Channels Hi-Z HPD from selected-active port HPD_SRC All Channels Hi-Z Selected port is active HPD-high for at least one other port HPD of prioritized Port t3 (250ms) t3 (250ms)Selected port is active Prioritized port is active HPD-low for all other ports Selected port is active Selected port is active t4 (1s) Fig 7. HPD timing. Fig 8. HPD timing Fig 9. HPD timing t4 15-0163

DP/HDMI 1:2 De-multiplexer switches www.pericom.com 12/15/15 All trademarks are property of their respective owners. Offset Name Description Power Up Condition Ty pe 0x00 CONFIG[7:0] [7] Reserved to 0 [6:5] Port SEL1/SEL0 selection control 00 port 1 (Reserved) 01 all off 10 port 2 (Reserved)

11 Auto selection mode depending on PRI_SEL

[4:2] PRI_SEL priority selection control by HPDx 00x port1/port2 010 port1/port2 011 port2/port1 1xx port2/port1 [1] DP_HDMI selection control 0=DP input, 1=Reserved [0] Cable ID type selection 0=Type 2 cable ID 1=Type 1 cable ID 0x01 R/W I2C Control Register The I2C control register uses index read or write for byte access. 15-0163

DP/HDMI 1:2 De-multiplexer switches www.pericom.com 12/15/15 All trademarks are property of their respective owners. 0x01 RX_SET[7:5] for port2; HPD auto selection time [7:5] EQ programmable setting 000: 1.5 dB 001: 4 dB 010: 6.5 dB 011: 9 dB 100: 11.5 dB 101: 4 dB 110: 16.5 dB 111: 19 dB [4:3] HPD auto selection time source control 00: normal 01: -25% 10: +25% 11: test mode [2] HPD auto selection time t3 setting 0: 256ms 1: 128ms [1] HPD auto selection time t4 setting 0: 1024ms 1: 516ms [0] HPD pulse duration treated as IRQ time t1 setting 0: 2ms 1: 4ms 0x00 R/W 15-0163

DP/HDMI 1:2 De-multiplexer switches www.pericom.com 12/15/15 All trademarks are property of their respective owners. 0x02 TX_SET[7:0] for port2 Output setting for HDMI re-driver/level shifter [7] HDMI output control 0: open drain 1: double termination [6:4] HDMI output Pre-emphasis settings 000: 0dB 001: 1.5dB 010: 2.5dB 011: 3.5dB 100: 6dB [3:2] TMDS output swing setting 00: 500mv as default 01: -10% 10: +10% 11: +20% [1] TMDS output slow rate setting 0: as default 1: +10% [0] DP1 and DP2 port 10Kohm pull low control 0=10Kohm pull low on 1=10Kohm pull low off 0x00 R/W 0x03 Pericom ID Pericom Vendor Register ID (refer to PCIE clock buffer) [7:4] Vendor ID 0101 [3:0] device revision 0001 0x51 R 15-0163

DP/HDMI 1:2 De-multiplexer switches www.pericom.com 12/15/15 All trademarks are property of their respective owners. 0x04 HPDx/ CABx[6:0 Read only [7] HPD_SRC output logic function (buffer) 0: HPD_SRC=HPDx 1: HPD_SRC=/HPDx [6] DDC function for port 2 0: Active buffer 1: passive switch [5] Port switching in manual selection 1: disable T3 time pulse when port switching, Port switch immediately 0: Enable T3 time pulse when port switching [4] Reserved [3] HPD2 status as read only [2] Reserved [1] HPD1 status as read only [0] Reserved for HPD1B 0x00 R/W [7:4] R [3:0] 15-0163

DP/HDMI 1:2 De-multiplexer switches www.pericom.com 12/15/15 All trademarks are property of their respective owners. Table of ID registers Data address offset Data as in spec Read/White as in spec Description as in spec WVR31212A 00h 44h RO D D 01h 50h RO P P 02h 2dh RO - - 03h 48h RO H H 04h 44h RO D D 05h 4dh RO M M 06h 49h RO I I 07h 20h RO Space Space 08h 41h RO A A 09h 44h RO D D 0ah 41h RO A A 0bh 50h RO P P 0ch 54h RO T T 0dh 4fh RO O O 0eh 52h RO R R 0fh 04h RO . . 10h A0h RO Cable Adaptor Identifier A0h 11h UD RO IEEE OUI 1st byte 00h 12h UD RO IEEE OUI 2nd byte 60h 13h UD RO IEEE OUI third byte 23h 14h UD RO Device Id 50h “P” 15h UD RO Device Id 49h “I” 16h UD RO Device Id 33h “3” 17h UD RO Device Id 57h “W” 18h UD RO Device Id 56h “V” 19h UD RO Device Id 52h “R” 1ah UD RO Hardware (chip) revision 7:4h: major revision 3:0h: minor revision. 00h 1bh UD RO Firmware/software major revision 00h 1ch UD RO Firmware/software minor revision 00h 1dh UD RO Clock rate, specified max 300mhz for HDMI 78h: 300MHz (300/2.5=120=78h) 1eh 0fh RO I2C speed control capabilities bit map 0fh 15-0163

DP/HDMI 1:2 De-multiplexer switches www.pericom.com 12/15/15 All trademarks are property of their respective owners. Data address offset Data as in spec Read/White as in spec Description as in spec WVR31212A 1fh 00h RW Reserved data Address at 1fh: 1. DP source reads data address 1fh, ID register returns 00h 2. DP source writes data AAh to data address 1fh, ID register responds ACK or returns 00h. 1fh=00, RW, reserved 20h 00h or 01h R/W TMDS output enable or disable. 00h: enabled 01h: disabled (<=10mV Voff) [7:1] Reserved 00h, RW (Not Applicable for PI- 3WVR31212A) 00h: enabled 01h: disabled (<=10mV Voff) [7:1] Reserved 21h 00h or 01h R/W Enables/disables the CEC Isolation Switch. 00h: enabled 01h: disabled [7:1] Reserved 00h, RW (Not Applicable for PI- 3WVR31212A) 00h: enabled 01h: disabled [7:1] Reserved 22h UD R/W I2C speed control status bit map. 01h: 1Kbps 02h: 5Kbps 04h: 10Kbps 08h: 100Kbps 10h, 20h, 40h and 80h are reserved 08h for 100Khz. (Not Applicable for PI- 3WVR31212A) For the function specified as: 01h: 1Kbps 02h: 5Kbps 04h: 10Kbps 08h: 100Kbps 10h, 20h, 40h and 80h are reserved 23h-ffh 00h R/W Reserved data Address from 23h to ffh: 1. DP source reads data address 23h thru ffh, ID register returns 00h. 2. DP source writes data AAh to data address 23h thru ffh, ID register responds ACK or returns 00h. 23h-ffh=00h, RW, reserved. Notes: 1. DP++ source accesses ID at device address 80h/81h with data offset from 00h-ffh. 2. UD: user dependent. 3. RO: read only. 4. OUI: IEEE Organizationally Unique Identifier. 15-0163

DP/HDMI 1:2 De-multiplexer switches www.pericom.com 12/15/15 All trademarks are property of their respective owners. ID Access Sequence Specified in DP Interoperability V1.1A It is suggested that the Source-side cable adaptor have a voltage-level shifter to convert the 5-V HPD signal from a DVI/HDMI Sink DDC Buffer ID of a Source-side HDMI Cable Adaptor Offset 0 1 2 3 4 5 6 7 8 9 Ah Bh Ch Dh Eh Fh Data 44h 50h 2Dh 48h 44h 4Dh 49h 20h 41h 44h 41h 50h 54h 4Fh 52h 04h Table below shows the I2C transaction sequence for a Source Device to read the DDC Buffer ID of the Source-side HDMI cable adap- tor. I2C write for setting the address offset is optional for a Dual-mode Source Device. The HDMI cable adaptor must acknowledge it when it receives this write operation. The DVI cable adaptor must NACK the I2C transaction to Device Address 80h/81h. DDC Buffer ID Access Sequence Phase I2C Transaction Transmitting Bit Bit Bit Bit Bit Bit Bit

1 R/W#

1 Start Master Optional -

2 Write command Master 1 0 0 0 0 0 0 0 Optional -

3 Acknowledge Slave - Mandatory

4 Word address

offset Master Word address offset data byte Optional -

5 Acknowledge Slave - Mandatory

6 Stop Master Optional -

7 Start Master Mandatory -

8 Read command Master 1 0 0 0 0 0 0 1 Mandatory -

9 Acknowledge Slave - Mandatory

10 Read data Slave Data byte at Offset 0 - Mandatory

11 Acknowledge Master Mandatory

12 Read data Slave Data byte at Offset 1 - Mandatory

13 - ... - ...

40 Read data Slave Data byte at Offset 15 - Mandatory

41 Not acknowlegde Master Mandatory -

42 Stop Master Mandatory -

Note: if the Slave does not acknowledge during the above transaction sequence, the entire sequence should be retried by the source. 15-0163

DP/HDMI 1:2 De-multiplexer switches www.pericom.com 12/15/15 All trademarks are property of their respective owners. Note: For latest package info, please check: http://www.pericom.com/products/packaging/mechanicals.php 14-0044

Ordering Information

Ordering Code Package Code Package Description PI3WVR31212AZLE ZL 60-Pin, (TQFN) 5X9mm PI3WVR31212AZLEX ZL 60-Pin, (TQFN) 5X9mm, Tape & Reel Notes:

• Thermal characteristics can be found on the company web site at www.pericom.com/packaging/
• "E" denotes Pb-free and Green
• Adding an "X" at the end of the ordering code denotes tape and reel packaging Packaging Mechanical: ZL60 15-0163