PI3WVR12612

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Document overview

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Technical content

Features

Î Î4-lane, 1:2 mux/demux that will support RBR, HBR1, or HBR2 Î ÎData rate: 3.4 Gbps to 6.0 Gbps for high data channels Î Î1-channel 1:2 mux/demux for HPD signal Î ÎDifferential switch matrix for DP AUX and HDMI DDC Î Îsupports 720 Mbps high-speed DP AUX Î Î-2.0 dB Insertion Loss for Dx channels @ 3 GHz Î Î-3 dB Bandwidth for Dx channels: 4.1 GHz Î ÎReturn loss for Dx channels @ 3 GHz: -12 dB Î ÎLow Crosstalk for high speed channels: -25 dB@ 6 Gbps Î ÎLow Off Isolation for high speed channels: -24dB@ 6 Gbps Î ÎLow channel-to-channel skew, 35ps max Î ÎLow Bit-to-Bit Skew, 5ps typ (between '+' and '-' bits) Î ÎVDD Operating Range: 3.3V +/-10% Î ÎESD Tolerance: 2kV HBM Î ÎPackaging (Pb-free & Green): -50-ball TFBGA (NEE) -52-pin TQFN (ZL52)

Description

Pericom Semiconductor’s PI3WVR12612 is a multi-standard video switch with wide voltage range capability. It supports DisplayPort 1.2, HDMI 2.0, and emerging and proprietary standards. PI3WVR12612 can pass high-speed signals up to 1.2 V peak- to-peak differential with a common-mode voltage from 0 to 3.4V. The wide voltage range allows DC-coupled multi-standard operation. Eliminating AC coupling capacitors saves board space and improves signal integrity for dense PCB designs. The high speed channels can also pass 0V-3.3V CMOS signals up to 1MHz. In addition to four high-speed lanes, PI3WVR12612 also switch - es AUX, DDC, and HPD signals. Application Routing of DisplayPort and HDMI signals with low signal at- tenuation between source and sink. Block Diagram PI3WVR12612 HDMI 2.0, DisplayPort 1.2 Video Switch Logic Control D0+AD0+ D0-AD0- D1+AD1+ D1-AD1- D2+AD2+ D0-AD2- D3+AD3+ D3-AD3- D0+B D0-B D1+B D1-B D2+B D2-B D3+B D3-B DDC_AUX_SEL GPU_SEL OE AUX+AAUX+ AUX+B SCL_A SCL_B SCL AUX-AAUX- AUX-B SDA_A SDA_B SDA HPD HPDA HPDB 15-0175

HDMI 2.0, DisplayPort 1.2 Video Switch www.pericom.com 12/03/15 All trademarks are property of their respective owners. Pin Assignment (50-Ball TFBGA, NEE) 1 2 3 4 5 6 7 8 9 D0- VDD D0+ GND D1+ D2+ D3+ GND AUX+ DDC_ AUX_ SEL D1- D2- D3- HPD HPD_A Vdd GNDHPD_B SCL_B SDA_B SCL_A SDA_A AUX+A AUX-A AUX+B GND AUX-B AUX- GPU _SEL D3-A D1-B D2-BD2+B D3-B GND GND D1+B D3+B D3+A D0-BD0+B D0-A D0+A D1-A D1+A D2-A D2+A OE A B C D E F G H J GPU_SEL SCL SDA Control Switch Function OE GPU_ SEL DDC_ AUX_ SEL D0- D3 AUX HPD DDC High Low Low A AUX A HPD A Hi-Z High High Low B AUX B HPD B Hi-Z High Low High A DDC A HPD A Hi-Z High High High B DDC B HPD B Hi-Z High Low Medium A AUX A HPD A DDC A High High Medium B AUX B HPD B DDC B Low x x Hi-Z Hi-Z Hi-Z Hi-Z Truth Table Î ÎMedium level = 1/2 VDD = 1.65V 52 51 50 49 22 23 24 25 26 OE D2-A D2+A D3-A D3+A V DD D0-B D0+B D1-B D1+B GND D2-B D2+B D3-B D3+B SDA_A SCL_A GND AUX-A AUX+A GND V DD GND GPU_SEL D0- D0+ DDC_AUX_SEL D1- D1+ D2- D2+ D3- D3+ GND VDD AUX- AUX+ HPD_B HPD_A HPD SCL SDA SDA_B SCL_B AUX-B AUX+B VDD D0-A D0+A D1-A D1+A GND Pin Assignment (52-Pin TQFN, ZL52) 15-0175

HDMI 2.0, DisplayPort 1.2 Video Switch www.pericom.com 12/03/15 All trademarks are property of their respective owners. (Continued) pin# pin Name Signal Type Description A1 GPU_SEL I switch logic control B1 D0- I/O negative differential signal 0 for COM port B2 D0+ I/O positive differential signal 0 for COM port D1 D1- I/O negative differential signal 1 for COM port D2 D1+ I/O positive differential signal 1 for COM port E1 D2- I/O negative differential signal 2 for COM port E2 D2+ I/O positive differential signal 2 for COM port F1 D3- I/O negative differential signal 3 for COM port F2 D3+ I/O positive differential signal 3 for COM port B3 GND Ground Ground H1 AUX- I/O negative differential signal for AUX COM port H2 AUX+ I/O posititve differential signal for AUX COM port J1 HPD I/O HPD for COM port J2 HPD_A I/O HPD for port A H3 HPD_B I/O HPD for port B C8 GND Ground Ground J4 VDD Pwr 3.3V +/-10% power supply G2 GND Ground Ground H6 AUX+B I/O positive differential signal for AUX, port B J6 AUX-B I/O negative differential signal for AUX, port B H9 AUX+A I/O positive differential signal for AUX, port A J9 AUX-A I/O negative differential signal for AUX, port A G8 GND Ground Ground F8 D3+B I/O positive differential signal 3 for portB F9 D3-B I/O negative differential signal 3 for portB E8 D2+B I/O positive differential signal 2 for portB E9 D2-B I/O negative differential signal 2 for portB D8 D1+B I/O positive differential signal 1 for portB D9 D1-B I/O negative differential signal 1 for portB B8 D0+B I/O positive differential signal 0 for portB B9 D0-B I/O negative differential signal 0 for portB Pin Description 15-0175

HDMI 2.0, DisplayPort 1.2 Video Switch www.pericom.com 12/03/15 All trademarks are property of their respective owners. pin# pin Name Signal Type Description A8 D3+A I/O positive differential signal 3 for port A A9 D3-A I/O negative differential signal 3 for port A H4 GND Ground B6 D2+A I/O positive differential signal 2 for port A A6 D2-A I/O negative differential signal 2 for port A B5 D1+A I/O positive differential signal 1 for port A A5 D1-A I/O negative differential signal 1 for port A B4 D0+A I/O positive differential signal 0 for port A A4 D0-A I/O negative differential signal 0 for port A A2 VDD Pwr Power C2 DDC_ AUX_SEL I switch logic control H5 SCL_B I/O DDC_clock channel for port B H7 GND Ground H8 SCL_A I/O DDC_clock channel for port A J5 SDA_B I/O DDC_data channel for port B J8 SDA_A I/O DDC_data channel for port A J3 SCL I/O DDC_clock channel for COM port J7 SDA I/O DDC_data channel for COM port B7 OE I Output enable. if OE is high, IC is enabled. If OE is low, then IC is power down and all I/Os are hi-z 15-0175

HDMI 2.0, DisplayPort 1.2 Video Switch www.pericom.com 12/03/15 All trademarks are property of their respective owners. DC Input Voltage HPD_x, SDA_x, SCL_x DC Output Current Power Dissipation Note: Stresses greater than those listed under MAXI - MUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating co ndi- tions for extended periods may affect reliability. Maximum Ratings (Above which useful life may be impaired. For user guidelines, not tested.) 3.3V ±10%) Parameter Description Test Conditions(1) Min Ty p(2) Max Units VIH Input HIGH Voltage (OE, GPU_SEL) Guaranteed HIGH level 1.5 V VIL Input LOW Voltage (OE, GPU_SEL) Guaranteed LOW level 0.75 VIH Input HIGH Voltage (DDC_AUX_SEL) Guaranteed HIGH level 2.65 VDD VIM Input Mid-Level Voltage (DDC_AUX_ SEL) Guaranteed MID level VDD/2- 300mV VDD/2 VDD/2+ 300mV VIL Input LOW Voltage (DDC_AUX_SEL) Guaranteed LOW level -0.5 0.6 VIK Clamp Diode Voltage (HS Channel) V DD = Max., IIN = –18mA –1.6V –1.8 VIK Clamp Diode Voltage (Aux, Cntrl ) V DD = Max., IIN = –18mA –0.7 –1.5 IIH Input HIGH Current (All Control Pins) V DD = Max., VIN = VDD ±5 µAIIL Input LOW Current (All Control Pins) V DD = Max., VIN = GND ±5 IOFF_SB I/O leakage when part is off for sideband signals only (DDC, AUX, HPD) V DD = 0V, VINPUT = 0V to 3.6V 20 RON_HS On resistance between input to output for high speed signals V INPUT,cm = 0V to 3.4V, VINPUT,diff < 1.2Vp-p,diff, VDD = 3.0V, IINPUT = 20mA

11 Ohm

RON_AUX On resistance between input to output for side-band signals (AUX) V DD = 3.0V, Vinput = 0 to 3.3V, IINPUT = 20mA 7 Ohm RON_DDC On resistance between input to output for DDC channel V DD = 3.0V, Vinput = 0V, IINPUT = 20mA 12 Ohm RON_HPD On resistance between input to output for HPD channel V DD = 3.0V, Vinput = 0 to 3.0V, IINPUT = 20mA 7 Ohm VAUX_SS Signal Swing Tolerance in Aux path V DD = 3.0V –0.5 5.5 V VHPD_I Input voltage on HPD path 5.5 V VHPD_O Output voltage tolerance on HPD path HPD input from 3.3V to 5.25V 3.3 3.6 V VSDA_X Input Voltage on SDA path 5 V VPASS (SDA_X) Switch output voltage tolerance input Vin = 5.25V, Ii = 100uA, VDD = 3.3V 1.8 2.2 2.5 V VSCL_X Input Voltage on SCL path 5 V VPASS (SCL_X) Switch output voltage tolerance input Vin = 5.25V, Ii = 100uA, VDD = 3.3V 1.8 2.2 2.5 V 15-0175

HDMI 2.0, DisplayPort 1.2 Video Switch www.pericom.com 12/03/15 All trademarks are property of their respective owners. Dynamic Electrical Characteristics over Operating Range (TA = -40º to +105ºC, VDD = 3.3V ±10%) Parameter Description Test Conditions1 Min Ty p2 MAX Units XTALK Crosstalk on High Speed Chan- nels See Fig. 1 for Measure- ment Setup f= 3.0 GHz -25 -22 f= 2.7 GHz -28 -25 dB f = 1.35 GHz -32 -28 O IRR OFF Isolation on High Speed Channels See Fig. 2 for Measure- ment Setup, f= 3.0 GHz -24 -20 f= 2.7 GHz -25 -22 f = 1.35 GHz -30 -27 I LOSS Differential Insertion Loss on High Speed Channels @6.0Gbps (see figure 4) -2.3 -2.0 dB @5.4Gbps (see figure 3) -2.0 -1.8 R loss Differential Return Loss on high speed channels @3.0GHz (6.0Gbps) -12 -11 dB @ 2.7GHz (5.4Gbps) -14 -12.5 BW_Dx± Bandwidth -3dB for Main high speed path (Dx±) See figure 3 3.7 4.1 GHz BW_AUX/ HPD -3dB BW for AUX, DDC, and HPD signals See figure 3 1.35 1.5 GHz 1. F or Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type. T ypical values are at V DD = 3.3V, TA = 25°C ambient and maximum loading. Switching Characteristics (TA= -40º to +105ºC, VDD = 3.3V±10%) Parameter Description Min. Ty p. Max. Units Tpd Propagation delay (input pin to output pin) on Dx± channels 80 ps tb-b Bit-to-bit skew within the same differential pair of Dx± channels 5 7 ps tch-ch Channel-to-channel skew of Dx± channels 35 ps Tsw a-b time it takes to switch from port A to port B 0.1 us Tsw b-a time it takes to switch from port B to port A 0.1 us Tstartup Vdd valid to channel enable 10 us Twa keup Enabling output by changing OE from low to High 10 us Power Supply Characteristics (TA = –40°C to +105°C) Parameter Description Test Conditions(1) Min Ty p(2) Max Units IDD Power Supply Current VDD = 3.3V, VIN = GND or VDD 1 3 mA IDD,Off Power Supply Current, Disabled VDD = 3.3V, VIN = GND or VDD, VOE < VIL 1 50 µA 1. F or Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type. T ypical values are at V DD = 3.3V, TA = 25°C ambient and maximum loading. 15-0175

HDMI 2.0, DisplayPort 1.2 Video Switch www.pericom.com 12/03/15 All trademarks are property of their respective owners. Fig 1. Crosstalk Setup Fig 2. Off-isolation setup BALANCED PORT1 DUT BALANCED PORT2 BALANCED PORT1 BALANCED PORT2 DUT BALANCED PORT1 BALANCED PORT2 DUT Fig 3. Differential Insertion Loss Test Circuit for Dynamic Electrical Characteristics 15-0175

HDMI 2.0, DisplayPort 1.2 Video Switch www.pericom.com 12/03/15 All trademarks are property of their respective owners. Fig 4. Crosstalk Fig 5. Off Isolation 15-0175

HDMI 2.0, DisplayPort 1.2 Video Switch www.pericom.com 12/03/15 All trademarks are property of their respective owners. Fig 6. Insertion Loss Fig 7. TDR Channel D0, VDD= 3.0V , 25C 15-0175

HDMI 2.0, DisplayPort 1.2 Video Switch www.pericom.com 12/03/15 All trademarks are property of their respective owners. Fig 8. Differential output Eye at Input signal is a 27-1 PRBS, Vdd=3.0V , 25C, Input swing is 800mV differential Fig 9. Differential output Eye at Input signal is a 27-1 PRBS, Vdd=3.0V , 25C, Input swing is 800mV differential 15-0175

HDMI 2.0, DisplayPort 1.2 Video Switch www.pericom.com 12/03/15 All trademarks are property of their respective owners. 4pF CL VDD 200-ohm Pulse Generator D.U.T SEL PA PB COM0V/3V 3V/0V Test Circuit for Electrical Characteristics(1-5) Notes: 1. CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to Z OUT of the Pulse Generator 3. A ll input impulses are supplied by generators having the following characteristics: PRR ≤ MHz, Z O = 50Ω, tR ≤ 2.5ns, t F ≤ 2.5ns. Th e outputs are measured one at a time with one transition per measurement. Switching Waveforms Voltage Waveforms Enable and Disable Times Test Condition Output 1 Test Conditon Output 2 Test Conditon PA = Low PA = High PB = High PB = Low Tsw a-b 50% 50% VDD VOH VOL Tsw b-a Output 1 Output 2 VOL VOH SEL 50% 50% 15-0175

HDMI 2.0, DisplayPort 1.2 Video Switch www.pericom.com 12/03/15 All trademarks are property of their respective owners. DATE: 04/04/13 DESCRIPTION: 50-Ball, Thin Fine Pitch Ball Grid Array, (TFBGA) PACKAGE CODE: NE50 DOCUMENT CONTROL #: PD - 2158 REVISION: - Notes: 1. Controlling dimensions in millimeters 2. Ref: JEDEC MO-195C 13-0150 Packaging Mechanical: 50-Ball TFBGA (NE50) 15-0175

HDMI 2.0, DisplayPort 1.2 Video Switch www.pericom.com 12/03/15 All trademarks are property of their respective owners. Note: For latest package info, please check: http://www.pericom.com/products/packaging/mechanicals.php

Ordering Information

Ordering Code Package Code Package Description PI3WVR12612NEE NE 50-Pin, Thin Fine Pitch Ball Grid Array (TFBGA) PI3WVR12612NEEX NE 50-Pin, Thin Fine Pitch Ball Grid Array (TFBGA), Tape & Reel PI3WVR12612ZLE ZL 52-Pin, 3.5 x 9.0 mm (TQFN) PI3WVR12612ZLEX ZL 52-Pin, 3.5 x 9.0 mm (TQFN), Tape & Reel Notes:

• Thermal characteristics can be found on the company web site at www.pericom.com/packaging/
• "E" denotes Pb-free and Green
• Adding an "X" at the end of the ordering code denotes tape and reel packaging 14-0122 Packaging Mechanical: 52-Pin TQFN (ZL52) Pericom Semiconductor Corporation • 1-800-435-2336 15-0175