PI3TB212

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Document overview

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Technical content

Features

ÎÎ Supports 5.4Gbps for DisplayPort 1.2 and 10.3Gbps for Thunderbolt Electrical Standard ÎÎ Supports DP and DP++ Configuration ÎÎ Supports AUX and DDC MUX ÎÎ VDD Operating Range for normal operation: 3.3V±10% ÎÎ Extended operation down to 2.5V min on the LSTx/LSRx to TBC-9/TBC-11 channels (performance not guaranteed, but all buffers will still operate) ÎÎ ESD protection on all pins ÎÎ 1.0kV HBM per JESD22 standard ÎÎ P ackaging (Pb-free & Green): à 3.0 mm x 3.0 mm, 24-contact TQFN Application ÎÎ Thunderbolt over mini-DP connector enablement

Description

Pericom Semiconductor's PI3TB212 is a high-speed multi - plexer/demultiplexer switch. PI3TB212 can switch signals up to 10.3125Gbps for DisplayPort and Thunderbolt™(TB) ap plications. The device supports 5.4Gbps for DisplayPort and 10.3125Gbps for Thunderbolt. PI3TB212 is a major advance over first-generation Thunderbolt solutions. PI3TB212 integrates the 10.3125 Gbps Thunderbolt path. This eliminates external PIN diode switches, thereby reducing board space, reducing cost, and improving link perfor mance. PI3TB212 achieves excellent signal integrity at 10.3125 Gbps as evidenced by measured results. PI3TB212 10.3Gbps Thunderbolt™ and DisplayPort™ Switch VDD AUX- AUX+ DDC_SDA DDC_SCL TB_Rx_1(n) TB_Rx_1(p) GND ML1(n) ML1(p) HPD_Out 10G_EN TBC-2 CA_DET_Out LSTx LSRx DP_EN# TBC-18 TBC-16 GND TBC-11 TBC-9 TBC-4 6 7 8 9 10 11 12 181920 2122 2324 GND GND Pin Configuration (Top View) Block Diagram Controller Chip CA_DET_Out DDC_SCL DDC_SDA AUX+ AUX- TB Rx_1(p) TB Rx_1(n) ML1(p) ML1(n) LSTx LSRx DP_EN# 10G_EN HPD_Out VDD TBC-16 TBC-18 TBC-9 TBC-11 PU/PD Enables HPD_SINK TBC-4 TBC-2 VDD 13-0026

All trademarks are property of their respective owners. PI3TB212 10.3Gbps Thunderbolt™ and DisplayPort™ Switch Pin Description Pin # Pin Name Ty pe Description 17 TBC-2 I Connector Side Hot Plug Detect Input. Connect to mini-DP connector pin2 ML1(p) ML1(n) I/O Controller Side Channel 1, DisplayPort Positive Signal (external AC coupling is required) Controller Side Channel 1, DisplayPort Negative Signal (external AC coupling is required) TBC-16 TBC-18 I/O Sink Side TB Rx1(p) or AUX+ Signal or DDC_SCL. Connect to mini-DP connector pin 16. Sink Side TB Rx1(n) or AUX- Signal or DDC_SDA. Connect to mini-DP connector pin 18. TBC-9 TBC-11 I/O Sink Side DP Main Link + Signal or LSTX. Connect to mini-DP connector pin 9. Sink Side DP Main Link - Signal or LSRX. Connect to mini-DP connector pin 11 AUX+ AUX- I/O Controller Side AUX Positive Signal Controller Side AUX Negative Signal TB Rx_1(p) TB Rx_1(n) I/O Controller Side 10Gbps Positive Signal (external AC coupling is required) Controller Side 10Gbps Negative Signal (external AC coupling is required) DDC_SCL DDC_SDA I/O Controller Side DDC Clock Controller Side DDC Data TBC-4 I Connector Side Cable Detect for DP++ Dongle. Connect to mini-DP connector pin 4. HPD_Out O Controller Side Buffered Hot Plug Detect Output LSTx LSRx I/O O Controller Side un-buffered UART TX Signal. Integrated 9K W pull-up Controller Side buffered UART RX Signal. 1M W pull-down present at buffer input I Control signal. See truth table for detailed functionality CA_DET_Out O Cable detect buffered output coming from TBC-4 (pin 18) 6 DP_EN# I DisplayPort path enable. See truth table for detailed functionality. 15 10G_EN I 10G path enable. See truth table for detailed functionality. VDD Power 3.3V+/-10% power supply voltage Center Pad, 9, 21 GND Ground Ground. both pins and center pad must all be connected to GND plane. 13-0026

All trademarks are property of their respective owners. PI3TB212 10.3Gbps Thunderbolt™ and DisplayPort™ Switch Description of Operation Truth Table Device States Control Pins Device and PU/PD Configurations S0 10G_EN DP_EN# TBC-4 2:1 Mux 3:1 Mux LSRx, HPD_Out, & CA_DET_Out buffers R1, R2 status Thunderbolt 10G mode 1 (System Active) 0 (System Sleep) X X LSTx & LSRx LSTx & LSRx TB Rx_1 Hi-z All buffers on R1 = R2 = OFF R1 = R2 = OFF DisplayPort Mode 1 (System Active) 0 (System Sleep) DP ML1 (p, n) Hi-Z AUX Hi-z All buffers on R1 = R2 = ON R1 = R2 = ON TMDS Mode 1 (System Active) 0 (System Sleep) DP ML1 (p, n) Hi-Z DDC Hi-z All buffers on R1 = R2 = ON R1 = R2 = ON Detect Mode X - don't care X LSTx & LSRx Hi-z All buffers on R1 = R2 = ON Chip Disable mode X - don't care x hi-z hi-z All buffers on R1 = ON, R2 = ON Power off (VDD = 0V) X - don't care x x x hi-z hi-z All buffers oFF R1 = OFF, R2 = ON ThunderBolt Connector Pins Controller Pin Names TBC-16 DDC_SCL or AUX(p) or TB RX_1 (p) TBC-18 DDC_SDA or AUX(n) or TB Rx_1 (n) TBC-9 ML1 (p) or LSTx TBC-11 ML1 (n) or LSRx TBC-4 CA_DET_Out TBC-2 HPD_Out 13-0026

All trademarks are property of their respective owners. PI3TB212 10.3125Gbps Thunderbolt and DisplayPort Switch 03/12/13 Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Expo sure to absolute maximum rating conditions for extended periods may affect reliability. Maximum Ratings (Above which useful life may be impaired. For user guidelines, not tested.) Recommended Operating Conditions Symbol Parameter Conditions Min Typ Max Units VDD 3.3V Power Supply 3.0 3.3 3.6 V IDD current consumption in normal op - peration Control pins = GND or VDD, LSTx = VDD 300 780 uA IDDQ (Sys - tem off) Current consumption when S0 = 0 S0 = 0, TBC-2 and TBC-4 = GND or VDD, LSTx = VDD, all I/Os are floating 100 300 IDD_detect Current consumption during detect S0 = VDD, 10G_EN = 0, DP_EN# = VDD, LSTx = VDD, all I/Os are floating 120 300 PDD Total Power from VDD 3.3V supply Control pins = GND or VDD, LSTx = VDD 1 2.8 mW PDDQ (Sys - tem off) Power consumption when S0 = 0 S0 = 0, TBC-2 and TBC-4 = GND or VDD, LSTx = VDD 330 1080 uW PDD_Detect Power consumption during detect S0 = VDD, 10G_EN = 0, DP_EN# = VDD, LSTx = VDD 400 1080 uW TCASE Case operating temperature range 0 105 C

Electrical Characteristics

Parameters Description Test Conditions(1) Min Ty p(1) Max V IH Input HIGH Voltage for S0, DP_EN#, 10G_EN, TBC-4, TBC-2, TBC-11 VDD = 3.3V 1.8 V V IL Input LOW Voltage for S0, DP_EN#, 10G_EN, TBC-4, TBC-2, TBC-11 VDD = 3.3V 0.8 VIK Clamp Diode Voltage VDD= Max., IIN = –18mA –0.7 –1.2 IIH Input HIGH Current for S0, DP_ EN#, 10G_EN, TBC-4. TBC-2 VDD = Max., VIN = VDD -1 1 µA I IL Input LOW Current for S0, DP_EN#, 10G_EN, TBC-4, TBC-2 VDD = Max., VIN = 0V -1 1 I OFF (TBC pins) leakage from TBC-16 VDD = 0V, 1.5V present on TBC-16 TB Rx_1 (p/n) is floating -60 +60 µA leakage from TBC-18 VDD = 0V, 1.5V present on TBC-18 TB Rx_1 (p/n) is floating -20 +20 leakage from TBC-9, TBC-11, TBC- 4, & TBC-2 VDD = 0V, 3.3V present on TBC pins ML1(p/n) is floating -20 +20 13-0026

All trademarks are property of their respective owners. PI3TB212 10.3125Gbps Thunderbolt and DisplayPort Switch 03/12/13 Parameters Description Test Conditions Min. Ty p. Max. Units RON AUX/LSTx AUX & LSTx On Resistance VDD = 3.3V Vinput = 3.3V, Iinput = -40mA 9 15 Ohms RON TB TB On Resistance VDD = 3.3V Vinput = 0V, Iinput = -40mA 5 8 RON DP DP On Resistance VDD = 3.3V Vinput = 0V, Iinput = -40mA 5 8 RON DDC DDC On Resistance VDD = 3.3V Vinput = 3.3V, Iinput = -40mA 5 25 RON Table Parameters Description Test Conditions(1) Min Ty p(1) Max Units ILeakage Leakage on TB-16/TB-18 Thunderbolt 10G Mode VDD = 3.6V. TB path on. Vin = 1.0V, TBRx_1 (p/n) is floating µA I OZL I/O leakage for DDC/AUX VDD = 3.6V. Vin = 0V I/O leakage for TB Rx1(p/n) VDD = 3.6V. Vin = 0V; TBC16, 18 = 0.2V I/O leakage for ML1 VDD = 3.6V. Vin = 0V; TBC9, 11 = 0.5V I/O leakage for LSTx VDD = 3.6V. Vin = 0V -600 -400 -300 I/O leakage for TBC9 and 11 VDD = 3.6V, Vin = 0V, ML1 (p/n) is float ing I/O leakage for TBC16 and 18 VDD = 3.6V, Vin = 0V, S0=low, 10G_EN = high, DP_EN# = high, TBRx_1 (p/n) is floating, Thunderbolt Mode I OZH I/O leakage for DDC/AUX VDD = 3.6V. Vin = VDD I/O leakage for TB Rx1(p/n) VDD = 3.6V. Vin = 0.5V I/O leakage for ML1 VDD = 3.6V. Vin = 2.6V I/O leakage for LSTx VDD = 3.6V. Vin = VDD I/O leakage for TBC9 and 11 VDD = 3.6V, Vin = VDD, ML1(p/n) is floating I/O leakage for TBC16 and 18 VDD = 3.6V, Vin = VDD, S0=low, 10G_ EN = high, DP_EN# = high, TBRx_1 (p/n) is floating, Thunderbolt mode 150 13-0026

All trademarks are property of their respective owners. PI3TB212 10.3125Gbps Thunderbolt and DisplayPort Switch 03/12/13 Parameters Description Test Conditions Min. Ty p. Max. Units VIH Input high for TBC-2, TBC-4 and TBC-11 VDD = 3.6V 1.8 V VIL Input Low for TBC-2, TBC-4 and TBC-11 VDD = 3.6V 0.8 VOH Output high for HPD_Out, CA_DET_Out, and LSRx VDD = 3.3V+/-10%, Ioh = -2mA 2.4 VDD VOL Output Low for HPD_Out, CA_DET_Out and LSRx VDD = 3.6V, Iol = 2mA 0.8 Buffers (HPD_Out, CA_DET_Out, TBC-2, TBC-4 and LSRx) Off-Isolation3 Off-isolation for DP path f = 810MHz f = 1.35GHz f = 2.7GHz -27 -22 -16 dB Off-isolatoin for TB path f = 4.0GHz f = 5.0GHz -16 -15 dB Notes: 1. Guaranteed by design. Typical values are at VDD = 3.3V , TA = 25°C ambient and maximum loading. 2. Refer to figure 1 for test setup 3. Refer to figure 3 for test setup Dynamic Electrical Characteristics Parameter Description Test Conditions Min. Ty p.(1) Max. Units DDIL (2) (TB R X _1) Insertion Loss on TB Rx_1 (p, n) to TBC- 16 and TBC-18 path (VIN = -10dBm, DC = 0V) f=4.0GHz f=5.0GHz f=8.0GHz -1.2 -1.5 -3.0 dB DDIL (ML1) Insertion Loss on ML1 (p, n) to TBC-9 and TBC-11 path (VIN = -10dBm, DC = 0V) f=810MHz (RBR) f=1.35GHz (HBR1) f=2.7GHz (HBR2) -0.5 -0.7 -1.1 dB DDRL (2) (TB R x _1) Differential Return Loss on 10G thunderbolt path f= 4.0GHz f= 5.0GHz f= 8.0GHz -24 -16 dB DDRL (ML1) Differential Return Loss on DP path f= 1.35GHz f= 2.7GHz f= 6.0GHz -31 -27 -17 dB 13-0026

All trademarks are property of their respective owners. PI3TB212 10.3125Gbps Thunderbolt and DisplayPort Switch 03/12/13 Pull-up/Pull-downs Parameter Description Test Conditions Min. Ty p.(1) Max. Units R2 Pull-down value on AUX+ path S0 = 10G_EN = DP_EN#=TBC-4 = 0V VDD=3.3V, TBC-16 = 3.3V VDD = 0V, TBC-16 = 3.3V 105 105 Kohm Pull-up value on AUX- path S0 = 10G_EN = DP_EN#=TBC-4 = 0V VDD = 3.3V, TBC-18 = 0V 105 Kohm Pull-down value on LSRx path S0 = 10G_EN = 0V; DP_EN#=TBC-11=3.3V; VDD = 3.3V 1.5 Mohm Pull-up value on LSTx path S0 = 10G_EN = 0V; DP_EN# = VDD; LSTx=0V VDD = 3.3V 8.8 10.5 Kohm Notes: 1. T ypical values are at V DD = 3.3V , TA = 25°C ambient and maximum loading. 2. See figure 2 for test setup Parameter Description Test Conditions Min. Ty p Max. Units Vp_TBT TB Rx_1(p) and TB Rx_1(n) path (2) VDD = 3.3V, Ipass = 10mA 1.0 1.3 V Vp_AUX/DDC AUX+, AUX-, DDC_SCL, & DDC_SDA path (2) VDD = 3.3V, Ipass = 10mA 3.6 4.2 V Vp_ML ML1(p) and ML1(n) path (2) VDD = 3.3V, Ipass = 10mA 2.2 2.5 V Vp_LSTx LSTx signal path (2) VDD = 3.3V, Ipass = 10mA 3.6 4.2 V Linear region for Analog switches (non-buffered paths) Timing Parameter Description Test Conditions Min. Ty p.(1) Max. Units Tsw Switching time between paths VDD = 3.0V 2 us Tstartup VDD valid to channel enable VDD valid = 2.7V VDD ramp is from 0V to 3.3V us Twa keup From sleep mode to on mode (tog gling S0) VDD = 3.0V us T b-b Bit-to-bit skew within the same differential pair VDD = 3.0V (between pin 22 & 23) ps (between pin 19 & 20) 13-0026

All trademarks are property of their respective owners. PI3TB212 10.3125Gbps Thunderbolt and DisplayPort Switch 03/12/13 BALANCED PORT1 BALANCED PORT2 DUT Fig 3: Diff. Off Isolation Test Circuit BALANCED PORT1 BALANCED PORT2 DUT Fig 1: Diff. Insertion Loss and Return Test Circuit VDD Fig 2: Linear Region Test Setup Test Circuit for Electrical Characteristics(1-5) Notes: 1. CL = Load capacitance: includes jig and probe capacitance. 2. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator 3. Output 1 is for an output with internal conditions such that the output is low except when disabled by the output control. output 2 is for an output with internal conditions such that the output is high except when disabled by the output control. 4. All input impulses are supplied by generators having the following characteristics: PRR ≤ MHz, ZO = 50Ω, tR ≤ 2.5ns, tF ≤ 2.5ns. 5. The outputs are measured one at a time with one transition per measurement. 4pF CL VDD COM Port 200-ohm Pulse Generator D.U.T Port2 Port1 xEN Switching Waveforms Voltage Waveforms SwitchingTimes Tsw 50% 50% VDD VOH VOL Tsw Tsw Tsw Output 1 Output 2 VOL VOH xEN 50% 50% Test Condition: Output1: Port 1=Low, Port 2=High Output2: Port 1=High, Port 2=Low 13-0026

All trademarks are property of their respective owners. PI3TB212 10.3125Gbps Thunderbolt and DisplayPort Switch 03/12/13 Measured Insertion loss for 10Gbps Thunderbolt Path at VDD = 3.3V , TA = 25°C Measured Return loss for 10Gbps Thunderbolt Path at VDD = 3.3V , TA = 25°C 13-0026

All trademarks are property of their respective owners. PI3TB212 10.3125Gbps Thunderbolt and DisplayPort Switch 03/12/13 Measured Data Eye for 10.3125 Gbps Thunderbolt Path at VDD = 3.0V , TA = 25°C, PRBS2^7-1 Measured Data Eye for 5.4 Gbps Display Port Path at VDD = 3.0V , TA = 25°C, PRBS2^7-1 13-0026

All trademarks are property of their respective owners. PI3TB212 10.3Gbps Thunderbolt™ and DisplayPort™ Switch Packaging Mechanical: 24-Contact TQFN

Ordering Information

Ordering Number Package Code Package Description PI3TB212ZLE ZL Pb-free & Green 24-Contact TQFN

• Thermal characteristics can be found on the company web site at www.pericom.com/packaging/
• E = Pb-free and Green
• X suffix = Tape/Reel Pericom Semiconductor Corporation • 1-800-435-2336 Please check for the latest package information on the Pericom web site at www.pericom.com/packaging/ DATE: 05/07/12 DESCRIPTION: 24-contact, Very Thin Quad Flat No-Lead (TQFN) PACKAGE CODE: ZL24 DOCUMENT CONTROL #: PD-2109 REVISION: -- Notes: 1. All dimensions are in mm. 2. Coplanarity applies to the exposed thermal pad as well as the terminals 3. Refer JEDEC MO-220 12-0353 13-0026