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Technical content

Features

Î Î4 Differential Channel, 2:1 Mux/DeMux Î ÎPCI Express® 3.0 Performance, 8.0Gbps Î ÎPinout optimized for placement between two PCIe slots Î ÎBi-directional operation Î ÎLow Bit-to-Bit Skew, 10ps max Î ÎLow Crosstalk: -48dB @4GHz Î ÎHigh Off Isolation: -22dB @4GHz Î ÎLow Insertion Loss: -1.6dB @4GHz Î ÎReturn Loss: -15dB @4GHz Î ÎVDD Operating Range: +3.3V Î ÎESD Tolerance: 2kV HBM Î ÎLow channel-to-channel skew, 20ps max Î ÎPackaging (Pb-free & Green): à 4 2-contact, TQFN (ZH42)

Description

Pericom Semiconductor’s PI3PCIE3415 is an 8 to 4 differential channel multiplexer/demultiplexer switch. This solution can switch 2 full PCI Express® 3.0, lanes to one of two locations. Using a unique design technique, Pericom has been able to minimize the impedance of the switch such that the attenuation observed through the switch is negligible. The unique design technique also offers a layout targeted for PCI Express signals, which minimizes the channel to channel skew as well as channel to channel crosstalk as required by the PCI Express specifica- tion. Application XAUI, RXAUI signals with low signal attenuation. Block Diagram Pin Description (Top-Side View) Truth Table Function SEL xIy to xOay L xIy to xOby H SEL BI BI AI AI DI DI CI CI + BOa BOa AOa AOa + BOb BOb AOb AOb + DOa DOa COa COa + DOb DOb COb COb + 42 41 40 39 18 19 20 21 GND VDD GND VDD GND VDD GND VDD GND AI+ AI- AOb+ AOb- BI+ BI- BOb+ BOb- VDD CI+ CI- COb+ COb- DI+ DI- DOb+ DOb- AOa+ AOa- GND GND VDD BOa+ BOa- VDD SEL GND COa+ COa- VDD GND DOa+ DOa- GND PI3PCIE3415 3.3V , PCI Express® 3.0 2-Lane, 2:1 Mux/DeMux Switch 13-0098

www.pericom.com PS9107 06/20/13 All trademarks are property of their respective owners. PI3PCIE3415 3.3V , PCI Express® 3.0 2-Lane, 2:1 Mux/DeMux Switch Signal Descriptions Pin Number Pin Name Ty pe Description 1, 2 AI+, AI- Differential I/O Differential I/O pair from PCIE signal source. Signal is routed to the AOa+, AOa- pin respectively when SEL=0. Signal is routed to the AOb+, AOb- pin respectively when SEL = 1. 37, 36 AOa+, AOa- Differential I/O Differential analog pass-through I/O. Signal from AI+ and AI- is routed to AOa+ and AOa- respectively when SEL=0. 3, 4 AOb+, AOb- Differential I/O Differential analog pass-through I/O. Signal from AI+ and AI- is routed to AOb+ and AOb- respectively when SEL=1. 5, 6 BI+, BI- Differential I/O Differential I/O pair from PCIE signal source. Signal is routed to the BOa+, BOa- pin respectively when SEL=0. Signal is routed to the BOb+, BOb- pin respectively when SEL = 1. 33, 32 BOa+, BOa- Differential I/O Differential analog pass-through I/O. Signal from BI+ and BI- is routed to BOa+ and BOa- respectively when SEL=0. 7, 8 BOb+, BOb- Differential I/O Differential analog pass-through I/O. Signal from BI+ and BI- is routed to BOb+ and BOb- respectively when SEL=1. 10, 11 CI+, CI- Differential I/O Differential I/O pair from PCIE signal source. Signal is routed to the COa+, COa- pin respectively When SEL=0. Signal is routed to the COb+, COb- pin respectively when SEL = 1. 28, 27 COa+, COa- Differential I/O Differential analog pass-through I/O. Signal from CI+ and CI- is routed to COa+, COa- pin respectively when SEL = 0. 12, 13 COb+, COb- Differential I/O Differential analog pass-through I/O. Signal from CI+ and CI- is routed to COb+, COb- pin respectively when SEL = 1. 14, 15 DI+, DI- Differential I/O Differential I/O pair from PCIE signal source. Signal is routed to the DOa+, DOa- pin respectively When SEL=0. Signal is routed to the DOb+, DOb- pin respectively when SEL = 1. 24, 23 DOa+, DOa- Differential I/O Differential analog pass-through I/O. Signal from DI+ and DI- is routed to DOa+, DOa- pin respectively when SEL = 0. 16, 17 DOb+, DOb- Differential I/O Differential analog pass-through I/O. Signal from DI+ and DI- is routed to DOb+, DOb- pin respectively when SEL = 1. 35, 38, 40, 42 GND Ground input Ground 30 SEL 3.6V tolerant low-voltage single-ended input SEL controls the mux through a flow-through latch. 9, 19, 21, 26, 31, 34, 39, 41 VDD Power supply Power, 3.3V ±10% 13-0098

www.pericom.com PS9107 06/20/13 All trademarks are property of their respective owners. PI3PCIE3415 3.3V , PCI Express® 3.0 2-Lane, 2:1 Mux/DeMux Switch Symbol Parameter Conditions Min Ty p Max Units VDD 3.3V Power Supply 3.0 3.3 3.6 V IDD Total current from VDD 3.3V supply SEL = 0V or VDD 0 0.15 1 mA TCASE Case temperature range for operation within spec. -40 85 Celsius Electrical Characteristics Recommended Operating Conditions Supply V oltage to Ground Potential Channel DC Input V oltage DC Output Current Power Dissipation Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indi- cated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Maximum Ratings (Above which useful life may be impaired. For user guidelines, not tested.) Parameter Description Test Conditions Min Ty p(1) Max Units VIH-SEL Input high level, SEL input 2.0 3.6 V VIL-SEL Input Low Level, SEL input 0 0.8 V IIN_SEL Input Leakage Current, SEL input Measured with input at VIH-SEL max and VIL-SEL min –10 10 uA I IH Input High Current, xI, xO V DD = Max, VIN = 1.5V –10 10 uA IIL Input Low Current, xI, xO V DD = Max, VIN = 0V –10 10 uA IIH Input High Current, SEL V DD = Max, VIN = VDD –5 5 uA IIL Input Low Current, SEL V DD = Max, VIN = 0V –5 5 uA IOZH HighZ High Current xOa, xOb V DD = Max, VIN = 1.5V –10 10 uA IOZL HighZ Low Current xOa, xOb V DD = Max, VIN = 0V –10 10 uA Note: T ypical values are at V DD = 3.3V, Ta = 25°C ambient and maximum loading. 13-0098

www.pericom.com PS9107 06/20/13 All trademarks are property of their respective owners. PI3PCIE3415 3.3V , PCI Express® 3.0 2-Lane, 2:1 Mux/DeMux Switch Switching Characteristics Parameter Description Test Conditions Min. Ty p. Max. Units tPZH, tPZL Line Enable Time - SEL to xI+/-, xOy+/- See "Test Circuit for Electrical Characteristics" 0.5 15 25 ns tPHZ, tPLZ Line Disable Time - SEL to xI+/-, xOy+/- See "Test Circuit for Electrical Characteristics" 0.5 5 25 ns t b-b Bit-to-bit skew within the same differential pair See "Test Circuit for Electrical Characteristics" 4 10 ps tch-ch Channel-to-channel skew See "Test Circuit for Electrical Characteristics" 20 ps Dynamic Electrical Characteristics for xI+/-, xOy+/- Parameter Description Test Conditions Min. Ty p.(1) Max. Units DDIL Differential Insertion Loss f=50MHz -1.25GHz f=1.25GHz - 2.5GHz f=2.5GHz - 4GHz f=5.0GHz -0.8 -1.1 -1.6 -1.7 -1.0 -1.3 -1.9 -2.0 dB DDIL OFF Differential Off Isolation f= 0 to 4.0GHz -25.8 -20.6 -17.6 -15.4 -32.2 -25.8 -22.0 -19.3 DDRL Differential Return Loss f=50MHz - 1.25GHz f=1.25GHz - 2.5GHz f=2.5GHz - 4GHz f=5.0GHz -18.2 -16.8 -12 -22.7 -21.0 -15.0 -10.0 DDNEXT Near End Crosstalk f=50MHz -1.25GHz f=1.25GHz - 2.5GHz f=2.5GHz - 4GHz f=5.0GHz -44.8 -41.6 -38.4 -36 -56 -52 -48 -45 BW Bandwidth -3dB 8.7 GHz 13-0098

www.pericom.com PS9107 06/20/13 All trademarks are property of their respective owners. PI3PCIE3415 3.3V , PCI Express® 3.0 2-Lane, 2:1 Mux/DeMux Switch 5.0 Gbps RX signal eye with PI3PCIE34155.0 Gbps RX signal eye without PI3PCIE3415 8.0 Gbps RX signal eye with PI3PCIE34158.0 Gbps RX signal eye without PI3PCIE3415 13-0098

www.pericom.com PS9107 06/20/13 All trademarks are property of their respective owners. PI3PCIE3415 3.3V , PCI Express® 3.0 2-Lane, 2:1 Mux/DeMux Switch Differential Insertion Loss Differential Return Loss 13-0098

www.pericom.com PS9107 06/20/13 All trademarks are property of their respective owners. PI3PCIE3415 3.3V , PCI Express® 3.0 2-Lane, 2:1 Mux/DeMux Switch Differential Off Isolation Differential Crosstalk 13-0098

www.pericom.com PS9107 06/20/13 All trademarks are property of their respective owners. PI3PCIE3415 3.3V , PCI Express® 3.0 2-Lane, 2:1 Mux/DeMux Switch Switch Positions Test Switch tPLZ, tPZL 3.0V tPHZ, tPZH GND Switching Waveforms Voltage Waveforms Enable and Disable Times RT 4pF CL VDD VIN VOUT 200-ohm 200-ohm 3.0 V Pulse Generator D.U.T SEL Test Circuit for Electrical Characteristics (1-5) Notes: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to Z OUT of the Pulse Generator O utput 1 is for an output with internal conditions such that the output is low except when disabled by the output control. o utput 2 is for an output with internal conditions such that the output is high except when disabled by the output control. a l l input impulses are supplied by generators having the following characteristics: PRR ≤ MHz, Z O = 50Ω, tR ≤ 2.5ns, t F ≤ 2.5ns. Th e outputs are measured one at a time with one transition per measurement. tPLZ VDD/2 VDD/2 VDD VOH VOL 0.75V 0.75V tPHZ tPZL tPZH Output 1 Output 2 VOL VOH SEL VOL + 0.15V VOH – 0.15V *VOUT = Port 1 or Port 2 tpZH/HZ = COM Port is High tpLZ/ZL = COM Port is Low 13-0098

www.pericom.com PS9107 06/20/13 All trademarks are property of their respective owners. PI3PCIE3415 3.3V , PCI Express® 3.0 2-Lane, 2:1 Mux/DeMux Switch BALANCED PORT1 DUT BALANCED PORT2 BALANCED PORT1 BALANCED PORT2 DUT Differential Insertion Loss and Return Test Circuit Differential Off Isolation Test Circuit Differential Near End Xtalk Test Circuit BALANCED PORT1 BALANCED PORT2 DUT 13-0098

www.pericom.com PS9107 06/20/13 All trademarks are property of their respective owners. PI3PCIE3415 3.3V , PCI Express® 3.0 2-Lane, 2:1 Mux/DeMux Switch

Ordering Information

Ordering Code Package Code Package Description PI3PCIE3415ZHE ZH Pb-free & Green, 42-contact TQFN Notes: Th ermal characteristics can be found on the company web site at www.pericom.com/packaging/ E" denotes Pb-free and Green A dding an "X" at the end of the ordering code denotes tape and reel packaging DATE: 11/14/12 DESCRIPTION: 42-contact Thin Fine Pitch Quad Flat No-Lead (TQFN) PACKAGE CODE: ZH42 DOCUMENT CONTROL #: PD-2035 REVISION:D Notes: 1. All dimensions are in millimeters. Angles in degrees. 2. Coplanarity applies to the exposed pad as well as the terminals. 3. Refer JEDEC MO-220. 4. Recommended land pattern is for reference only. 5. Thermal pad soldering area 12-0529 Note: For latest package info, please check: http://www.pericom.com/products/packaging/mechanicals.php 13-0098