PI3HDMI341AR PERICOM | Alldatasheet

Document overview

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Technical content

Features

  • Supply voltage, VCC = 3.3V ±5%
  • Each Port is compatible w/ DVI, HDMI 1.1, HDMI 1.2 or HDMI 1.3 signals
  • Supports both AC-coupled and DC-coupled inputs
  • High Performance, up to 1.65 Gbps per channel
  • Switching support for 3 side band signals (SCL, SDA and HPD)
  • 5V Tolerance on all side band signals
  • SCL, SDA, and HPD pins are the only pins that can support HOT INSERTION
  • Integrated 50-ohm (±10%) termination resistors at each high speed signal input
  • Confi gurable output swing control (500mV, 750mV, 1000mV)
  • Confi gurable Pre-Emphasis levels (0dB, 1.5dB, 3.5dB, & 6.0dB)
  • Confi gurable De-Emphasis (0dB, -3.5dB, -6.0dB, -9.5dB)
  • Optimized Equalization Single default setting will support all cable lengths
  • ESD protection = 8kV (typical) on high-speed data channels only
  • Propagation delay ≤ 2ns
  • High Impedance Outputs when disabled
  • Packaging (Pb-free & Green): 80-contact LQFP (FF80)

Description

Pericom Semiconductor’s PI3HDMI341AR 3:1 active switch circuit is targeted for high-resolution video networks that are based on DVI/HDMI standards and TMDS signal processing. The PI3HDMI341AR is an active 3 TMDS to 1 TMDS receiver switch with Hi-Z outputs. The device receives differential signals from selected video components and drives the video display unit. It provides three controllable output swings that can be controlled through a single bit. The allowable output swings are 500mV, 750mV and 1000mV. This solution also provides a unique advanced pre-emphasis technique to increase rise and fall times which are reduced during transmission across long distances. Each complete HDMI/DVI channel also has slower speed, side band signals, that are required to be switched. Pericom’s solution provides a complete solution by integrating the side band switch together with the high speed switch in a single solution. Using Equalization at the input of each of the high speed channels, Pericom can successfully eliminate deterministic jitter caused by long cables from the source to the sink. The elimination of the deterministic jitter allows the user to use much longer cables (up to 25 meters). The maximum DVI/HDMI Bandwidth of 1.65 Gbps provides 8- bit deep color support, which is offered by HDMI revision 1.3. Due to its active uni-directional feature, this switch is designed for usage only for the video receiver’s side. For consumer video networks, the device sits at the receiver’s side to switch between multiple video components, such as PC, DVD, STB, D-VHS, etc. The PI3HDMI341AR is the industry’s fi rst active DVI/HDMI switch compatible with HDMI 1.1, 1.2, and 1.3 which ensures transmitting high-bandwidth video streams from video components to the display unit. The PI3HDMI341AR also provides enhanced robust ESD/EOS protection of 8kV, which is required by many consumer video networks today. The Optimized Equalization provides the user a single optimal setting that can provide HDMI compliance for all cable lengths: 2meter, 10meter, 15meter, and 20 meter. Pericom also offers the ability to fi ne tune the equalization settings in situations where cable length is known. For example, if 25meter length cable isrequired, Pericom's solution can be adjusted to 16dB EQ to accept 25meter cable length. 06-0340

P-1.1 12/20/06 PI3HDMI341AR 3:1 Active HDMI 1.3 Compatible Switch with Optimized Equalization for Enhanced Signal Integrity ADVANCE INFORMATION - COMPANY CONFIDENTIAL Pin Confi guration VCC HPD2 SDA2 SCL2 GND GND B21 A21 VCC A22 GND B22 VCC GND VCC HPD1 HPD_SINK SDA_SINK SCL_SINK GND GND VCC GND VCC GND OC_S2 OC_S0 OC_S1 VCC GND A14 B14 VCC A13 B13 GND A12 B12 VCC A11 B11 GND SCL1 SDA1 OC_S3 EQ_S1 GND A34 B34 A33 B33 GND A32 B32 VCC A31 B31 GND SCL3 SDA3 HPD3 VCC OE EQ_S0 A23 B23 A24 B24 VCC 06-0340

P-1.1 12/20/06 PI3HDMI341AR 3:1 Active HDMI 1.3 Compatible Switch with Optimized Equalization for Enhanced Signal Integrity ADVANCE INFORMATION - COMPANY CONFIDENTIAL Pin Description Pin # Pin Name I/O 6,9,12,15 A11, A12, A13, A14 I Port 1 TMDS Positive inputs 68, 71, 74, 77 A21, A22, A23, A24 I Port 2 TMDS Positive inputs 49, 52, 55, 58 A31, A32, A33, A34 I Port 3 TMDS Positive inputs 5, 8, 11, 14 B11, B12, B13, B14 I Port 1 TMDS Negative inputs 67, 70, 73, 76 B21, B22, B23, B24 I Port 2 TMDS Negative inputs 48, 51, 54, 57 B31, B32, B33, B34 I Port 3 TMDS Negative inputs 4, 10, 16 24, 30, 36, 37, 47, 53, 59, 65, 66, 72, 78 GND Ground HPD1 O Port 1 HPD output HPD2 O Port 2 HPD output HPD3 O Port 3 HPD output HPD_Sink I Sink side hot plug detector input. High: 5-V power signal asserted from source to sink and EDID is ready. Low: No 5-V power signal asserted from source to sink, or EDID is not ready. OE I Output Enable, Active LOW SCL1 I Port 1 DDC Clock SCL2 I Port 2 DDC Clock SCL3 I Port 3 DDC Clock SCL_Sink O Sink Side DDC Data SDA1 I/O Port 1 DDC Data SDA2 I/O Port 2 DDC Data SDA3 I/O Port 3 DDC Data SDA_Sink I/O Sink Side DDC Data 21,22,23 S1, S2, S3 I Source Input Selector 7, 13, 17 27, 33, 43, 50, 56 61, 69, 75, 79 VCC 3.3V Power Supply 34, 31, 28, 25 Y1, Y2, Y3, Y4 O TMDS positive outputs 35, 32, 29, 26 Z1, Z2, Z3, Z4 O TMDS negative outputs 41, 60 EQ_S0, EQ_S1 I Equalizer controls(1) 19, 18, 20, 1 OC_S0, OC_S1, OC_S2, OC_S3 I Output buffer controls Note: OC_S3 has an internal pull-up resistor. OC_S2 has an internal pull-down resistor. Note: 1. EQ_S0 has an internal pull-down and EQ_S1 has an internal pull-up 06-0340

P-1.1 12/20/06 PI3HDMI341AR 3:1 Active HDMI 1.3 Compatible Switch with Optimized Equalization for Enhanced Signal Integrity ADVANCE INFORMATION - COMPANY CONFIDENTIAL Switch Block Diagram CC V r e vie c e R Q E h ti w RINT CC V r e vie c e R Q E h ti w CC V r e vie c e R Q E h ti w CC V r e vie c e R Q E h ti w CC V r e vie c e R Q E h ti w CC V r e vie c e R Q E h ti w CC V r e vie c e R Q E h ti w CC V r e vie c e R Q E h ti w CC V r e vie c e R Q E h ti w CC V r e vie c e R Q E h ti w CC V r e vie c e R Q E h ti w CC V r e vie c e R Q E h ti w Control Logic 3-to-1 MUX TDMS Drive TDMS Drive TDMS Drive TDMS Drive . . . . . . . . . RINT RINT RINT RINT RINT RINT RINT RINT RINT RINT RINT A24 B24 A23 B23 A22 B22 A21 B21 A34 B34 A33 B33 A32 B32 A31 B31 HPD1 HPD2 HPD3 A14 B14 A13 B13 A12 B12 A11 B11 OE HPD_SINK SCL_SINK SCL1 SDA1 SCL2 SDA2 SCL3 SDA3 SDA_SINK OC_S1 OC_S2 OC_S3 E2_S1 OC_S0 E2_S0 06-0340

P-1.1 12/20/06 PI3HDMI341AR 3:1 Active HDMI 1.3 Compatible Switch with Optimized Equalization for Enhanced Signal Integrity ADVANCE INFORMATION - COMPANY CONFIDENTIAL Truth Table Control Pins I/O Selected Hot Plug Detect Status Y/Z SCL_Sink SDA_Sink HPD1 HPD2 HPD3 H x x A1/B1 SCL1 SDA1 HPD_Sink L L L H x A2/B2 SCL2 SDA2 L HPD_Sink L L L H A3/B3 SCL3 SDA3 L L HPD_Sink L L L None (Hi-Z) None (Hi-Z) L L L OC Setting Value Logic Table Input Control Pins Setting Value OC_S3 OC_S2 OC_S1 OC_S0 Vswing (mV) Vos (V) Pre-emphasis/De-emphasis (dB) 500 3.06 none 750 2.95 none 1000 2.84 none 500 3.02 none 500 3.06 500 3.05 1.5 500 2.97 3.5 500 2.9 500 3.08 340 3.08 -3.5 270 3.08 160 3.08 -9.5 1000 2.85 830 2.85 -3.5 500 2.85 330 2.85 -9.5 EQ Setting Value Logic Table EQ_S1 EQ_S0 Setting Value 3dB on all high speed inputs 8dB on all high speed inputs Optimized Equalization enabled on all high speed inputs (default value if both EQ_S0 and EQ_S1 are left fl oating) 16dB on all high speed inputs 06-0340

P-1.1 12/20/06 PI3HDMI341AR 3:1 Active HDMI 1.3 Compatible Switch with Optimized Equalization for Enhanced Signal Integrity ADVANCE INFORMATION - COMPANY CONFIDENTIAL Note: Stresses greater than those listed under MAX I MUM RAT INGS may cause permanent damage to the de vice. This is a stress rating only and func tion al op er a tion of the device at these or any other conditions above those indicated in the operational sections of this spec i fi ca tion is not implied. Exposure to ab- solute max i mum rating con di tions for extended periods may affect re li abil i ty. Maximum Ratings (Above which useful life may be impaired. For user guide lines, not tested.) Recommended Operating Conditions Symbol Parameter Min. Typ. Max. Units VCC Supply Voltage 3135 3.3 3465 V TA Operating free-air temperature TMDS Differential Pins (A/B) VID Receiver peak-to-peak differential input voltage 150 1560 mVp-p VIC Input common mode voltage VCC + 0.01 V VCC TMDS output termination voltage 3.135 3.3 3.465 V RT Termination resistance ohm Signaling rate 1.65 Gbps Control Pins (OC_Sx, EQ_Sx, S, OE) VIH LVTTL High-level input voltage VCC V VIL LVTTL Low-level input voltage GND 0.8 DDC Pins (SCL, SCL_SINK, SDA, SDA_SINK) VI(DDC) Input voltage GND 5.5 V Status Pins (HPD_SINK) VIH LVTTL High-level input voltage 5.3 V VIL LVTTL Low-level input voltage GND 0.8 06-0340

P-1.1 12/20/06 PI3HDMI341AR 3:1 Active HDMI 1.3 Compatible Switch with Optimized Equalization for Enhanced Signal Integrity ADVANCE INFORMATION - COMPANY CONFIDENTIAL Item HDMI 1.3 Spec Pericom Product Spec Operating Conditions Termination Supply Voltage, VCC 3.3V ≤ 5% 3.30 ± 10% Terminal Resistance 50-ohm ± 10% 45 to 55-ohm Source DC Characteristics at TP1 Single-ended high level output voltage, VH VCC ± 10mV VCC ±5mV Single-ended low level output voltage, VL ( VCC - 600mV) ≤ VL ≤ ( VCC- 400mV) ( VCC - 600mV) ≤ VL ≤ ( VCC - 400mV) Single-ended output swing voltage, Vswing 400mV ≤ Vswing ≤ 600mV 400mV ≤ Vswing ≤ 600mV Single-ended standby (off) output voltage, Voff VCC ± 10mV VCC ± 10mV Transmitter AC Characteristics at TP1 Risetime/Falltime (20%-80%) 75ps ≤ Risetime/Falltime ≤ 0.4 Tbit (75ps ≤ tr/tf ≤ 242ps) @ 1.65 Gbps 240ps Intra-Pair Skew at Transmitter Connector, max

0.15 Tbit

(90.9ps @ 1.65 Gbps) 60ps max Inter-Pair Skew at Transmitter Connector, max

0.2 Tpixel

(1.2ns @ 1.65 Gbps) 100ps max Clock Jitter, max

0.25 Tbit

(151.5ps @ 1.65 Gbps) 82ps max Sink Operating DC Characteristics at TP2 Input Differential Voltage Level, Vdiff 150 ≤ Vdiff ≤ 1200mV 150mV ≤ VDIFF ≤ 1200mV Input Common Mode Voltage Level, VICM ( VCC - 300mV) ≤ Vicm ≤ ( VCC- 37.5mV) Or VCC ±10% ( VCC - 300mV) ≤ Vicm ≤ ( VCC- 37.5mV) Or VCC ±10% Sink DC Characteristics When Source Disabled or Disconnected at TP2 Differential Voltage Level VCC ± 10mV VCC ±10mV TMDS Compliance Test Results 06-0340

P-1.1 12/20/06 PI3HDMI341AR 3:1 Active HDMI 1.3 Compatible Switch with Optimized Equalization for Enhanced Signal Integrity ADVANCE INFORMATION - COMPANY CONFIDENTIAL Electrical Characteristics (over recommended operating conditions unless otherwise noted) Symbol Parameter Test Conditions Min. Typ.(1) Max. Units ICC Supply Current VIH = VCC, VIL = VCC - 0.4V, RT = 50-ohm, VCC = 3.3V Am/Bm = 1.65 Gbps HDMI data pattern, m = 2, 3, 4 A1/B1 = 165 MHz clock 190 230 mA PD Power Dissipation 394 657 mW TMDS Differential Pins (A/B; Y/Z) VOH Single-ended high-level output voltage VCC = 3.3V, RT = 50-ohm Pre-emphasis/De-emphasis = 0dB VCC- VCC + mV VOL Single-ended low-level output voltage VCC - 600 VCC - 400 Vswing Single-ended output swing voltage 400 600 VOD(O) Overshoot of output differential volt- age 15% Vswing VOD(U) Undershoot of output differential volt- age 12% 25% ΔVOC(SS) Change in steady-state common-mode output voltage between logic states 0.5 mV |I(OS)| Short circuit output current mA VODE(SS) Steady state output differential voltage OC_S0 = VCC, Am/Bm = 250 Mbps HDMI data pattern, m = 2, 3, 4 A1/B1 = 25 MHz clock 560 840 mVp-p VODE(PP) Peak-to-peak output differential voltage 800 1200 VI(open) Single-ended input voltage under high impedance input or open input II = 10μA VCC - 10 VCC + 10 mV RINT Input termination resistance VIN = 2.9V ohm DDC I/O Pins (SCL, SCL_SINK, SDA, SDA_SINK) |Ilkg| Input leakage current VI = 0.1VCC to 0.9VCC to isolated DDC ports 0.1 μA CIO Input/output capacitance VI = 0V 7.5 pF RON Switch resistance IO = 3mA, VO = 0.4V ohm VPASS Switch output voltage VI = 3.3V, II = 100μA 1.5(2) 2.0 2.5(3) V Status Pins (HPD) VOH(TTL) TTL High-level output voltage IOH = -8mA 2.4 V VOL(TTL) TTL Low-level output voltage IOH = 8mA 0.4 V (Table Continued) 06-0340

P-1.1 12/20/06 PI3HDMI341AR 3:1 Active HDMI 1.3 Compatible Switch with Optimized Equalization for Enhanced Signal Integrity ADVANCE INFORMATION - COMPANY CONFIDENTIAL Symbol Parameter Test Conditions Min. Typ.(1) Max. Units Control Pins (OC_Sx, EQ_Sx, S, OE) |IIH| High-level digital input current VIH= 2.0V or VCC 0.1 μA |IIL| Low-level digital input current VIL = GND or 0.8V 0.1 Status Pins (HPD_SINK) |IIH| High-level digital input current VIH = 5.3V 100 μA VIH = 2.0V or VCC 0.1 |IIL| Low-level digital input current VIL = GND or 0.8V 0.1 Electrical Characteristics (Continued) Notes: 1. All typical values are at 25°C and with a 3.3V supply. 2. The value is tested in full temperature range at 3.0V. 3. The value is tested in full temperature range at 3.6V. 06-0340

P-1.1 12/20/06 PI3HDMI341AR 3:1 Active HDMI 1.3 Compatible Switch with Optimized Equalization for Enhanced Signal Integrity ADVANCE INFORMATION - COMPANY CONFIDENTIAL Switching Characteristics (over recommended operating conditions unless otherwise noted) Symbol Parameter Test Conditions Min. Typ.(1) Max. Units TMDS Differential Pins (Y/Z) tpd Propagation delay VCC = 3.3V, RT = 50-ohm, pre-emphasis/de-emphasis = 0dB 2000 ps tr Differential output signal rise time (20% - 80%) 240 tf Differential output signal fall time (20% - 80%) 240 tsk(p) Pulse skew tsk(D) Intra-pair differential skew tsk(o) Inter-pair differential skew(2) 100 tjit(pp) Peak-to-peak output jitter from Y/Z(1) residual jitter pre-emphasis/de-emphasis = 0dB, Am/Bm = 1.65 Gbps HDMI data pat- tern, m = 2 ,3, 4 A1/B1 = 165 MHz clock tjit(pp) Peak-to-peak output jitter from Y/Z(2:4) residual jitter tDE De-emphasis duration de-emphasis = -3.5dB, Am/Bm = 250 Mbps HDMI data pattern, m = 2, 3, 4 A1/B1 = 25 MHz clock 240 tSX Select to switch output ns ten Enable time tdis Disable time DDC I/O Pins (SCL, SCL_SINK, SDA, SDA_SINK) tpd(DDC) Propagation delay from SCLn to SCL_SINK or SDAn to SDA_SINK or SDA_SINK to SDAn CL = 10pF 0.4 2.5 ns Control and Status Pins (OC_SX, EQ_SX, S, HPD_SINK, HPD) tpd(HPD) Propagation delay (from HPD_SINK to the active port of HPD) CL = 10pF 6.0 ns tsx(HPD) Switch time (from port select to the lat- est valid status of HPD) 6.5 Notes: 1. All typical values are at 25°C and with a 3.3V supply. 2. tsk(o) is the magnitude of the difference in propagation delay times between any specifi ed terminals of channel 2 to 4 of a device when inputs are tied together. 06-0340

P-1.1 12/20/06 PI3HDMI341AR 3:1 Active HDMI 1.3 Compatible Switch with Optimized Equalization for Enhanced Signal Integrity ADVANCE INFORMATION - COMPANY CONFIDENTIAL

Application Information

All VCC pins are recommended to have a 0.01uF capacitor tied from VCC to GND to fi lter supply noise TMDS inputs Standard TMDS terminations have already been integrated into Pericom’s PI3HDMI341AR device. Therefore, external termina- tions are not required. Any unused port must be left fl oating and not tied to GND. HPD Pins The HPD pins on the PI3HDMI341AR require external pull down transistors to maintain a 0V signal when port is not selected, as follows: This architecture allows EDID readability when the DTV is power off or power on. SCL and SDA pins For EDID readability when the Sink is power off, 3 EEPROMs will be needed as follows PI3HDMI341AR HPD1 HPD2 HPD3 100K 100K 100K HPD HPD HPD PI3HDMI341AR SCL1 SDA1 SCL2 SDA2 SCL3 SDA3 HDMI RX 06-0340

P-1.1 12/20/06 PI3HDMI341AR 3:1 Active HDMI 1.3 Compatible Switch with Optimized Equalization for Enhanced Signal Integrity ADVANCE INFORMATION - COMPANY CONFIDENTIAL Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com

Ordering Information

80-pin, Pb-free & Green LQFP Notes:

  • Thermal characteristics can be found on the company web site at www.pericom.com/packaging/
  • E = Pb-free and Green
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