PI3HDMI101 | DigiCamel IC Datasheet

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PI3HDMI101 PERICOM | Alldatasheet

Document overview

Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
PDF pages: 12

Technical content

Features

Supply voltage, VDD = 3.3V ±5%
Support for both DVI and HDMI TM signals
Supports both AC-coupled and DC-coupled inputs
Supports Deep Color TM
High Performance, up to 2.5 Gbps per channel
5V Tolerance on I 2C path
Integrated 50-ohm (±10%) termination resistors at each high speed signal input
Rx Sense Support, CLK-off channel is switched to 250K-Ohm pull-up vs. 50-Ohm pull-up
Conﬁ gurable output swing control (400mV , 500mV , 600mV , 750mV , 1000mV)
Conﬁ gurable Pre-Emphasis levels (0dB, 1.5dB, 3.5dB, & 6.0dB, 9.0dB)
Conﬁ gurable De-Emphasis (0dB, -3.5dB, -6.0dB, -9.5dB)
Optimized Equalization Single default setting will support all cable lengths
8kV Contact ESD protection on all high speed input data channels per IEC 61000-4-2
Hot insertion support on output high speed pins & SCL/SDA pins only
Propagation delay ≤ 1ns
High Impedance Outputs when disabled
Packaging (Pb-free & Green): 42-contact TQFN (ZH42)

Description

Pericom Semiconductor’s PI3HDMI101 1:1 active redriver circuit is targeted for high-resolution video networks that are based on DVI/HDMI TM standards and TMDS signal processing. The PI3HDMI101 is an active redriver with Hi-Z outputs. The device receives differential signals from selected video components and drives the video display unit. This solution also provides a unique advanced pre-emphasis technique to increase rise and fall times which are reduced during transmission across long distances. Each complete HDMI TM/DVI channel also has slower speed, side band signals, that are required to be switched. Pericom’s solution provides a complete solution by integrating the side band buffer together with the high speed buffer in a single solution. Using Equalization at the input of each of the high speed channels, Pericom can successfully eliminate deterministic jitter caused by long cables from the source to the sink. The elimination of the deterministic jitter allows the user to use much longer cables (up to 25 meters). The maximum DVI/HDMI TM Bandwidth of 2.5 Gbps provides 36- bit deep color TM support, which is offered by HDMI TM revision 1.3. The PI3HDMI101 also provides enhanced robust ESD/EOS protection of 8kV , which is required by many consumer video networks today. The Optimized Equalization provides the user a single optimal setting that can provide HDMITM compliance for all cable lengths: 1meter to 20meters and color depths of 8bit/ch, or 12bit/ch. Pericom also offers the ability to ﬁ ne tune the equalization settings in situations where cable length is known. For example, if 25meter cable length is required, Pericom's solution can be adjusted to 16dB EQ to accept 25meter cable length. 07-0230

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1:1 Active HDMITM Redriver with Optimized Equalization & I2C Buffer HDMI, High-Deﬁ nition Multimedia Interface, and Deep Color are trademarks of HDMI Licensing, LLC in the United States and other countries. ADV ANCE INFORMATION - COMPANY CONFIDENTIAL Pin Conﬁ guration TMDS Receiver Block CLK+/- 250K/nonmarkingreturnohm R AV R 2 DD Control Rx Sense Each high speed data and clock input has integrated equalization that can eliminate deterministic jitter caused by input cables. All activity can be conﬁ gured using pin strapping. The Rx block is designed to receive all rel- evant signals directly from the HDMITM connector without any additional circuitry, 3 High speed TMDS data, 1 pixel clock, and DDC signals. Pixel clock channel has following temination scheme for Rx Sense support. 42 41 40 39 18 19 20 21 SCL_T VDD GND OUT_CLK– OUT_CLK+ VDD OUT_D0– OUT_D0+ GND OUT_D1– OUT_D1+ VDD OUT_D2– OUT_D2+ GND VDD OC_S3 EQ_S0 EQ_S1 GND IN_CLK– IN_CLK+ VDD IN_D0– IN_D0+ GND IN_D1– IN_D1+ VDD IN_D2– IN_D2+ GND Rx_Sense DCC_EN OE OC_S0 OC_S1 OC_S2 IADJ SCL_R SDA_R SDA_T GND Rx Sense LR 2 switch is open, CLK+/- termination is 250kΩ HR 2 switch is closed, CLK+/- termination is 50Ω 07-0230

3 PS8924A 11/29/07

1:1 Active HDMITM Redriver with Optimized Equalization & I2C Buffer HDMI, High-Deﬁ nition Multimedia Interface, and Deep Color are trademarks of HDMI Licensing, LLC in the United States and other countries. ADV ANCE INFORMATION - COMPANY CONFIDENTIAL I2C Buffer Buffer/nonmarkingreturnT Buffer/nonmarkingreturnR Port/nonmarkingreturnR Port/nonmarkingreturnT IADJ,/nonmarkingreturnDDC_EN The VOL of the Buffer R is around 0.2V . The VOL of the Buffer T is around 0.7V . Functional Truth Tables IADJ External Pull-Up Range H 1KΩ to 2KΩ (HDMI spec) L > 3KΩ (4.7KΩ typically) DDC_EN Port T / Port R (if no external pull-up resistor L Hi-Z (I2C buffer disable) H (I2C buffer enable) 07-0230

4 PS8924A 11/29/07

1:1 Active HDMITM Redriver with Optimized Equalization & I2C Buffer HDMI, High-Deﬁ nition Multimedia Interface, and Deep Color are trademarks of HDMI Licensing, LLC in the United States and other countries. ADV ANCE INFORMATION - COMPANY CONFIDENTIAL Pin Description Pin # Pin Name I/O Description 5, 8, 11, 14 IN_CLK+, IN_D0+, IN_D1+, IN_D2+ I TMDS Positive inputs 4, 7, 10, 13 IN_CLK-, IN_D0-, IN_D1-, IN_D2- I TMDS Negative inputs 3, 9, 15, 24, 30, 36 GND P Ground

18 OE I Output Enable, Active LOW

41 SCL_R I/O DDC Clock , Source Side

40 SDA_R I/O DDC Data, Source Side

6, 12, 23, 27, 33, 37 VDD P 3.3V Power Supply 34, 31, 28, 25 OUT_CLK+, OUT_D0+, OUT_D1+, OUT_D2+ O TMDS positive outputs 35, 32, 29, 26 OUT_CLK-, OUT_D0-, OUT_ D1-, OUT_D2- O TMDS negative outputs 1, 2 EQ_S0, EQ_S1 I Equalizer controls, both pins with internal pull-ups 19, 20, 21, 22 OC_S0, OC_S1, OC_S2, OC_S3 I Output buffer controls Note: All 4 pins have internal pull-ups

17 DDC_EN I I2C path enable

38 SCL_T I/O DDC Clock, Sink side

39 SDA_T I/O DDC Data, Sink side

16 Rx_Sense I Rx_Sense control

42 IADJ I High/Low V oltage Selection, depends on I2C exter-

5 PS8924A 11/29/07

1:1 Active HDMITM Redriver with Optimized Equalization & I2C Buffer HDMI, High-Deﬁ nition Multimedia Interface, and Deep Color are trademarks of HDMI Licensing, LLC in the United States and other countries. ADV ANCE INFORMATION - COMPANY CONFIDENTIAL Complete high speed input Rx block is as follows: rev ie ce R Q E h t iw rev ie ce R Q E h t iw rev ie ce R Q E h t iw rev ie ce R Q E h t iw EQ_S1 EQ_S0 IN_D0+ IN_D0- IN_D1+ IN_D1- IN_D2+ IN_D2- DDV R2 R2250kΩ 150kΩ IN_CLK+ IN_CLK- OUT_D0+ OUT_D0- OUT_D1+ OUT_D1- OUT_D2+ OUT_D2- OUT_CLK+ OUT_CLK- TMDS drive TMDS drive TMDS drive TMDS drive OC_S0 OC_S1 OC_S2 OC_S3 OE Control Buffer T Buffer R Port R Port T IADJ, DDC_EN DDV DDV DDV 50Ω 50Ω 50Ω 50Ω 50Ω 50Ω 07-0230

6 PS8924A 11/29/07

1:1 Active HDMITM Redriver with Optimized Equalization & I2C Buffer HDMI, High-Deﬁ nition Multimedia Interface, and Deep Color are trademarks of HDMI Licensing, LLC in the United States and other countries. ADV ANCE INFORMATION - COMPANY CONFIDENTIAL Truth Table OE Function

0 Active

1 All TMDS outputs are Hi-Z

EQ Setting Value Logic Table EQ_S1(2) EQ_S0(2) Setting Value @ 825MHz 0 0 3dB on all high speed inputs 0 1 8dB on all high speed inputs 1 0 12dB on all high speed inputs 1 1 16dB on all high speed inputs Notes: 1. External pull-ups are required along SCL/SDA path 2. Internal 100Kohm pull-ups Truth Table 1 OC_S3(2) OC_S2(2) OC_S1(2) OC_S0(2) Vswing (mV) Pre/De- emphasis 0 0 0 0 500 0 0 0 0 1 600 0 0 0 1 0 750 0 0 0 1 1 1000 0 0 1 0 0 500 0 0 1 0 1 500 1.5dB 0 1 1 0 500 3.5dB 0 1 1 1 500 6dB 1 0 0 0 400 0 1 0 0 1 400 3.5dB 1 0 1 0 400 6dB 1 0 1 1 400 9dB 1 1 0 0 1000 0 1 1 0 1 660 -3.5dB 1 1 1 0 500 -6dB 1 1 1 1 330 -9dB 07-0230

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1:1 Active HDMITM Redriver with Optimized Equalization & I2C Buffer HDMI, High-Deﬁ nition Multimedia Interface, and Deep Color are trademarks of HDMI Licensing, LLC in the United States and other countries. ADV ANCE INFORMATION - COMPANY CONFIDENTIAL DD Note: Stresses greater than those listed under MAX I MUM RAT INGS may cause permanent damage to the de vice. This is a stress rating only and func tion al op er a tion of the device at these or any other conditions above those indicated in the operational sections of this spec i ﬁ ca tion is not implied. Exposure to ab- solute max i mum rating con di tions for extended periods may affect re li abil i ty. Maximum Ratings (Above which useful life may be impaired. For user guide lines, not tested.) Recommended Operating Conditions Symbol Parameter Min. Typ. Max. Units VDD Supply V oltage 3.135 3.3 3.465 V TA Operating free-air temperature 0 70 °C TMDS Differential Pins VID Receiver peak-to-peak differential input voltage 150 1560 mVp-p VIC Input common mode voltage 2 VDD + 0.01 V VDD TMDS output termination voltage 3.135 3.3 3.465 V RT Termination resistance when RxSense pin is HIGH 45 50 55 ohm TMDS Data Rate Signaling rate 0.25 2.5 Gbps Control Pins (OC_Sx, EQ_Sx, OE, DDC_EN) VIH LVTTL High-level input voltage 2 VDD VVIL LVTTL Low-level input voltage GND 0.8 DDC Pins (SCL_R, SCL_T, SDA_R, SDA_T) VI(DDC) Input voltage GND 5.5 V I2C Pins (SCL_T, SDA_T) VIH High-level input voltage 0.7 x VDD 5.5 V VIL Low-level input voltage -0.5 0.3 x VDD V VICL Low-level input voltage contention (1) -0.5 0.4 V I2C Pins (SCL_R, SDA_R) VIH High-level input voltage 0.7 x VDD 5.5 V VIL Low-level input voltage -0.5 0.3 x VDD V Notes: 1. VIL speciﬁ cation is for the ﬁ rst low level seen by the SCL/SDA lines. VICL is for the second and subsequent low levels seen by the TSCL/TSDA lines. 07-0230

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1:1 Active HDMITM Redriver with Optimized Equalization & I2C Buffer HDMI, High-Deﬁ nition Multimedia Interface, and Deep Color are trademarks of HDMI Licensing, LLC in the United States and other countries. ADV ANCE INFORMATION - COMPANY CONFIDENTIAL Symbol Parameter Test Conditions Min. Typ. (1) Max. Units IDD Supply Current VIH = VDD, VIL = VDD - 0.4V , RT = 50-ohm, VDD = 3.3V Data Inputs = 1.65 Gbps HDMI data pattern CLK Inputs = 165 MHz clock OC_Sx = Low, x = 0,1,2,3 120 mA PD Power Dissipation 400 mW IDDQ Standby Current OE = HIGH, VDD = 3.3V , Source = off 2 mA TMDS Differential Pins VOH Single-ended high-level output voltage VDD = 3.3V , RT = 50-ohm Pre-emphasis/De-emphasis = 0dB VDD- VDD + 10 mVVOL Single-ended low-level output voltage VDD - 600 VDD - 400 Vswing Single-ended output swing voltage 400 600 VOD(O) Overshoot of output differential volt- age 6% 15% 2x Vswing VOD(U) Undershoot of output differential volt- age 12% 25% ΔV OC(SS) Change in steady-state common-mode output voltage between logic states 0.5 5 mV I (OS) Short circuit output current 12 mA VODE(SS) Steady state output differential voltage OC_Sx = GND, Data Inputs = 250 Mbps HDMI data pattern,

25 MHz pixel clock, x = 0,1,2,3

V ODE(PP) Peak-to-peak output differential voltage 800 1200 VI(open) Single-ended input voltage under high impedance input or open input II = 10μA VDD - 10 VDD + 10 mV RINT Input termination resistance VIN = 2.9V , RxSense pin = HIGH 45 50 55 ohm Control Pins (OE, DDC_EN, IADJ) IIH High-level digital input current V IH = 2V or VDD -10 10 μA IIL Low-level digital input current V I = GND or 0.8 V -10 10 μA I2C Pins (SCL_T, SDA_T) (T Port) Iikg Input leakage current VI = 5.5 V -50 50 μAVI = VDD -10 10 IOH High-level output current VO = 3.6 V -10 10 μA IIL Low-level input current VIL = GND -40 40 μA VOL Low-level output voltage IOL = 2.5 mA IADJ = H 0.65 0.9 V CIO Input/output capacitance VI = 5.0 V or 0 V , Frequency = 100kHz 25 pFVI = 3.0 V or 0 V , Freq = 100kHz 10 VOH(TTL) 1 TTL High-level output voltage I OH = -8 mA 2.4 V VOL(TTL) 1 TTL Low-level output voltage I OL = 8 mA 0.4 V Note: 1. V oh/V ol of external driver at the R and T ports. (Table Continued) Electrical Characteristics (over recommended operating conditions unless otherwise noted) 07-0230

9 PS8924A 11/29/07

1:1 Active HDMITM Redriver with Optimized Equalization & I2C Buffer HDMI, High-Deﬁ nition Multimedia Interface, and Deep Color are trademarks of HDMI Licensing, LLC in the United States and other countries. ADV ANCE INFORMATION - COMPANY CONFIDENTIAL Switching Characteristics (over recommended operating conditions unless otherwise noted) Symbol Parameter Test Conditions Min. Typ. (1) Max. Units TMDS Differential Pins tpd Propagation delay VDD = 3.3V , RT = 50-ohm, pre-emphasis/de-emphasis = 0dB 2000 ps tr Differential output signal rise time (20% - 80%) 75 240 tf Differential output signal fall time (20% - 80%) 75 240 t sk(p) Pulse skew 10 50 tsk(D) Intra-pair differential skew 23 50 tsk(o) Inter-pair differential skew(2) 100 tCLKjit(pp) Peak-to-peak output jitter for TMDS clock channel pre-emphasis/de-emphasis = 0dB, Data Inputs = 1.65 Gbps HDMI data pattern CLK input = 165 MHz clock 15 30 t Datajit(pp) Peak-to-peak output jitter for TMDS data channels 18 50 tDE De-emphasis duration de-emphasis = -3.5dB, Data Inputs =

250 Mbps HDMI data pattern,

CLK output = 25 MHz clock 240 t SX Select to switch output 10 nsten Enable time 200 tdis Disable time 10 I2C PINS (SCL_R, SDA_R, SCL_T, SDA_T) tPLH Propagation delay time, low-to-high-level output SCL_T/SDA_T to SCL_R/SDA_R IADJ = V DD CLOAD = 300 pF Tbuffer : Rpu = 2K, Vpu = 3.0V 500 ns tPHL Propagation delay time, high-to-low-level output SCL_T/SDA_T to SCL_R/SDA_R 136 t PLH Propagation delay time, low-to-high-level output SCL_T/SDA_T to SCL_R/SDA_R Rbuffer : Rpu = 1.2K, Vpu = 3.3V or Rpu = 1.8K, Vpu = 5V IADJ = GND C LOAD = 100 pF 450 tPHL Propagation delay time, high-to-low-level output SCL_T/SDA_T to SCL_R/SDA_R 136 tr SCL_T/SDA_T Output signal rise time See Fig. A 999 tf SCL_T/SDA_T Output signal fall time 90 tr SCL_R/SDA_R Output signal rise time 999 tf SCL_R/SDA_R Output signal fall time 90 tset Enable to start condition 6 10 ns thold Enable after stop condition 6 10 I2C Pins (SCL_R, SDA_R Port) Iikg Input leakage current VI = 5.5 V -50 50 μAVI = VDD -10 10 IOH High-level output current VO = 3.6 V -10 10 μA IIL Low-level input current VIL = GND -10 10 μA VOL Low-level output voltage IOL = 4 mA, IADJ = H 0.2 V CI Input capacitance VI = 5.0 V or 0 V , Freq = 100kHz 25 pFVI = 3.0 V or 0 V , Freq = 100kHz 10 07-0230

10 PS8924A 11/29/07

1:1 Active HDMITM Redriver with Optimized Equalization & I2C Buffer HDMI, High-Deﬁ nition Multimedia Interface, and Deep Color are trademarks of HDMI Licensing, LLC in the United States and other countries. ADV ANCE INFORMATION - COMPANY CONFIDENTIAL PULSE GENERATOR D.U.T. VDD 3.3V/nonmarkingreturn±/nonmarkingreturn10% R/nonmarkingreturn=/nonmarkingreturn1.2kΩL C/nonmarkingreturn=/nonmarkingreturn100pFLVIN VIOUT PULSE GENERATOR D.U.T. V DD 3.3V/nonmarkingreturn±/nonmarkingreturn10% R/nonmarkingreturn=/nonmarkingreturn2kΩL C/nonmarkingreturn=/nonmarkingreturn300pFLVIN VIOUT IADJ/nonmarkingreturn=/nonmarkingreturnL IADJ/nonmarkingreturn=/nonmarkingreturnH tf tf 20% 80% 20% 80% tPHL tPLH RSCL/RSDA Input TSCL/TSDA Input VDD VDD /2 0.1V 3.3V±10% 1.5V VOL tf tf 20% 80% 20% 80% tPHL tPLH RSCL/RSDA Input TSCL/TSDA Input VDD 1.5V 0.1V 5V±10% VOL VDD /2 tPLH Figure A. I2C Timing Test Circuit and Deﬁ nition 07-0230

11 PS8924A 11/29/07

1:1 Active HDMITM Redriver with Optimized Equalization & I2C Buffer HDMI, High-Deﬁ nition Multimedia Interface, and Deep Color are trademarks of HDMI Licensing, LLC in the United States and other countries. ADV ANCE INFORMATION - COMPANY CONFIDENTIAL Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com

Ordering Information

Ordering Code Package Code Package Description PI3HDMI101ZHE ZH 42-pin, Pb-free & Green TQFN Notes:

Thermal characteristics can be found on the company web site at www.pericom.com/packaging/
E = Pb-free and Green
Adding an X Sufﬁ x = Tape/Reel
HDMI & Deep Color are trademarks of Silicon Image DESCRIPTION: 42-contact Thin Fine Pitch Quad Flat No-Lead (TQFN) PACKAGE CODE: ZH (ZH42) DOCUMENT CONTROL #: PD-2035 REVISION: A DATE: 03/10/06 06-0219

Application Information

All VDD pins are recommended to have a 0.01uF capacitor tied from VDD to GND to ﬁ lter supply noise TMDS inputs Standard TMDS terminations have already been integrated into Pericom’s PI3HDM101 device. Therefore, external terminations are not required. Any unused port must be left ﬂ oating and not tied to GND. 07-0230

12 PS8924A 11/29/07

1:1 Active HDMITM Redriver with Optimized Equalization & I2C Buffer HDMI, High-Deﬁ nition Multimedia Interface, and Deep Color are trademarks of HDMI Licensing, LLC in the United States and other countries. ADV ANCE INFORMATION - COMPANY CONFIDENTIAL HDMI Licensing, LLC, a wholly owned subsidiary of Silicon Image, Inc., is the agent responsible for li- censing the HDMI Speciﬁ cation, promoting the HDMI standard and providing education on the beneﬁ ts of HDMI to retailers and consumers. The HDMI Speciﬁ cation was developed by Sony, Hitachi, Thomson (RCA), Philips, Matsushita (Panasonic), Toshiba and Silicon Image as the digital interface standard for the consumer electronics market. The HDMI speciﬁ cation combines uncompressed high-deﬁ nition video and multi-channel audio in a single digital interface to provide crystal-clear digital quality over a single cable. For more information about HDMI, please visit www.hdmi.org 07-0230

Product Information

PI3HDMI101 specifications and overview.

Summary

1:1 Active HDMITM Redriver with Optimized Equalization & I2C Buffer

Description

1:1 Active HDMITM Redriver with Optimized Equalization & I2C Buffer

Source title PI3HDMI101 Datasheet(PDF) - Pericom Semiconductor Corporation

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