PI3EQX4951B

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Document overview

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Technical content

Features

Î SATA2 i, m; external SATA2 Î Two 3.0Gbps differential signal pairs Î Independent Digital Output Emphasis Control Î 100Ω Differential CML I/O’s Î Input signal level detect and squelch for each channel Î OOB Support Î Enhanced Mode Features: à A djustable Receiver Equalization à I ndependent Analog Output Swing Adjustment à I ndependent Analog Output Emphasis Control à I ndependent Channel Power Down Control Î Low Power (220mW per Channel) Î Stand-by Mode – Power Down State Î Supply Voltage: 3.3V Î Packaging (Pb-free & Green): à 2 0-TQFN (4x4mm)

Description

Pericom Semiconductor’s PI3EQX4951B is a low power, signal ReDriver™. The device provides programmable equalization, to optimize performance over a variety of physical mediums by reducing Inter-Symbol Interference. PI3EQX4951B supports two 100Ω Differential CML data I/O’s between the Protocol ASIC to a switch fabric, across a backplane, or to extend the signals across other distant data pathways on the user’s plat- form. The integrated equalization circuitry provides flexibility with signal integrity of the signal before the ReDriver. A low-level input signal detection and output squelch function is provided for each channel. Each channel operates fully indepen- dently. When the channels are enabled (x_EN=1) and operating, that channels input signal level (on xI+/-) determines whether the output is active. If the input signal level of the channel falls below the active threshold level (Vth-) then the outputs are driven to the common mode voltage. In addition to signal conditioning, when EN = 0, the device enters a low power standby mode. Block Diagram Pin Diagram (Top Side View) EN x_EQ x_EM X_EN# xl+ xl- xO+ xO- Limiting Amp Equalizer EMx Power Management Control Circuit - Repeated 2 times - CML CML Signal Detection 6 7 8 9 19181716 A_EN# BO- AI+ AI- BO+ VDD EN B_EQ A_EQ MODE VDD AO+ AO- B_EN# BI- BI+ B_EM VDD VDD A_EM GND 10 89 18 17 GND GND AI+ AI- BO- BO+ VDD VDD AO+ AO- GND BI- BI+ VDD EN B_EM GND MODE GND A_EM VDD Standard Mode (MODE = 0) Enhanced Mode (MODE = 1) PI3EQX4951B 3.3V, 1-port, SATA2 i/m ReDriver™ with Analog/Digital Configuration 10-0248

www.pericom.com PS9016B 12/09/10 PI3EQX4951B 3.3V, 1-Port, SATA2 i/m ReDriver™ with Analog/Digital Configuration Pin Description Standard Mode Pin Enhanced Mode Pin Pin Name Type Description 9 19 A_EM Input Output emphasis adjustment for channel A. à W hen in Standard Mode (MODE= 0) digital control is enabled, and a 100KΩ pull-up resistor is enabled on A_EM. à W hen in Enhanced Mode (MODE= 1) analog resistive adjustment of emphasis is enabled. Refer to Configuration Tables and System Implementation diagrams for design guidelines. — 3 A_EN# Input Channel A Enable, is active only when in Enhanced Mode (MODE=1). Low is normal operation. High is power down mode. Has internal 100KΩ pull-down resistor. — 18 A_EQ Input Channel A Equalization adjustment is active only in Enhanced Mode (MODE = 1). With internal 100KΩ pull-up to VDD. Refer to Enhanced Mode Configuration Table and System Implementation diagram for design guidelines. AI+ AI- Input CML input forward channel A with internal 50Ω pull-up resistors connected to VBIAS (100Ω differential). AO- AO+ Output CML output channel A with internal 50Ω pull-up resistors connected to VBIAS (100Ω differential). 8 9 B_EM Input Output emphasis adjustment for channel B. à W hen in Standard Mode (MODE= 0) digital control is enabled, and a 100KΩ pull-up resistor is enabled on A_EM. à W hen in Enhanced Mode (MODE= 1) analog resistive adjustment of emphasis is enabled. Refer to Configuration Tables and System Implementation diagrams for design guidelines. — 13 B_EN# Input Channel B Enable, is active only when in Enhanced Mode (MODE=1). Low is normal operation. High is power down mode. Has internal 100KΩ pull-down resistor. — 8 B_EQ Input Channel A Equalization adjustment, is active only in Enhanced Mode (MODE = 1). With internal 100KΩ pull-up to VDD. Refer to Enhanced Mode Configuration Table and System Implementation diagram for design guidelines. BI+ BI- Input CML input return channel B with internal 50Ω pull-up, resistor connected to VBIAS (100Ω differential). BO- BO+ Output Positive CML output channel B with internal 50Ω pull-up resistor connected to VBIAS (100Ω differential). 7 7 EN Input Chip Enable "High" provides normal operation. "Low" for power down mode. With internal 100KΩ pull-up resistor. 3, 13, 18, 19, Center Pad Center Pad GND GND Supply ground. 6,10, 16, 20 6, 10, 16, 20 V DD Power 3.3V supply voltage ± 10% 17 17 MODE Input MODE selects Enhanced Mode operation and pin function when high. When MODE is low, Standard Mode operation is selected. With internal 100KΩ pull- up resistor to V DD. See Configuration tables for use information. 10-0248

www.pericom.com PS9016B 12/09/10 PI3EQX4951B 3.3V, 1-Port, SATA2 i/m ReDriver™ with Analog/Digital Configuration Configuration Table (Standard Mode) EN MODE B_EM (1) A_EM (1) Output B Emphasis Output A Emphasis Input B Equalization @ f=1.5GHz Input A Equalization @ f=1.5GHz

0 X X X Disable Disable Disable Disable

1 0 0 0 0dB 0dB 2.5dB 2.5dB 1 0 0 1 0dB 3.0dB 2.5dB 2.5dB 1 0 1 0 3.0dB 0dB 2.5dB 2.5dB 1 0 1 1 3.0dB 3.0dB 2.5dB 2.5dB Note: R efer to Standard Mode Implementation Diagram Configuration Table (Enhanced Mode) EN MODE x_EN# x_EQ Input X Equaliza- tion x_EM Output X Emphasis Function

0 X X X n/a X n/a Chip Power Down

1 1 1 X n/a X n/a Chip enabled, Channel x disabled 1 1 0 0 2.5dB 1.1K to 15K resistor Resistor Controlled, 6dB to 0dB (1) Chip and channel enabled, low input equalization 1 1 0 1 6.5dB 1.1K to 15K resistor Resistor Controlled, 6dB to 0dB (1) Chip and channel enabled, high input equalization Note: R efer to Enhanced Mode Implementation Diagram 10-0248

www.pericom.com PS9016B 12/09/10 PI3EQX4951B 3.3V, 1-Port, SATA2 i/m ReDriver™ with Analog/Digital Configuration Supply Voltage to Ground Potential 0.5V to +4.6V DC SIG Voltage 0.5V to VDD +0.5V Current Output 25mA to +25mA Power Dissipation Continuous 00mW Operating Temperature o +70°C Note: Stresses greater than those listed under MAXIMUM RAT- INGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Maximum Ratings (Above which useful life may be impaired. For user guidelines, not tested.) AC/DC Electrical Characteristics Symbol Parameter Conditions Min. Typ. Max. Units VDD Power Supply Voltage 3.0 3.6 V PSTANDBY Supply Power, Standby EN = 0 1.5 mW PIDLE Supply Power, Idle EN = 1, x_EN# = 0 DIFFP-P < VTH-SD 235 mW PACTIVE Supply Power, Active EN = 1, x_EN# = 0 DIFFP-P ≥ VTH-SD 440 mW IDD-STANDBY Supply Current Standby EN = 0 0.4 mAIDD-IDLE Supply Current Idle EN = 1, x_EN# = 0, VRX-DIF- FP-P < VTH-SD IDD-ACTIVE Supply Current Active EN = 1, x_EN# = 0, VRX-DIF- FP-P ≥ VTH-SD 120 tPD Latency From input to output 2.0 ns CML Receiver Input ZRX-DC DC Input Impedance 40 50 60 ΩZRX-DIFF-DC DC Differential Input Impedance 80 100 120 VRX-DIFFP-P Differential Input Peak-to- peak Voltage 0.2 1.6 V V RX-CM-ACP AC Peak Common Mode Input Voltage 150 mV V TH-SD Signal detect Threshold EN = 1, x_EN# = 0 50 200 (1) mVppd Note: (continued) 10-0248

www.pericom.com PS9016B 12/09/10 PI3EQX4951B 3.3V, 1-Port, SATA2 i/m ReDriver™ with Analog/Digital Configuration Symbol Parameter Conditions Min. Typ. Max. Units RLdd11_RX RX differential mode return loss 75MHz-300MHz 300MHz-600MHz 600MHz-1.2GHz 1.2GHz-2.4GHz 2.4GHz-3.0GHz 3.0 GHz-5.0GHz dB RL cc11_RX RX common mode return loss 150MHz – 300MHz 300MHZ – 600MHz 600MHz – 1.2GHz 1.2GHz – 2.4GHz 2.4GHz – 3.0GHz 3.0GHz – 5.0GHz dB RL dc11_RX RX impedance balance 150MHz – 300MHz 300MHz – 600MHz 600MHz – 1.2GHz 1.2GHz – 2.4GHz 2.4GHz – 3.0GHz 3.0GHz – 5.0GHz dB Equalization TJ Total Jitter Measured at 3Gbps/500 0.37 UI DJ Deterministic Jitter Measured at 3Gbps/500 0.19 UI CML Transmitter Output (100Ω differential)1 ZTX-DIFF-DC DC Differential TX Imped- ance 80 100 120 Ω VTX-DIFFP-P Differential Peak-to-peak Output Voltage V TX-DIFFP-P = 2 * | VTX-D+ - VTX-D- | 500 600 mV VTX-C Common-Mode Voltage | V TX-D+ + VTX-D-|/2 1 1.8 V tF, tR Transition Time 20% to 80%(1) 50 150 ps tF-tR Mis-match Transition Time 3G only; HFTP, MFTP 20 % Vamp_bal TX amplitude imbalance 3G only; HFTP, MFTP 10 % Tskew TX differential skew 1.5G and 3G; HFTP, MFTP 20 ps Vcm_ac TX AC common mode voltage 3G only; MFTP 50 mVpp VcmOOB OOB common mode delta voltage 50 mV V diffOOB OOB differential delta voltage 25 mV VTX-Pre-Ratio-max Max TX Pre-emphasis Level 6 dB AC/DC Electrical Characteristics (CML Receiver Input continued) (continued) Note: R ecommended output coupling capacitor is 4.7nF to 12nF (on each output) 10-0248

www.pericom.com PS9016B 12/09/10 PI3EQX4951B 3.3V, 1-Port, SATA2 i/m ReDriver™ with Analog/Digital Configuration Symbol Parameter Conditions Min. Typ. Max. Units RLdd11_TX TX differential mode return loss 150MHz – 300MHz 300MHz – 600MHz 600MHz – 1.2GHz 1.2GHz – 2.4GHz 2.4GHz – 3.0GHz 3.0 GHz – 5.0GHz dB RL cc11_TX TX common mode return loss 150MHz – 300MHz 300MHz – 600MHz 600MHz – 1.2GHz 1.2GHz – 2.4GHz 2.4GHz – 3.0GHz 3.0 GHz – 5.0GHz dB RL dc11_TX TX impedance balance 150MHz – 300MHz 300MHz – 600MHz 600MHz – 1.2GHz 1.2GHz – 2.4GHz 2.4GHz – 3.0GHz 3.0 GHz – 5.0GHz dB LVCMOS Control Pins VIH Input High Voltage 0.65 × VDD V VIL Input Low Voltage 0.35 × V DD IIH Input High Current 100 µA IIL Input Low Current 100 AC/DC Electrical Characteristics (CML Transmitter Output continued) 10-0248

www.pericom.com PS9016B 12/09/10 PI3EQX4951B 3.3V, 1-Port, SATA2 i/m ReDriver™ with Analog/Digital Configuration Test Condition Referenced in the Electrical Characteristic Table D.U.T. Signal Source SmA Connector In Out A SmA Connector B C FR4 30IN Standard Mode Implementation Diagram xI+ xI- EQ xO+ xO- x_EM MODE Recommended coupling capacitors are 4.7nF Output T/S/T 4/8/4 mil FR4 PCB trace Output AWG 28 SATA Cable < 6 inch < 36 inch 0 > 6 inch > 36 inch open Emphasis Setting for PCB Trace or Cable VD+ Common Mode Voltage V_D+ - V_D- 0V VCM VDIFF VD- VDIFFp-p VDIFFp-p VD+ VCM VDIFF VD- 1stTBIT 2nd +TBIT(s) VDIFF-PRE Pre-emphasis = 20.Log(VDIFF-PRE/VDIFF) Definition of Differential Voltage and Differential Voltage Peak-to-Peak Definition of Pre-emphasis 10-0248

www.pericom.com PS9016B 12/09/10 PI3EQX4951B 3.3V, 1-Port, SATA2 i/m ReDriver™ with Analog/Digital Configuration Notes: 1. Pericom PI3EQX4951 control pins are with internal 100k pull up R. 2. The R6, R10, R11 are use in standard mode. xI+ xI- x_EQ EQ VDD xO+ xO- x_EM REM Recommended coupling capacitors are 4.7nF 1.0K<REM<15K REM sets output emphasis level (See table) MODE Output T/S/T 4/8/4 mil FR4 PCB trace Output AWG 28 SATA Cable < 6 inch < 36 inch 0 > 6 inch > 36 inch open Equalization Setting for PCB Trace or Cable Output T/S/T 4/8/4 mil FR4 PCB trace Output AWG 28 SATA Cable Pre-emphasis dB REM < 3 inch < 18 inch 0 15k 4 inch 30 inch 1.5dB 7.5k 6 inch 30 inch 2.0dB 6.2k 8 inch 40 inch 2.5dB 5.1k 12 inch 60 inch 3.5dB 3.3k 16 inch 48 inch 4.5dB 2.2k 24 inch 48 inch 6.0dB 1.1k REM Suggested Inital Values for PCB Trace or Cable Enhanced Mode Implementation Diagram Application Schematic 10-0248

www.pericom.com PS9016B 12/09/10 PI3EQX4951B 3.3V, 1-Port, SATA2 i/m ReDriver™ with Analog/Digital Configuration : 20-Lead, Thin Fine Pitch Quad Flat No-Lead (TQFN)N O I T P I R C S E D : E D O C E G A K C A P 2084 - D P : # L O R T N O C T N E M U C O D - - : N O I S I V E R 8 0 / 1 1 / 9 0 : E T A D ZD20 08-0456

Ordering Information

Ordering Number Package Code Package Description PI3EQX4951BZDE ZD Pb-Free and Green 20-contact TQFN (4x4mm) Notes:

• Th ermal characteristics can be found on the company web site at www.pericom.com/packaging/
• E = P b-free and Green
• X s uffix = Tape/Reel Pericom Semiconductor Corporation • 1-800-435-2336 • All trademarks are property of their respective owners. Packaging Mechanical: 20-contact TQFN (ZD) Note: For latest package info, please check: http://www.pericom.com/products/packaging/mechanicals.php 10-0248