PI3749-00-LGIZ

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Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 26

Technical content

Datasheet sections

Features

• Up to 98.5% efficiency at 800kHz FSW
• Over 200W of continuous output power (for specific conditions)
• Fast transient response
• Parallel capable with single wire current sharing
• External frequency synchronization / interleaving
• High Side Current Sense Amplifier
• General Purpose Amplifier
• Input Over/Undervoltage Lockout (OVLO/UVLO)
• Output Overvoltage Protection (OVP)
• Overtemperature Protection (OTP)
• Fast and slow current limits
• -40°C to 115°C operating range (TJ)
• Excellent light load efficiency
• Optional I2C functionality & programmability: n VOUT margining n Fault reporting n Enable and SYNCI pin polarity

Applications

• Computing, Communications, Industrial
• Variable output step up/down voltage regulation

Package Information

• 10mm x 14mm x 2.56mm LGA SiP SGND Vin Vin VOUT Vout PGND COMP ISP ISN IMON EAO Cin Cout PGND VS1 VS2 VSN VSP VDIFF EAIN SYNC I VDR EN SYNC O TRK PGD PI3749-00 Typical Application VIN (V) Efficiency (%) Efficiency Power Dissipation Power Dissipation (W) 15 20 25 30 35 1.5 2.5 3.5 4.5

Cool-Power® Rev 1.5 vicorpower.com Page 3 of 26 04/2016 800 927.9474 PI3749-x0 Order Information Absolute Maximum Ratings Note: Stresses beyond these limits may cause permanent damage to the device. Operation at these conditions or conditions beyond those listed in the Electrical Specifications table is not guaranteed. All voltage nodes are referenced to PGND unless otherwise noted. [1] Non-Operating Test Mode Limits. [2] The ISP pin to ISN pin has a maximum differential limit of +5.5VDC and -0.5VDC. Part Number Description Package Transport Media MFG PI3749-00-LGIZ 16VIN to 34VIN SiP 10mm x 14mm 108-pin LGA TRAY Picor PI3749-20-LGIZ 16VIN to 34VIN SiP I2C compatible 10mm x 14mm 108-pin LGA TRAY Picor Location Name VMAX VMIN ISOURCE ISINK 1-2,G-K VIN 36V -0.3V 40A[1] 40A[1] 4-5,G-K VS1 36V -0.7 VDC 40A[1] 18A[1] 10-11,G-K VS2 36V -0.7 VDC 40A[1] 18A[1] 13-14,G-K VOUT 36V -0.7 VDC 40A[1] 40A[1] 1E VDR 5.5V -0.3V 30mA 200mA 1D PGD 5.5V -0.3V 20mA 20mA 1C SYNCO 5.5V -0.3V 5mA 5mA 1B SYNCI 5.5V -0.3V 5mA 5mA 1A ADR1 5.5V -0.3V 5mA 5mA 2A ADR0 5.5V -0.3V 5mA 5mA 3A SCL 5.5V -0.3V 5mA 5mA 4A SDA 5.5V -0.3V 10mA 10mA 5A EN 5.5V -0.3V 5mA 5mA 6A TRK 5.5V -0.3V 50mA 50mA 7A TEST5 5.5V -0.3V 5mA 5mA 8A COMP 5.5V -0.3V 5mA 5mA 9A VSN 5.5V -1.5V 5mA 5mA 10A VSP 5.5V -1.5V 5mA 5mA 11A VDIFF 5.5V -0.5V 5mA 5mA 12A EAIN 5.5V -0.3V 5mA 5mA 13A EAO 5.5V -0.3V 5mA 5mA 14A IMON 5.5V -0.3V 5mA 5mA 14D ISN[2] 40V -2 VDC 5mA 5mA 14E ISP[2] 40V -2 VDC 5mA 5mA 10-14,B + 10-12,C-E SGND 0.3V -0.3V 200mA 200mA 2-9,B-E + 7-8,F-K PGND N/A N/A 18A[1] 18A[1]

Cool-Power® Rev 1.5 vicorpower.com Page 4 of 26 04/2016 800 927.9474 PI3749-x0 Pin Description Pin Number Pin Name Description 1-2,G-K VIN Input voltage and sense node for UVLO, OVLO and feed forward compensation. 4-5,G-K VS1 Input side switching node and ZVS sense node for power switches. 10-11,G-K VS2 Output side switching node and ZVS sense node for power switches. 13-14,G-K VOUT Output voltage and sense node for power switches, VOUT feed forward compensation, VOUT_OV and internal signals. 1E VDR Internal 5.1V supply for gate drivers and internal logic; not for external use. 1D PGD Fault & Power Good indicator. PGD pulls low when the regulator is not operating or if EAIN is less than 1.4V. 1C SYNCO Synchronization output. Outputs a high signal for ½ of the programmed switching period at the beginning of each switching cycle, for synchronization of other regulators. 1B SYNCI Synchronization input. When a falling edge synchronization pulse is detected, the PI3749-x0 will delay the start of the next switching cycle until the next falling edge sync pulse arrives, up to a maximum delay of two times the programmed switching period. If the next pulse does not arrive within two times the programmed switching period, the controller will leave sync mode and start a switching cycle automatically. Connect to SGND when not in use. 1A ADR1 I2C Addressing Pin, for use with PI3749-20 only. No connect for the PI3749-00. 2A ADR0 I2C Addressing Pin, for use with PI3749-20 only. No connect for the PI3749-00. 3A SCL I2C Clock, for use with the PI3749-20 only. Connect to SGND for PI3749-00. 4A SDA I2C Clock, for use with the PI3749-20 only. Connect to SGND for PI3749-00. 5A EN Regulator Enable control. Asserted high or left floating = regulator enabled; Asserted low, regulator output disabled. 6A TRK Soft-start and track input. An external capacitor may be connected between TRK pin and SGND to decrease the rate of output rise during soft-start. 7A TEST5 For factory use only. Connect to SGND in application. 8A COMP Error amp compensation dominant pole. Connect a capacitor between COMP and SGND to set the control loop dominant pole. 9A VSN General purpose amplifier inverting input 10A VSP General purpose amplifier non-inverting input 11A VDIFF General Purpose amplifier output. When unused connect VDIFF to VSN and VSP to SGND. 12A EAIN Error amplifier inverting input and sense for PGD. Connect by resistive divider to the output. 13A EAO Transconductance error amplifier output, PWM input and external connection for load sharing. Connect a capacitor between EAO and SGND to set the control loop high frequency pole. 14A IMON High side current sense amplifier output 14D ISN High side current sense amplifier negative input 14E ISP High side current sense amplifier positive input 10-14,B + 10-12,C-E SGND Signal ground. Internal logic and analog ground for the regulator. SGND and PGND are star connected within the regulator package. 2-9,B-E + 7-8,F-K PGND Power ground. VIN, VOUT, VS1 and VS2 power returns. SGND and PGND are star connected within the regulator package.

Cool-Power® Rev 1.5 vicorpower.com Page 5 of 26 04/2016 800 927.9474 PI3749-x0 Large Pin Blocks Pin Block Name Group of pins VIN K1-2, J1-2, H1-2, G1-2 VS2 K10-11, J10-11, H10-11, G10-11 VOUT K13-14, J13-14, H13-14, G13-14 SGND E10-12, D10-12, C10-12, B10-14 PACKAGE TOP VIEW Exposed Copper Solder Mask Over Copper Solder Mask Over Board A B C D E F G H J K 12 34 56 78 91 01 11 21 31 4 VINV S1 PGND VS2V OUT VDR PGD SYNCO SYNCI ADDR1 ADDR0 SCL SDA EN TRK COMP VSN VSP VDIFF EAIN EAO IMON ISP ISN SGND TEST5 Package Pin-Out

Cool-Power® Rev 1.5 vicorpower.com Page 6 of 26 04/2016 800 927.9474 PI3749-x0 Block Diagram Storage and Handling Information Maximum Storage Temperature Range -65°C to 150°C Maximum Operating Junction Temperature Range -40°C to 115°C Soldering Temperature for 20 seconds 245°C MSL Rating 3 ESD Rating [3] 500V HBM; 1.0kV CDM VIN SGND ZVS Buck Boost Control and Digital Parametric Trim VDR SYNCO SYNCI PGD EN FT1 - FT5 PGND 0 Ω LDO VS1 VS2 VS1V S2 VOUT ISP ISN IMON VSN VSP VDIFF EAIN EAO COMP TRK VREF CLAMP SCL* SDA* ADR1* ADR0* *Simplified Block Diagram (I2C pins SCL, SDA, ADRO, ADR1, only active for PI3749-20 device version) [3] JESD22-C101F, JESD22-A114F.

Cool-Power® Rev 1.5 vicorpower.com Page 7 of 26 04/2016 800 927.9474 PI3749-x0

Electrical Characteristics

Specifications apply for the conditions -40°C < TJ < 115°C, VIN = 16V - 34V, VOUT = 24V, LEXT = 480nH[4], external CIN = COUT = 20µF, unless otherwise noted. Parameter Symbol Conditions Min Typ Max Unit Input Specifications Input Voltage VIN_DC 16 24 34 V Input Current IIN_DC IOUT = 4A, VIN = 24V, VOUT = 24V, TCASE = 25°C 4.06 A Input Current IIN_DC IOUT = 7.0A, VIN = 16V, VOUT = 24V, TCASE = 25°C 10.8 A Input Current During Output Short (fault condition duty cycle) IIN_SHORT [5] 2.5 mA Input Quiescent Current IQ_VIN Enabled (no load) 6.6 mA Input Voltage Slew Rate VIN_SR [5] 1 V/µs Internal Input Capacitance CIN 50V, X7R type 25°C, VOUT = 0V 2 µF VIN UVLO threshold rising VIN_UVLO_START 13.0 14.1 15.0 V VIN UVLO hysteresis VIN_UVLO_HYS 0.7 V VIN OVLO threshold rising VIN_OVLO_START 35.2 37.4 39.5 V VIN OVLO hysteresis VIN_OVLO_HYS 0.75 V Output Specifications Output Voltage Range VOUT_DC VIN = 16V to 34V 12 29 V VIN = 24V to 34V 12 34 Output Current Steady State IOUT_DC VIN =24V, VOUT = 24V, TCASE = 25°C[6] 6.8 AVIN = 16V, VOUT = 24V, TCASE = 25°C[6] 7.2 VIN = 24V, VOUT = 12V, TCASE = 25°C[6] 10 Output Power Steady State POUT_DC VIN = 24V, VOUT = 24V, TCASE = 25°C[6] 163.2 WVIN = 16V, VOUT = 24V, TCASE = 25°C[6] 172.8 VIN = 24V, VOUT = 12V, TCASE = 25°C[6] 120 Output Ripple VOUT_AC IOUT = 4A, VIN = 24V, VOUT = 16V, Tcase = 25°C COUT_EX = 8 x 10µF, 50V, X7S, 20MHz BW 137 mVp-p Internal Output Capacitance COUT 50V, X7R type 25°C, VOUT = 0V 1 µF VOUT Over Voltage Threshold VOUT_OVT Rising VOUT threshold to detect open loop 35.2 37.4 39.5 V V drive VDR Internal drive supply, internal use only 4.84 5.10 5.36 V Current Sense Amplifier (Dedicated to monitor Input or Output current) ISP Pin Bias Current (Sink) VOUT = 10V, Flows to SGND 90 150 260 µA ISN Pin Bias Current VOUT = 10V 0 µA Common Mode Input Range 8 36 V IMON Source Current 1 1.8 3 mA IMON Sink Current 1 1.6 2.6 mA IMON Output At No Load 0 10 mV Full Scale Error 40mV input -4 4 % Bandwidth [5] 40 kHz Settling Time For Full Scale Step 1% 20 µs Gain AV_CS 20 V/V

Cool-Power® Rev 1.5 vicorpower.com Page 8 of 26 04/2016 800 927.9474 PI3749-x0 Electrical Characteristics (Cont.) Specifications apply for the conditions -40°C < TJ < 115°C, VIN = 16V - 34V, VOUT = 24V, LEXT = 480nH[4], external CIN = COUT = 20µF, unless otherwise noted. Parameter Symbol Conditions Min Typ Max Unit General Purpose Amplifier Open Loop Gain [5] 96 120 140 dB Small Signal Gain-Bandwidth [5] 5 7 12 MHz Offset -1 0.2 1 mV Common Mode Input Range -0.1 2.5 V Differential Mode Input Range 2 V Maximum Output Voltage IDIFF = -1mA VDR - 0.2 V V Minimum Output Voltage No Load 20 mV Capacitive Load for Stable Oper- ation [5] 0 100 pF Slew Rate 10 V/µs Output Current -1 1 mA Transconductance Error Amplifier Reference VREF EAIN = EAO 1.667 1.7 1.734 V Input Range VEAIN Note VEAIN_OV below 0 VDR V Maximum Output Voltage 3.45 4.0 V Minimum Output Voltage 0 0.1 V Transconductance Factory Set 7.6 mS Zero Resistor Factory Set 7.0 kΩ EAO Output Current Sourcing VEAO = 50mV, VEAIN = 0V 400 µA EAO Output Current Sinking VEAO = 2V, VEAIN = 5V 400 µA Open Loop Gain ROUT > 1MΩ [5] 70 80 dB Control and Protection Switching Frequency FSW VIN = VOUT = 24V IOUT = 2A 800 kHz Switching Frequency FSW VIN = 16V, VOUT = 12V IOUT = 7A 480 kHz VEAO Pulse Skip Threshold VEAO_PST VEAO to SGND 0.6 V Control Node Range VRAMP 0 3.3 V VEAO Overload Threshold VEAO_OL VEAO to SGND 3.2 3.4 V Overload Timeout TOL VEAO > VEAO_OL 1 msec Vout Slow Current Limit VOUT_SCL 10µs time constant 18 A VEAIN Output Over Voltage Thresh- old VEAIN_OV VEAIN > VEAIN_OV 2.04 V Overtemperature Fault Threshold TOTP [5] 125 129 °C Overtemperature Restart Hysteresis TOPT_HYS [5] 30 °C

Cool-Power® Rev 1.5 vicorpower.com Page 9 of 26 04/2016 800 927.9474 PI3749-x0 Electrical Characteristics (Cont.) Specifications apply for the conditions -40°C < TJ < 115°C, VIN = 16V - 34V, VOUT = 24V, LEXT = 480nH[4], external CIN = COUT = 20µF, unless otherwise noted. Parameter Symbol Conditions Min Typ Max Unit Soft Start and Tracking Function TRK Active Range Nominal 0 1.7 V TRK Disable Threshold 20 40 70 mV TRK Internal Capacitance .047 µF Soft Start Charge Current 30 50 70 µA Soft Start Discharge Current VTRK = 0.5V 8.5 mA Soft Start Time tSS Ext CSS = 0µF 1.6 msec Enable Enable High Threshold ENIH 0.9 1 1.1 V Enable Low Threshold ENIL 0.7 0.8 0.9 V Enable Threshold Hysteresis ENHYS 100 200 300 mV Enable Pin Bias Current VEN = 0V or VEN = 2V -50 µA Enable Pull-up Voltage Floating 2.0 V Fault Restart Delay Time tFR_DLY 30 msec Digital Signals SYNCI Threshold Rising VDR = 5.1V 3.1 V SYNCI Threshold Falling VDR = 5.1V 2.2 V SYNCO High SYNCOOH VDR - 0.5 VDR V SYNCO Low SYNCOOL ISYNCOUT = 1mA 0.5 V PGD High Leakage PGDILH VPGD = VDR 10 µA PGD Output Low PGDOL IPGD = 4mA 0.4 V PGD EAIN Low Rise 1.41 1.45 1.48 V PGD EAIN Low Fall 1.36 1.41 1.46 V PGD EAIN Threshold Hysteresis 35 mV PGD EAIN High 1.94 2.04 2.14 V I2C Digital Signals (PI3749-20 only) I2C Address high threshold VADRx-HI 3.872 4.59 V I2C Address mid threshold VADRx-MID 1.452 3.752 V I2C Address low threshold VADRx-LOW 0.51 1.072 V I2C Address resistance, within mid thresholds RADRx-MID Resistance to 2.5V, when ADRx pin voltage within VADRx_MID 10 V I2C Address resistance, outside mid thresholds RADRx-MID Resistance to 2.5V, when ADRx pin voltage outside range of VADRx_MID 200 V SCL, SDA in high VSER_IH 2.1 V SCL, SDA in low VSER_IL 1.5 V SDA out low VSER_OL Sinking up to 3mA 0.4 V SCL, SDA pull-down current ISER_I Weak pull-down current to SGND 10 V [4] See Inductor Pairing section. [5] Assured to meet performance specification by design, test correlation, characterization, and/or statistical process control. [6] Output current capability varies with input & output voltage. See performance curves in figures 15 - 17.

Cool-Power® Rev 1.5 vicorpower.com Page 14 of 26 04/2016 800 927.9474 PI3749-x0 Figure 23 — PI3749-x0 calculated MTBF Telcordia SR-332 GB MTBF 100 1000 10000 -60 -40 -20 0 20 40 60 80 100 1201 40 MTBF (Mhrs) PI3749-00-LGIZ vs. Temperature, Assuming 50% Derating and GB Temperature (°C) MTBF Calculations Over Temperature Using Telcordia SR-332

Cool-Power® Rev 1.5 vicorpower.com Page 15 of 26 04/2016 800 927.9474 PI3749-x0 Functional Description The PI3749-x0 is part of a family of highly integrated ZVS Buck- Boost regulators. The PI3749-x0 has a variable output voltage that is set with a resistive divider. Performance and maximum output current are characterized with a specific external power inductor as defined in electrical specifications, with Inductor Pairing section. For basic operation, Figure 24 shows the minimum connections and components required. Enable The EN pin of the regulator is referenced to SGND and permits the user to turn the regulator on or off. The EN polarity is a positive logic assertion. If the EN pin is left floating or asserted high, the regulator output is enabled. Pulling the EN pin below 0.8VDC with respect to SGND will discharge the SS/TRK pin until the output reaches zero or the EN pin is released. Switching Frequency Synchronization The SYNCI input allows the user to synchronize the controller switching frequency to the falling edge of an external clock referenced to SGND. The external clock can synchronize the unit between 50% and 110% of the preset switching frequency (FSW). The SYNCI pin should be connected to SGND when not in use, and should never be left floating. Soft-Start and Tracking The PI3749-x0 provides a soft start and tracking feature using the TRK pin. Programmable Soft Start requires an external capacitor from the TRK pin to SGND in addition to the internal 47nF soft-start capacitor to set the start-up ramp period greater then tSS. The PI3749-x0 output will proportionately follow the TRK pin when it is below 1.7VDC. If the TRK pin is goes below the disable threshold, the regulator will finish the current switching cycle and then stop switching. Remote Sensing Differential Amplifier A general purpose operational amplifier is provided to assist with differential remote sensing and or level shifting of the output voltage. The VDIFF pin can be connected to the transconductance error amplifier input EAIN pin, or with proper configuration can also be connected to the EAO pin to drive the modulator directly. Power Good The PI3749-x0 PGD pin functions as a power good indicator and pulls low when the regulator is not operating or if EAIN is less than 1.4V. Output Current Limit Protection PI3749-x0 has three methods implemented to protect from output short circuit or over current condition. Slow Current Limit protection: prevents the output load from sourcing current higher than the maximum rated regulator current. If the output current exceeds the Vout Slow Current Limit (VOUT_SCL) a slow current limit fault is initiated and the regulator is shutdown which eliminates output current flow. After Fault Restart Delay (tFR_DLY ), a soft-start cycle is initiated. This restart cycle will be repeated indefinitely until the excessive load is removed. Fast Current Limit protection: monitors the regulator inductor current pulse-by-pulse to prevent the output from supplying very high current. If the regulator senses a high inductor current pulse, it will initiate a fault and stop switching. After Fault Restart Delay (tFR_DLY ), a soft-start cycle is initiated. This restart cycle will be repeated indefinitely until the excessive load is removed. Overload Timeout protection: If the regulator is providing maximum output power for longer than the Overload Timeout delay (TOL), it will initiate a fault and stop switching. After Fault Restart Delay (tFR_DLY ), a soft-start cycle is initiated. This restart cycle will be repeated indefinitely until the overload load is removed. Input Undervoltage Lockout If VIN falls below the input Under Voltage Lockout (UVLO) threshold, the PI3749-x0 will complete the current cycle and stop switching. The system will restart once the input voltage is reestablished and after the Fault Restart Delay. Input Overvoltage Lockout If VIN rises above the input Overvoltage Lockout (OVLO) threshold, the PI3749-x0 will complete the current cycle and stop switching. The system will restart once the input voltage is reestablished and after the Fault Restart Delay. Output Overvoltage Protection The PI3749-x0 family is equipped with two methods of detecting an output overvoltage condition. Output Overvoltage Protection (OVP) to prevent damage to input voltage sensitive devices. If the output voltage exceeds 20% of its set regulated value as measured by the EAIN pin (V EAIN_OV ), the regulator will complete the current cycle, stop switching and issue an OVP fault. Also if the output voltage of the regulator exceeds the VOUT Overvoltage Threshold (VOUT_OVT ) then the regulator will complete the current cycle, stop switching and issue an OVP fault. The system will resume operation once the output voltage falls below the OVP threshold and after Fault Restart Delay. SGND Vin Vin VOUT Vout PGND COMP ISP ISN IMON EAO Cin Cout PGND VS1 VS2 VSN VSP VDIFF EAIN SYNC I VDR EN SYNC O TRK PGD PI3749-00 Figure 24 — ZVS Buck-Boost with required components

Cool-Power® Rev 1.5 vicorpower.com Page 16 of 26 04/2016 800 927.9474 PI3749-x0 Overtemperature Protection The internal package temperature is monitored to prevent internal components from reaching their thermal maximum. If the Overtemperature Protection threshold is exceeded (TOTP), the regulator will complete the current switching cycle, enter a low power mode, set a fault flag, and will soft-start when the internal temperature decreases by more than the Overtemperature Restart Hysteresis (T OTP_HYS). Pulse Skip Mode (PSM) PI3749-x0 features a hysteretic Pulse Skip Mode to achieve high efficiency at light loads. The regulator is setup to skip pulses if VEAO falls below the Pulse Skip Threshold (VEAO_PST ). Depending on conditions and component values, this may result in single pulses or several consecutive pulses followed by skipped pulses. Skipping cycles significantly reduces gate drive power and improves light load efficiency. The regulator will leave Pulse Skip Mode once the control node rises above the Pulse Skip Mode threshold (VEAO_PST ). Variable Frequency Operation The PI3749-x0 is preprogrammed to a fixed, maximum, base operating frequency. The frequency is selected with respect to the required power stage inductor to operate at peak efficiency across line and load variations. The switching frequency period will stretch as needed during each cycle to accommodate low line and or high load conditions. By stretching the switching frequency period, thus decreasing the switching frequency, the ZVS operation is preserved throughout the input line voltage range maintaining optimum efficiency. IMON Amplifier The PI3749-x0 provides a differential amplifier with a level shifted, SGND referenced output, the IMON Pin, which is useful for sensing input or output current on high voltage rails. A fixed gain of 20:1 is provided over a large common mode range. When using the amplifier, the ISN pin must be referenced to the common mode voltage of the ISP pin for proper operation. See Absolute Maximum Ratings for more information. If not in use, the ISN and ISP pins should be connected to SGND and the IMON pin left floating. I2C Interface Operation PI3749-20 devices provide an I2C digital interface that enables the user to: Device Configuration Options: n Dynamic VOUT margining n Programmable Sync Phase Delay Fault telemetry including: n Input and Output Overvoltage n Input and Output Undervoltage n Internal Bias Supply Undervoltage n Overtemperature Protection n Multi Tiered Current Limit reporting

Cool-Power® Rev 1.5 vicorpower.com Page 18 of 26 04/2016 800 927.9474 PI3749-x0 number of ceramic capacitors used to calculate the individual capacitor’s RMS current. Table 2 includes the recommended input and output ceramic capacitor. It is very important to verify that the voltage supply source as well as the interconnecting line are stable and do not oscillate. Input Filter case 1; Inductive source and local, external, input decoupling capacitance with negligible ESR (i.e.: ceramic type) The voltage source impedance can be modeled as a series Rline Lline circuit. The high performance ceramic decoupling capacitors will not significantly damp the network because of their low ESR; therefore in order to guarantee stability the following conditions must be verified: Where, rEQ_IN can be calculated by dividing the lowest line voltage by the full load input current. It is critical that the line source impedance be at least an octave lower than the converter’s dynamic input resistance, Equation (4). However, Rline cannot be made arbitrarily low otherwise Equation (3) is violated and the system will show instability, due to under- damped RLC input network. Input Filter case 2; Inductive source and local, external input decoupling capacitance with significant RCIN_EXT ESR (i.e.: electrolytic type) In order to simplify the analysis in this case, the voltage source impedance can be modeled as a simple inductor L line. Notice that, the high performance ceramic capacitors CIN_INT within the PI3749-x0 should be included in the external electrolytic capacitance value for this purpose. The stability criteria will be: Equation (6) shows that if the aggregate ESR is too small – for example by using very high quality input capacitors (CIN_EXT ) – the system will be under-damped and may even become destabilized. Again, an octave of design margin in satisfying Equation (5) should be considered the minimum. Note: When applying an electrolytic capacitor for input filter damping the ESR value must be chosen to avoid loss of converter efficiency and excessive power dissipation in the electrolytic capacitor. Parallel Operation PI3749-x0 can be connected in parallel up to two phases, with interleaving. Parallel interleaved modules can be used to increase the output current capability of a single power rail and reduce output voltage ripple. Figure 27 shows the proper connection of two regulators in parallel interleaved operation. Connecting a higher number of modules (up to six maximum) is possible without interleaving or synchronization. Connecting groups of interleaved modules would be the best configuration for applications requiring higher current than two modules can produce. The user must consider a worst case sharing error of +/-10% when considering a two unit parallel system to avoid overloading one module or tripping current limit during load transients. By connecting the EAO pins and SGND pins of each module together, the regulators will share the output current equally, provided each power inductor is the same value and the output ripple is not excessive. Connecting all TRK pins will force all units to track each other during soft-start. Additionally, all units EN pins must be released to allow the units to start (See Figure 27). To provide synchronization between regulators over the entire operational frequency range, the Power Good (PGD) pin must be connected to the lead regulator’s (#1) SYNCI pin and a 2.5kΩ Resistor, R1, must be placed between SYNCO (#2) return and the lead regulator’s SYNCI (#1) pin, as shown in Figure 27. In this configuration, at system soft-start, the PGD pin pulls SYNCI low forcing the lead regulator to initialize the open-loop startup synchronization. Once the regulators reach regulation, SYNCI is released and the system is now synchronized in a closed- loop configuration which allows the system to maintain correct synchronization when any of the individual regulators begin to enter variable frequency mode. Any fault event flagged by one regulator will disable the other regulators. The regulators will not be synchronized during a fault or during startup (resulting in higher output ripple for that period of time) until the PGD pin is released. Rline > Lline CIN_INT + CIN_EXT • rEQ_IN (3) ( ) Rline << rEQ_IN (4) rEQ_IN > RCIN_EXT (5) Lline CIN_INT • RCIN_EXT (6)< rEQ_IN SGND Vin Vin Vout Vout PGND EAIN TRK EAO PI3749-x0 (#1) Cin Cout SGND Vin Vout PGND EAIN PI3749-x0 (#2) Cout EN EAO( #2) TRK(#2) EN(#2) Vin Cin PGD SYNCI SYNCOSYNCI(#2) SYNCO (#2) TRK EAO EN EAO(#1) TRK (#1) EN(#1) PGD SYNCI SYNCOSYNCI(#1) SYNCO(#1) VS1 VS2 VS1 VS2 Figure 27 — PI3749-x0 parallel operation

Cool-Power® Rev 1.5 vicorpower.com Page 19 of 26 04/2016 800 927.9474 PI3749-x0 VOUT (V) VIN (V) ILOAD (A) CINPUT (see table 2) COUTPUT (see table 2) CINPUT Ripple Current (IRMS) COUTPUT Ripple Current (IRMS) Output Ripple (mVpp) Input Ripple (mVpp) 12 16

6 X 10µF 8 X 10µF

3.55 3.65 37.1 67.5 7 4.59 4.89 60.6 113 12 20 4.45 4.43 44 84.3 9 6.08 6.32 80.5 162 12 24 4.68 4.36 40.2 81 10 6.93 6.84 88 184 12 28 5.06 4.34 43.4 90.1 11 7.66 7.21 95 217 12 34 5.78 4.64 50 125 11 7.8 6.76 87 240 24 16 5.13 4.49 75.4 63.5 7 7.08 6.07 138 114 24 20 4.28 3.91 61.6 56 7 5.3 4.6 85 75 24 24 4.24 4.13 64 82 7 4.7 4.5 68 88 24 28 4.55 4.4 68 105 7 5.1 5.1 74 121 24 34 5.1 4.66 72.5 142 7 5.93 5.67 83 176 28 16 7.18 6.5 143.5 108 9 10.62 9.37 301 223 28 20 5.09 4.65 84 70 7 6.49 5.51 122 95 28 24 4.68 4.46 82 83 6 5.06 4.68 87 83.5 28 28 4.66 4.54 83 107.5 7 5.31 5.16 93 119 28 34 4.5 4.18 77.4 130.6 6 5.49 5.26 95 168 34 24 5.6 5.39 124 95 7 6.66 5.76 148 100 34 29 4.5 4.5 107 107 6 5.6 5.33 133 122 34 34 3.87 3.7 90.4 118 5 5.12 4.95 124 160 Table 1 — Recommended input and output capacitance Part Number Description MFG Description C3225X7S1H106M250AB 10µF Capacitor, X7S 20% 50V, 1210 TDK Table 2 — Capacitor manufacturer part numbers

Cool-Power® Rev 1.5 vicorpower.com Page 20 of 26 04/2016 800 927.9474 PI3749-x0 Figure 28 — Data transfer on the I2C bus I2C Addressing The PI3749-20 is hardware compatible with the NXP I2C Bus Specification Version 2.1, January 2000, in Standard Mode (100kHz) for all bus timing and voltage levels up to 5.5V. It operates as a slave on the I2C bus. The PI3749-20 I2C interface responds to the address programmed by the two I2C Address pins, ADR1 and ADR0. The address pins are three level inputs, providing nine possible combination pairs, although only eight of these combinations are unique, as shown in table 3. Considering only the 7 bit address sub-field, the high-order address bits <6> through <4> are hardcoded to 4’b1001, while the lower order address bits <3> through <0> are modified by the ADRx pins. Note that the state of the ADRx pins is resolved on each I2C address transfer. Therefore the PI3749-20 address can be changed while the regulator is powered up and in operation. I2C Command Structure Depending on the state of the read/write bit, two types of transfers are possible: a. Write: Data transferred from the I2C master to the PI3749-20 slave The first byte is transmitted by the master and includes the slave address and the R/W bit set to write (as shown in the last column of table 3.) The second byte is also transmitted by the master and is the write data. The slave responds between each byte with an acknowledge bit. b. Read: Data returned from the PI3749-20 slave to the master The first byte is transmitted by the master and includes the slave address but the R/W bit is set to read. The slave responds to the first byte (the address transmitted by the master) with an acknowledge bit. The second byte is transmitted by the slave back to the master and is the read data. The master responds after the read data byte with a not-acknowledge bit (since the PI3749-20 read data are all single byte registers). Per the I2C standard, the master generates all serial clock pulses, and all data is transferred MSB first. ADDRx state Resultant I2C address sub-field Sub-field bit positions <7.1> Fully formed address write word (including lsb of the transfer set for a write) ADR1 ADR0 Hexadecimal Decimal Binary Binary L L 7’h48 72 7’b100_1000 8’b1001_0001 L M 7’h49 73 7’b100_1001 8’b1001_0011 L H 7’h4A 74 7’b100_1010 8’b1001_0101 M L 7’h4B 75 7’b100_1011 8’b1001_0111 M M 7’h4C 76 7’b100_1100 8’b1001_1001 M H 7’h4D 77 7’b100_1101 8’b1001_1011 H L 7’h4E 78 7’b100_1110 8’b1001_1101 H M 7’h4F 79 7’b100_1111 8’b1001_1111 H H 7’h4F 79 7’b100_1111 8’b1001_1111 Table 3 — I2C Address selection

Cool-Power® Rev 1.5 vicorpower.com Page 21 of 26 04/2016 800 927.9474 PI3749-x0 I2C Parameter Readback Fault Monitoring The fault bits in the FLT2 and FLT3 registers are only latched when the regulator first stops operating due to a given fault type. If the regulator is already not operating (perhaps due to a fault protection or being disabled) then should a new fault condition occur, the fault bit associated with the new fault will not be registered. Both versions of the PI3749-x0 will auto recover from any fault protection mechanism, once the fault is corrected. However in order to aid in monitoring of the regulator via the I2C fault monitoring registers, when a fault occurs, the associated fault bit(s) will set and latch until they are explicitly cleared by the I2C host using the FLTREG_CLR register. A write to the FLTREG_CLR register address will clear all latched fault register bits. I2C Volatile Addresses for Parameter Programming Register Name Register FLT2 2 TRISE OTP VOUT_NEG VOUT_OV EAIN_HI VIN_OV VIN_UV VCC_UV FLT3 3 0 0 0 0 Q1_FIL Q3_SIL Q3_FIL SLOW_IL FLTREG_CLR 4 Write only, data ignored Table 4 — PI3749-20 Fault Readback/Clear Registers Fault Bit Name Fault Bit Location Fault Destination TRISE FLT2, Bit<7> Overtemperature Protection: The predicted maximum hot-spot temperature, based on measured temperature and loading, exceeded the maximum safe operating temperature. OTP FLT2, Bit<6> Overtemperature Protection: The internal measured temperature exceeded the maximum safe operating temperature. VOUT_NEG FLT2, Bit<5> VOUT negative fault. The output voltage was below ground. VOUT_OV FLT2, Bit<4> Output Overvoltage protection. EAIN_HI FLT2, Bit<3> Current Limit: Overload Timeout. VIN_OV FLT2, Bit<2> Input Overvoltage Lockout. VIN_UV FLT2, Bit<1> Input Undervoltage Lockout. VCC_UV FLT2, Bit<0> VCC undervoltage. The internal bias supply faulted due to undervoltage. Q1_FIL FLT3, Bit<3> Current Limit: Fast current limit (Q1) The peak current through Q1 and the inductor was higher than the maximum current allowed. Q3_SIL FLT3, Bit<2> Current Limit: Slow current limit (Q3) Q3_FIL FLT3, Bit<1> Current Limit: Fast current limit (Q3) The peak current through Q3 and the inductor was higher than the maximum current allowed. SLOW_IL FLT3, Bit<0> Current Limit: Slow current limit. Register Name Register Address Readback MRGN 5 Yes MRGN_ENA MRGN<2> MRGN<1> MRGN<0> Table 6 — PI3749-20 Parameter Programming Volatile Registers Table 5 — Fault register bit summary

Cool-Power® Rev 1.5 vicorpower.com Page 22 of 26 04/2016 800 927.9474 PI3749-x0 MRGN: Margin Control By default, output voltage margining is disabled, corresponding to B3 being cleared. In this case, the reference to the error amplifier is at its nominal value of 1.700V. When margining is enabled, the reference can be modified in 85 mV steps according to Table 7. The MRGN state is always controlled by four bit wide volatile register. At power up, the register always resets to 4’b0000. The MRGN address can be freely read and written, as there are no one-time programmable fuses involved. MRGN state MRGN data Resultant Margin Function MRGN_ENA<3> MRGN<2..0> Margin active? Reference Voltage (V) 1 100 Yes 1.360 1 101 Yes 1.445 1 110 Yes 1.530 1 111 Yes 1.615 0 xxx No (data ignored), default 1.700 1 000 Yes 1.785 1 001 Yes 1.870 1 010 Yes 1.955 1 011 Yes 2.040 Table 7 — Margin control register programming

Cool-Power® Rev 1.5 vicorpower.com Page 23 of 26 04/2016 800 927.9474 PI3749-x0 PACKAGE BOTTOM VIEW PACKAGE TOP VIEW PACKAGE SIDE VIEW DETAIL A DETAIL B NOTES ‘e’ REPRESENTS THE BASIC TERMINAL PITCH. SPECIFIES THE TRUE GEOMETRIC POSITION OF THE TERMINAL AXIS. DIMENSION ‘b’ APPLIES TO METALLIZED PAD OPENING. DIMENSION ‘A’ INCLUDES PACKAGE WARPAGE. EXPOSED METALLIZED PADS ARE CU PADS WITH SURFACE FINISH PROTECTION. ALL DIMENSIONS IN MILLIMETERS. D E PIN 1 INDEX PAD OPENING b L PIN 1 INDEXD1 e SEE NOTES SEE NOTES DATUM B DATUM A DETAIL A MOLD CAP SUBSTRATE DETAIL B A SEATING PLANE PAD OPENING SOLDER MASK B A aaa C C aaa C bbb C// ddd CM BA Ceee M ddd CM BA Ceee M b L e SEE NOTES1 DIMENSIONS

14.00 BSC

10.00 BSC

13.00 BSC

9.00 BSC

1.00 BSC

2.63 0.04 2.59 0.60 0.60 0.275 0.10 0.10 0.08 0.10 0.08 SYMBOL A b L D E e aaa bbb ccc ddd eee NOM 2.56 0.55 0.55 0.225 MIN 2.49 0.50 0.50 0.175 Package Drawings

Cool-Power® Rev 1.5 vicorpower.com Page 24 of 26 04/2016 800 927.9474 PI3749-x0 PACKAGE PCB FOOTPRINT TOP VIEW PIN 1A INDEX D1 1mm DATUM B DATUM A DETAIL B 1mm Exposed Copper Solder Mask Over Copper Solder Mask Over Board DETAIL A Thermal Vias DETAIL B 0.55 mm (S MD ) Pa ck ag e Ou t lin e 0.55 mm (S MD ) 0.65 mm (C u Pa d) 0.65 mm (C uP ad ) 0.35 mm DE TA IL A 0.55 mm (S MD ) 0.55 mm (S MD ) Pa ck ag e Ou t lin e 0.55 mm (S MD ) 0.65 mm (C u Pa d) 0.65 mm (C u Pa d) ≥0.5mm 0.55 mm (S MD ) 0.55 mm (S MD ) 0.55 mm (S MD ) SM D = So ld er ma sk De fin ed Pa ds ≥0.5 mm ≥0.5 mm ≥0.5 mm Receiving PCB Pattern Design Recommendations

Cool-Power® Rev 1.5 vicorpower.com Page 25 of 26 04/2016 800 927.9474 PI3749-x0

Revision History

Revision Date Description Page Number(s) 1.0 04/13/15 Initial Release n/a 1.1 07/14/15 Updated conditions column Added additional specifications Clarified parameters and updated typical Corrected labels Corrected labels Inductor Pairing updated 1.2 08/03/15 Inductor value corrected 7-9 1.3 09/03/15 Added I2C capability throughout all 1.4 10/??/15 Added documentation for I2C capability Changed frequency units for readability Reformatted for readability 1.5 04/??/15 Updated VDIFF description 4

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