PI3323-00

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ZVS Regulators Rev 1.6 Page 1 of 36 02/2021 14 – 42VIN ZVS Buck Regulator ZVS Regulators PI332x-00 Note: Product images may not highlight current product markings. Product Description The PI332x-00 is a family of high-input-voltage, wide-input-range DC-DC ZVS Buck regulators integrating controller, power switches and support components all within a high -density System-in-Package (SiP). The integration of a high-performance Zero-Voltage Switching (ZVS) topology, within the PI332x-00 series, increases point -of-load performance providing best-in-class power efficiency. The PI332x-00 requires only an external inductor, two voltage selection resistors and minimal capacitors to form a complete DC-DC switch-mode buck regulator. Features & Benefits

• High‑Efficiency HV ZVS Buck Topology
• Wide input voltage range of 14 – 42V
• Power‑up into pre‑biased load
• Parallel capable with single‑wire current sharing
• Input Over/Undervoltage Lockout (OVLO/UVLO)
• Output Overvoltage Protection (OVP)
• Overtemperature Protection (OTP)
• Fast and slow current limits
• Differential amplifier for output remote sensing
• User‑adjustable soft start & tracking
• –40 to 120°C operating range (TINT), ‑LGIZ, ‑BGIZ models
• –55 to 120°C operating range (TINT), ‑LGMZ, ‑BGMZ, ‑BGMP models

Applications

• HV to PoL Buck Regulator Applications
• Computing, Communications, Industrial, Automotive Equipment

Package Information

• 10 x 14 x 2.56mm LGA SiP
• 10.5 x 14.5 x 3.05mm BGA SiP Device Output Voltage IOUT Max Set Range PI3323-00 3.3V 2.2 – 4.0V 22A PI3325-00 5.0V 4.0 – 6.5V 20A

ZVS Regulators Rev 1.6 Page 3 of 36 02/2021 PI332x-00 Order Information Thermal, Storage and Handling Information Name Rating Storage Temperature –65 to 150°C Internal Operating Temperature -LGIZ, BGIZ –40 to 120°C -LGMZ, -BGMZ, -BGMP –55 to 120°C Soldering Temperature for 20 seconds 245°C MSL Rating 3 ESD Rating, JESD22-A114F, JESD22-C101F 2kV HBM; 1kV CDM, respectively Product Nominal Output Voltage Rated Output Current Temperature Range Package Transport Media PI3323-00-BGIZ 3.3V 22A –40 to 120°C 10.5 x 14.5mm BGA TRAY PI3323-00-BGMZ –55 to 120°CPI3323-00-BGMP 10.5 x 14.5mm lead-solder BGA PI3323-00-LGMZ 10 x 14mm LGA PI3325-00-BGIZ 5.0V 20A –40 to 120°C 10.5 x 14.5mm BGA PI3325-00-BGMZ –55 to 120°C PI3325-00-BGMP 10.5 x 14.5mm lead-solder BGA PI3325-00-LGIZ –40 to 120°C 10 x 14mm LGA PI3325-00-LGMZ –55 to 120°C Absolute Maximum Ratings Notes: Stresses beyond these limits may cause permanent damage to the device. Operation at these conditions or conditions beyond those listed in the Electrical Specifications table is not guaranteed. All voltages are referenced to PGND unless otherwise noted. Name Rating VIN –0.7 to 55V VS1 –0.7VDC to 55V VOUT –0.5 to 25V SGND ±100mA TRK –0.3 to 5.5V, ±30mA VDR, SYNCI, SYNCO, PWRGD, EN, COMP , EAO, EAIN, VDIFF, VSN, VSP , TESTx –0.3 to 5.5V, ±5mA

ZVS Regulators Rev 1.6 Page 4 of 36 02/2021 PI332x-00 Functional Block Diagram VIN PGND SGND SYNCO PWRGD Q1 Q2 VCC EN SYNCI TRK EAO EAIN Power Control VDR ZVS Control Digital Parametric Trim VREF CHF CEAIN-INT COMP VSP+ - VSN VDIFF VS1 VOUT TESTx RZI Simplified block diagram

ZVS Regulators Rev 1.6 Page 5 of 36 02/2021 PI332x-00 Pin Description Name Location I/O Description VS1 Block 1 Power Switching Node: and ZVS sense for power switches. VIN Block 3 Power Input Voltage: and sense for UVLO, OVLO and feed forward ramp. VDR 5K I/O Gate Driver VCC: Internally generated 5.1V. May be used as a bias supply for low power external loads. See Application Description for important considerations. SYNCI 4K I Synchronization Input: Synchronize to the falling edge of external clock frequency. SYNCI is a high impedance digital input node and should always be connected to SGND when not in use. The PI332x-00 family is not optimized for external synchronization functionality. Refer to Application Description of Parallel Operation for details. SYNCO 3K O Synchronization Output: Outputs a high signal at the start of each clock cycle for the longer of ½ of the minimum period or the on time of the high-side power MOSFET. TEST1 2K I/O Test Connections: Use only with factory guidance. Connect to SGND for proper operation. TEST2 1K I/O Test Connections: Use only with factory guidance. Connect to SGND for proper operation. TEST3 1J I/O Test Connections: Use only with factory guidance. Connect to SGND for proper operation. TEST4 1H I/O Test Connections: Use only with factory guidance. Connect to SGND for proper operation. TEST5 1E I/O Test Connections: Use only with factory guidance. Connect to SGND for proper operation. PWRGD 1G O Power Good: High impedance when regulator is operating and VOUT is in regulation. Otherwise pulls to SGND. EN 1F I/O Enable Input: Regulator enable control. When asserted active or left floating: regulator is enabled. Otherwise regulator is disabled. SGND Block 5 Signal Ground: Internal logic ground for EA, TRK, SYNCI, SYNCO communication returns. SGND and PGND are star connected within the regulator package. TRK 1C I Soft Start and Track Input: An external capacitor may be connected between TRK pin and SGND to increase the rise time of the internal reference during soft start. COMP 1B O Compensation Capacitor: Connect capacitor for control loop dominant pole. See Error Amplifier section for details. A default CCOMP of 4.7nF is used in the example. EAO 1A O Error Amp Output: External connection for additional compensation and current sharing. EAIN 2A I Error Amp Inverting Input: Connection for the main Vout feedback divider tap VDIFF 3A O Independent Amplifier Output: Active only when module is enabled. VSN 4A I Independent Amplifier Inverting Input: If unused connect in unity gain. VSP 5A I Independent Amplifier Non-Inverting Input: If unused connect to SGND. VOUT 6A,B Power Direct VOUT Connect: for per-cycle internal clamp node and feed-forward ramp. PGND Block2 Power Power Ground: VIN and VOUT power returns.

ZVS Regulators Rev 1.6 Page 6 of 36 02/2021 PI332x-00 VIN VINVINVINVINVINVINVINVINVIN VINVINVINVINVINVINVINVINVIN VINVINVINVINVINVINVINVINVIN VIN VIN PGND PGNDPGNDPGNDPGNDPGNDPGNDPGNDPGNDPGND VS1 VS1VS1VS1VS1VS1VS1VS1VS1VS1 PGND PGND PGND PGND PGND SYNC0 TEST5 EN SGND PGND PGND PGND PGND SYNC1PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGNDVOUT TEST2 SGND SGND SGND SGND SGND SGND SGND VOUT VDR TEST1 TEST3TEST4PWRG0 SGND SGNDEA0 EAIN VDIFF VSN VSP TRKCOMP1 Package Pinout Pin Block Name Group of pins VS1 A14, B14, C14, D14, E14, F14, G14, H14, J14, K14 PGND A12, B12, C12, D12, E12, F12, G12, H12, J12, K12 VOUT A6, B6 SGND B2-4, C2-3, D1-3, E2-3 10x14mm SiP

ZVS Regulators Rev 1.6 Page 7 of 36 02/2021 PI332x-00 PI332x-00 Common Electrical Characteristics Specifications apply for –40°C < TINT < 120°C for -LGIZ, -BGIZ, –55°C < TJ < 115°C for -LGMZ, -BGMZ, -BGMP , VIN = 24V, EN = High, unless otherwise noted. [a] All parameters reflect regulator and inductor system performance. Measurements were made using a standard PI332x evaluation board with 3 x 3” dimensions and four-layer, 2oz copper. Refer to inductor pairing table within Application Description section for specific inductor manufacturer and value. [b] Regulator is assured to meet performance specifications by design, test correlation, characterization, and/or statistical process control. Output voltage is determined by an external feedback divider ratio. [c] Output current capability may be limited and other performance may vary from noted electrical characteristics when VOUT is not set to nominal. [d] Refer to Output Ripple plots. [e] Refer to Load Current vs. Ambient Temperature curves. [f] Refer to Switching Frequency vs. Load current curves. Parameter Symbol Conditions Min Typ Max Unit Differential Amp Open Loop Gain [b] 96 120 140 dB Small Signal Gain-Bandwidth [b] 5 7 12 MHz Input Offset 0.5 1 mV Common Mode Input Range –0.1 2.5 V Differential Mode Input Range 2 V Input Bias Current –1 1 µA Output Current –1 1 mA Maximum VOUT IVDIFF = –1mA 4.85 V Minimum VOUT IVDIFF = –1mA 20 mV Capacitive Load Range for Stability [b] 0 50 pF Slew Rate 11 V/µs PWRGD VOUT Rising Threshold VPG_HI% 78 84 90 % VOUT_DC VOUT Falling Threshold VPG_LO% 75 81 87 % VOUT_DC PWRGD Output Low VPG_SAT Sink = 4mA 0.4 V VDR Voltage Setpoint VVDR VIN_DC > 10V 4.9 5.05 5.2 V External Loading IVDR See Application Description for details 0 2 mA Enable High Threshold VEN_HI 0.9 1.0 1.1 V Low Threshold VEN_LO 0.7 0.8 0.9 V Threshold Hysteresis VEN_HYS 100 200 300 mV Pull Up Voltage Level for Source Current VEN_PU 2 V Pull Up Current IEN_PU_POS VIN > 8V, excluding tFR_DLY 50 µA Reliability MTBF MIL-HDBK-217, 25°C, Ground Benign: GB 14.6 MHrs Telcordia SR-332, 25°C, Ground Benign: GB 201 MHrs

ZVS Regulators Rev 1.6 Page 8 of 36 02/2021 PI332x-00 PI3323-00 (3.3VOUT) Electrical Characteristics Specifications apply for –40°C < TINT < 120°C for -LGIZ, -BGIZ, –55°C < TJ < 115°C for -LGMZ, -BGMZ, -BGMP , VIN = 24V, EN = High, unless otherwise noted. Parameter Symbol Conditions Min Typ Max Unit Input Specifications Input Voltage VIN_DC 14 24 42 V Input Current IIN_DC VIN = 24V, TCASE = 25°C, IOUT = 22A 3.35 A Input Current At Output Short (Fault Condition Duty Cycle) IIN_Short Short at terminals 5 mA Input Quiescent Current IQ_VIN Disabled 0.94 1.6 mA Input Quiescent Current IQ_VIN Enabled, no load, TCASE = 25°C 3.2 mA Input Voltage Slew Rate VIN_SR [b] 1 V/µs Input capacitance, Internal CIN_INT Effective value VIN = 24V, 25°C 0.7 µF Output Specifications EAIN Voltage Total Regulation VEAIN [b] 0.975 0.990 1.005 V Output Voltage Trim Range VOUT_DC [b] [c] 2.2 3.3 4.0 V Line Regulation ΔVOUT / ΔVIN At 25°C, 14V < VIN < 42V 0.10 % Load Regulation ΔVOUT / ΔIOUT At 25°C, 2A < IOUT < 20A 0.10 % Output Voltage Ripple VOUT_AC IOUT = 20A, COUT = 8 x 100µF, 20MHz BW [d] 67 mVP-P Output Current IOUT_DC [e] 0 22 A Current Limit IOUT_CL Typical current limit based on nominal 230nH inductor. 25.1 A Maximum Array Size NPARALLEL [b] 3 Modules Output Current, Array of 2 IOUT_DC_ARRAY2 Total array capability, [b] see applications section for details 0 [g] A Output Current, Array of 3 IOUT_DC_ARRAY3 Total array capability, [b] see applications section for details 0 [g] A Protection Input UVLO Start Threshold VUVLO_START 12.9 13.8 V Input UVLO Stop Hysteresis VUVLO_HYS 0.85 1.21 1.75 V Input UVLO Response Time 1.25 µs Input OVLO Stop Threshold VOVLO 44 47 V Input OVLO Start Hysteresis VOVLO_HYS Hysteresis active when OVLO present for at least tFR_DLY 0.5 0.9 1.3 V Input OVLO Response Time tf 1.25 µs Output Overvoltage Protection, Relative VOVP_REL Above set VOUT 20 % Output Overvoltage Protection, Absolute VOVP_ABS 4.3 4.7 V [a] All parameters reflect regulator and inductor system performance. Measurements were made using a standard PI332x evaluation board with 3 x 3” dimensions and four-layer, 2oz copper. Refer to inductor pairing table within Application Description section for specific inductor manufacturer and value. [b] Regulator is assured to meet performance specifications by design, test correlation, characterization, and/or statistical process control. Output voltage is determined by an external feedback divider ratio. [c] Output current capability may be limited and other performance may vary from noted electrical characteristics when VOUT is not set to nominal. [d] Refer to Output Ripple plots. [e] Refer to Load Current vs. Ambient Temperature curves. [f] Refer to Switching Frequency vs. Load current curves. [g] Contact factory applications for array derating and layout best practices to minimize sharing errors.

ZVS Regulators Rev 1.6 Page 9 of 36 02/2021 PI332x-00 PI3323-00 (3.3VOUT) Electrical Characteristics (Cont.) Specifications apply for –40°C < TINT < 120°C for -LGIZ, -BGIZ, –55°C < TJ < 115°C for -LGMZ, -BGMZ, -BGMP , VIN = 24V, EN = High, unless otherwise noted. Parameter Symbol Conditions Min Typ Max Unit Timing Switching Frequency fs [f] While in Discontinuous Conduction Mode (DCM) only, SYNCI grounded 470 500 530 kHz Fault Restart Delay tFR_DLY 30 ms Synchronization Input (SYNCI) Synchronization Frequency Range fSYNCI –50% and +10% relative to set switching frequency (fS), while in DCM operating mode only. [c] and [f] 250 550 kHz SYNCI Threshold VSYNCI 2.5 V Synchronization Output (SYNCO) SYNCO High VSYNCO_HI Source 1mA 4.5 V SYNCO Low VSYNCO_LO Sink 1mA 0.5 V SYNCO Rise Time tSYNCO_RT 20pF load 10 ns SYNCO Fall Time tSYNCO_FT 20pF load 10 ns Soft Start, Tracking and Error Amplifier TRK Active Range (Nominal) VTRK 0 1.4 V TRK Enable Threshold VTRK_OV 20 40 60 mV TRK to EAIN Offset VEAIN_OV 40 80 120 mV Charge Current (Soft Start) ITRK 30 50 70 µA Discharge Current (Fault) ITRK_DIS VTRK = 0.5V 8.7 mA TRK Capacitance, Internal CTRK_INT 47 nF Soft-Start Time tSS CTRK_EXT = 0µF 0.6 0.94 1.6 ms Error Amplifier Transconductance GMEAO 5.06 mS PSM Skip Threshold PSMSKIP 0.6 V EAIN Capacitance, Internal CEAIN_INT 56 pF Error Amplifier Output Impedance ROUT [b] 1 MΩ Internal Compensation Capacitor CHF 56 pf Internal Compensation Resistor RZI 5 kΩ [a] All parameters reflect regulator and inductor system performance. Measurements were made using a standard PI332x evaluation board with 3 x 3” dimensions and four-layer, 2oz copper. Refer to inductor pairing table within Application Description section for specific inductor manufacturer and value. [b] Regulator is assured to meet performance specifications by design, test correlation, characterization, and/or statistical process control. Output voltage is determined by an external feedback divider ratio. [c] Output current capability may be limited and other performance may vary from noted electrical characteristics when VOUT is not set to nominal. [d] Refer to Output Ripple plots. [e] Refer to Load Current vs. Ambient Temperature curves. [f] Refer to Switching Frequency vs. Load current curves.

ZVS Regulators Rev 1.6 Page 15 of 36 02/2021 PI332x-00 PI3325-00 (5.0VOUT) Electrical Characteristics Specifications apply for –40°C < TINT < 120°C for -LGIZ, -BGIZ, –55°C < TJ < 115°C for -LGMZ, -BGMZ, -BGMP , VIN = 24V, EN = High, unless otherwise noted. Parameter Symbol Conditions Min Typ Max Unit Input Specifications Input Voltage VIN_DC 14 24 42 V Input Current IIN_DC VIN = 24V, TCASE = 25°C, IOUT = 20A 4.41 A Input Current At Output Short (Fault Condition Duty Cycle) IIN_Short Short at terminals 5 mA Input Quiescent Current IQ_VIN Disabled 0.94 1.6 mA Input Quiescent Current IQ_VIN Enabled, no load, TCASE = 25°C 4.2 mA Input Voltage Slew Rate VIN_SR [b] 1 V/µs Input capacitance, Internal CIN_INT Effective value VIN = 24V, 25°C 0.7 µF Output Specifications EAIN Voltage Total Regulation VEAIN [b] 0.975 0.990 1.005 V Output Voltage Trim Range VOUT_DC [b] [c] 4.0 5.0 6.5 V Line Regulation ΔVOUT / ΔVIN At 25°C, 14V < VIN < 42V 0.10 % Load Regulation ΔVOUT / ΔIOUT At 25°C, 2A < IOUT < 20A 0.10 % Output Voltage Ripple VOUT_AC IOUT = 20A, COUT = 12 x 47µF, 20MHz BW [d] 55.7 mVP-P Output Current IOUT_DC [e] 0 20 A Current Limit IOUT_CL Typical current limit based on nominal 230nH inductor. 24 A Maximum Array Size NPARALLEL [b] 3 Modules Output Current, Array of 2 IOUT_DC_ARRAY2 Total array capability, [b] see applications section for details 0 [g] A Output Current, Array of 3 IOUT_DC_ARRAY3 Total array capability, [b] see applications section for details 0 [g] A Protection Input UVLO Start Threshold VUVLO_START 12.9 13.8 V Input UVLO Stop Hysteresis VUVLO_HYS 0.85 1.21 1.75 V Input UVLO Response Time 1.25 µs Input OVLO Stop Threshold VOVLO 44 47 V Input OVLO Start Hysteresis VOVLO_HYS Hysteresis active when OVLO present for at least tFR_DLY 0.5 0.9 1.3 V Input OVLO Response Time tf 1.25 µs Output Overvoltage Protection, Relative VOVP_REL Above set VOUT 20 % Output Overvoltage Protection, Absolute VOVP_ABS 6.7 7.37 V [a] All parameters reflect regulator and inductor system performance. Measurements were made using a standard PI332x evaluation board with 3 x 3” dimensions and four-layer, 2oz copper. Refer to inductor pairing table within Application Description section for specific inductor manufacturer and value. [b] Regulator is assured to meet performance specifications by design, test correlation, characterization, and/or statistical process control. Output voltage is determined by an external feedback divider ratio. [c] Output current capability may be limited and other performance may vary from noted electrical characteristics when VOUT is not set to nominal. [d] Refer to Output Ripple plots. [e] Refer to Load Current vs. Ambient Temperature curves. [f] Refer to Switching Frequency vs. Load current curves. [g] Contact factory applications for array derating and layout best practices to minimize sharing errors.

ZVS Regulators Rev 1.6 Page 16 of 36 02/2021 PI332x-00 PI3325-00 (5.0VOUT) Electrical Characteristics (Cont.) Specifications apply for –40°C < TINT < 120°C for -LGIZ, -BGIZ, –55°C < TJ < 115°C for -LGMZ, -BGMZ, -BGMP , VIN = 24V, EN = High, unless otherwise noted. Parameter Symbol Conditions Min Typ Max Unit Timing Switching Frequency fs [f] While in Discontinuous Conduction Mode (DCM) only, SYNCI grounded 564 600 636 kHz Fault Restart Delay tFR_DLY 30 ms Synchronization Input (SYNCI) Synchronization Frequency Range fSYNCI –50% and +10% relative to set switching frequency (fS), while in DCM operating mode only. [c] and [f] 300 660 kHz SYNCI Threshold VSYNCI 2.5 V Synchronization Output (SYNCO) SYNCO High VSYNCO_HI Source 1mA 4.5 V SYNCO Low VSYNCO_LO Sink 1mA 0.5 V SYNCO Rise Time tSYNCO_RT 20pF load 10 ns SYNCO Fall Time tSYNCO_FT 20pF load 10 ns Soft Start, Tracking and Error Amplifier TRK Active Range (Nominal) VTRK 0 1.4 V TRK Enable Threshold VTRK_OV 20 40 60 mV TRK to EAIN Offset VEAIN_OV 40 80 120 mV Charge Current (Soft Start) ITRK 30 50 70 µA Discharge Current (Fault) ITRK_DIS VTRK = 0.5V 8.7 mA TRK Capacitance, Internal CTRK_INT 47 nF Soft-Start Time tSS CTRK_EXT = 0µF 0.6 0.94 1.6 ms Error Amplifier Transconductance GMEAO 7.6 mS PSM Skip Threshold PSMSKIP 0.8 V EAIN Capacitance, Internal CEAIN_INT 56 pF Error Amplifier Output Impedance ROUT [b] 1 MΩ Internal Compensation Capacitor CHF 56 pf Internal Compensation Resistor RZI 5 kΩ [a] All parameters reflect regulator and inductor system performance. Measurements were made using a standard PI332x evaluation board with 3 x 3” dimensions and four-layer, 2oz copper. Refer to inductor pairing table within Application Description section for specific inductor manufacturer and value. [b] Regulator is assured to meet performance specifications by design, test correlation, characterization, and/or statistical process control. Output voltage is determined by an external feedback divider ratio. [c] Output current capability may be limited and other performance may vary from noted electrical characteristics when VOUT is not set to nominal. [d] Refer to Output Ripple plots. [e] Refer to Load Current vs. Ambient Temperature curves. [f] Refer to Switching Frequency vs. Load current curves.

ZVS Regulators Rev 1.6 Page 22 of 36 02/2021 PI332x-00 Functional Description The PI332x-00 is a family of highly integrated ZVS Buck regulators. The PI332x-00 has an output voltage that can be set within a prescribed range shown in Table 1. Performance and maximum output current are characterized with a specific external power inductor (see Table 3). For basic operation, Figure 58 shows the connections and components required. No additional design or settings are required. ENABLE (EN) EN is the enable pin of the converter. The EN Pin is referenced to SGND and permits the user to turn the regulator on or off. The EN default polarity is a positive logic assertion. If the EN pin is left floating or asserted high, the converter output is enabled. Pulling EN pin below VEN_LO with respect to SGND will disable the regulator output. Remote Sensing If remote sensing is required, the PI332x-00 product family is equipped with a general purpose op-amp. This amplifier can allow full differential remote sense by configuring it as a differential follower and connecting the VDIFF pin to the EAIN pin. Soft Start The PI332x-00 includes an internal soft-start capacitor to control the rate of rise of the output voltage. See the Electrical Characteristics Section for the default value. Connecting an external capacitor from the TRK pin to SGND will increase the start-up ramp period. See, “Soft Start Adjustment and Track,” in the Applications Description section for more details. Output Voltage Selection The PI332x-00 output voltage is set with REA1 and REA2 as shown in Figure 58. Table 1 defines the allowable operational voltage ranges for the PI332x-00 family. Refer to the Output Voltage Set Point Application Description for details. Output Current Limit Protection The PI332x-00 has a current limit protection, which prevents the output from sourcing current higher than the regulator’s maximum rated current. If the output current exceeds the Current Limit (IOUT_CL) for 1024μs, a slow current limit fault is initiated and the regulator is shutdown which eliminates output current flow. After Fault Restart Delay (tFR_DLY ), a soft-start cycle is initiated. This restart cycle will be repeated indefinitely until the excessive load is removed. The PI332x-00 also has short circuit protection which can rapidly stop switching to protect against catastrophic failure of an external component such as a saturated inductor. If short-circuit protection is triggered the PI332x-00 will complete the current cycle and stop switching. The module will attempt to soft start after Fault Restart Delay (tFR_DLY ). Input Undervoltage Lockout If VIN falls below the input Undervoltage Lockout (UVLO) threshold, but remains high enough to power the internal bias supply, the PI332x-00 will complete the current cycle and stop switching. The system will soft start once the input voltage is reestablished and after the Fault Restart Delay. Figure 58 — ZVS Buck with required components ZVS Buck VINV S1 VOUT VSP VSN VDIFF EAIN EAO COMP TRK PGND VDR SYNCO SYNCI PWRGD EN TESTx SGND CIN REA2 REA1 CCOMP COUT VIN VOUT Table 1 — PI332x-00 family output voltage ranges Device Output Voltage Nominal Range PI3323-00-BGIZ 3.3V 2.2 – 4.0V PI3325-00-LGIZ 5.0V 4.0 – 6.5V

ZVS Regulators Rev 1.6 Page 23 of 36 02/2021 PI332x-00 Input Overvoltage Lockout If VIN exceeds the input Overvoltage Lockout (OVLO) threshold (VOVLO), while the controller is running, the PI332x-00 will complete the current cycle and stop switching. If VIN remains above OVLO for at least tFR_DLY, then the input voltage is considered reestablished once VIN goes below VOVLO-VOVLO_HYS . If VIN goes below OVLO before tFR_DLY elapses, then the input voltage is considered reestablished once VIN goes below VOVLO. The system will soft start once the input voltage is reestablished and after the Fault Restart Delay. Output Overvoltage Protection The PI332x-00 family is equipped with output Overvoltage Protection (OVP) to prevent damage to input voltage sensitive devices. If the output voltage exceeds VOVP-REL or VOVP-ABS , the regulator will complete the current cycle and stop switching. The system will resume operation once the output voltage falls below the OVP threshold and after Fault Restart Delay. Overtemperature Protection The PI332x features an overtemperature protection (OTP), which will not engage until after the product is operated above the maximum rated temperature. The OTP circuit is only designed to protect against catastrophic failure due to excessive temperatures and should not be relied upon to ensure the device stays within the recommended operating temperature range. Thermal shut down terminates switching and discharges the soft-start capacitor. The PI332x will restart after the excessive temperature has decreased by 30°C. Pulse Skip Mode (PSM) PI332x-00 features a Pulse Skip Mode (PSM) to achieve high efficiency at light loads. The regulators are set up to skip pulses if EAO falls below a PSM threshold (PSMSKIP). Depending on conditions and component values, this may result in single pulses or several consecutive pulses followed by skipped pulses. Skipping cycles significantly reduces gate drive power and improves light load efficiency. The regulator will leave PSM once the EAO rises above the Pulse Skip Mode threshold. Variable Frequency Operation Each PI332x-00 is preprogrammed to a base operating frequency, with respect to the power stage inductor (see Table 2), to operate at peak efficiency across line and load variations. At low -line and high-load applications, the base frequency will decrease to accommodate these extreme operating ranges. By stretching the frequency, the ZVS operation is preserved throughout the total input line voltage range therefore maintaining optimum efficiency. Thermal Characteristics Figure 59(a) and 59(c) thermal impedance models that can predict the maximum temperature of the hottest component for a given operating condition. This model assumes that all customer PCB connections are at one temperature, which is PCB equivalent Temperature TPCB °C. The SiP model can be simplified as shown in Figure 59(b). which assumes all PCB nodes are at the same temperature.

ZVS Regulators Rev 1.6 Page 24 of 36 02/2021 PI332x-00 Figure 59 — PI332x-00 thermal model (a), SiP simplified version (b) and inductor thermal model (c) (a) (b) SiP Power Dissipa/g415o n PDSIP (W) Thermal Resistance SiP Case Top θINT-TOP oC / W Thermal Resistance SiP PCB Equivalent θINT-PCB oC / W Case Top Temperature TTOP oC SiP PCB Common Temperature TPCB oC Maximum SiP Internal Temperature TINT ( oC ) (c) Inductor Power Dissipa/g415 on PDIND (W) Thermal Resistance Inductor Case Top θINT-TOP oC / W Inductor Case Top Temperature TTOP oC Maximum Inductor Internal Temperature TINT ( oC ) θINT-LEAD1 oC / W TVS1 oC TVOUT oC Thermal Resistance Inductor Case Bo/g425om θINT-BOTTOM oC / W Inductor Case Bo/g425om Temperature TBOTTOM oC Thermal Resistances Inductor PCB Pads Inductor PCB Pad Temperatures θINT-TAB oC / W θINT-LEAD2 oC / W TTAB oC SiP Power Dissipa/g415on PDSiP (W) Thermal Resistance SiP Case Top θINT-TOP oC / W θINT-VIN oC / W SiP Case Top Temperature TTOP oC TVIN oC Maximum SiP Internal Temperature TINT ( oC ) θINT-VS1 oC / W TVS1 oC θINT-PGND1 oC / W TPGND1 oC θINT-PGND2 oC / W TPGND2 oC θINT-SGND oC / W TSGND oCSiP PCB Pad Temperatures Thermal Resistances SiP PCB Pads

ZVS Regulators Rev 1.6 Page 25 of 36 02/2021 PI332x-00 θINT-TOP the thermal impedance from the hottest component inside the SiP to the top side θINT-PCB the thermal impedance from the hottest component inside the SiP to the customer PCB, assuming all pins are at one temperature. θINT-VIN the thermal impedance from the hottest component inside the SiP to the circuit board VIN pads. θINT-VS1 the thermal impedance from the hottest component inside the SiP to the circuit board VS1 pads. θINT-PGND1 the thermal impedance from the hottest component inside the SiP to the circuit board at the PGND1 pads. PGND1 is pins 12A-K. θINT-PGND2 the thermal impedance from the hottest component inside the SiP to the circuit board at the PGND2 pads . PGND2 is pins 2F-J, 3F-J, 4C-J, 5B-J and 6C-K. θINT-SGND the thermal impedance from the hottest component inside the SiP to the circuit board at the SGND pads. The following equation can predict the junction temperature based on the heat load applied to the SiP and the known ambient conditions with the simplified thermal circuit model: θINT-TOP θINT-PCB TTOP θINT-TOP TPCB θINT-PCB PD + (1)TINT = Product System Simplified SiP Thermal Impedances Detailed SiP Thermal Impedances θINT-TOP (°C / W) θINT-PCB (°C / W) θINT-TOP (°C / W) θINT-VIN (°C / W) θINT-VS1 (°C / W) θINT-PGND1 (°C / W) θINT-PGND2 (°C / W) θINT-SGND (°C / W) PI332x-00 110 1.7 110 3.4 4.8 33 33 91 Table 2 — PI332x-00 SiP thermal impedance Where the symbol in Figure 59(a) and (b) is defined as the following: θINT-TOP the thermal impedance from the hot spot to the top surface of the core. θINT-BOT the thermal impedance from the hot spot to the bottom surface of the core. θINT-TAB the thermal impedance from the hot spot to the metal mounting tab on the core body, if applicable. θINT-LEAD1 the thermal impedance from the hot spot to one of the mounting leads. Since the leads are the same thermal impedance, there is no need to specify by explicit pin number. θINT-LEAD2 the thermal impedance from the hot spot to the other mounting lead. Where the symbol in Figure 59(c) is defined as the following: Table 3 — Inductor effective thermal model parameters Product System Inductor Part Number Effective Thermal Impedances θINT-TOP (°C / W) θINT-LEAD1, θINT-LEAD2 (°C / W) θINT-BOTTOM (°C / W) θINT-TAB (°C / W) PI332x-00 FP2207R1-R230-R 11 9.4 6.8 N/A

ZVS Regulators Rev 1.6 Page 28 of 36 02/2021 PI332x-00 Inductor Pairing The PI332x-00 utilizes an external inductor. This inductor has been optimized for maximum efficiency performance. Table 3 details the specific inductor value and part number utilized for each PI332x-00. The same inductor model may have different effective thermal impedances, depending on the model ZVS Buck paired with it. The thermal impedances are used in a virtual model of the inductor to estimate the maximum temperature, and the location of the maximum temperature may vary depending on the ZVS Buck model that the inductor is used with. This is because the effective thermal impedances are not only based on the geometry and materials used in the inductor, but include how the inductor power dissipation is distributed among core losses, DC copper losses and AC copper losses. This distribution is dependent on the ZVS Buck model that uses the inductor. Parallel Operation Multiple PI332x-00 can be connected in parallel to increase the output capability of a single output rail. When connecting modules in parallel, each EAO, TRK and EN pin should be connected together. EAIN pins should remain separated, each with an REA1 and REA2, to reject noise differences between different modules' SGND pins. Current sharing will occur automatically in this manner so long as each inductor is the same value. Refer to the Electrical Characteristics table for maximum array size and array rated output current. Current sharing may be considered independent of synchronization and/or interleaving. Modules do not have to be interleaved or synchronized to share current. Due to the high output current capability of a single module and Critical Conduction Mode (CrCM) occurring at approximately 50% rated load, interleaving is not supported. Use of the PI332x-00 SYNCI pin is practical only under a limited set of conditions. Synchronizing to another converter or to a fixed external clock source can result in a significant reduction in output power capability or higher than expected ripple. Filter Considerations The PI332x-00 requires low impedance ceramic input capacitors (X7R/X5R or equivalent) to ensure proper start up and high-frequency decoupling for the power stage. The PI332x-00 will draw nearly all of the high-frequency current from the low-impedance ceramic capacitors when the main high-side MOSFET(s) are conducting. During the time the MOSFET(s) are off, the input capacitors are replenished from the source. Table 6 shows the recommended input and output capacitors to be used for the PI332x-00 as well as per capacitor RMS ripple current and the input and output ripple voltages. Table 5 lists the recommended input and output ceramic capacitors manufacturer and part numbers. It is very important to verify that the voltage supply source as well as the interconnecting lines are stable and do not oscillate. Input filter case 1 — Inductive source and local, external, input decoupling capacitance with negligible ESR (i.e., ceramic type): The voltage source impedance can be modeled as a series RLINE LLINE circuit. The high performance ceramic decoupling capacitors will not significantly damp the network because of their low ESR; therefore in order to guarantee stability the following conditions must be verified: Where rEQ_IN can be calculated by dividing the lowest line voltage by the full load input current. It is critical that the line source impedance be at least an octave lower than the converter’s dynamic input resistance, Equation 6. However, RLINE cannot be made arbitrarily low otherwise Equation 5 is violated and the system will show instability, due to an under-damped RLC input network. Figure 65 — PI332x-00 parallel operation ZVS Buck VINV S1 VOUT VSP VSN VDIFF EAIN EAO COMP TRK PGND VDR SYNCO SYNCI PWRGD EN TESTx SGND CIN_1 COUT_1 REA2_1 L1_1 REA1_1 CCOMP_1 VIN EN ZVS Buck VINV S1 VOUT VSP VSN VDIFF EAIN EAO COMP TRK PGND VDR SYNCO SYNCI PWRGD EN TESTx SGND CIN_2 COUT_2 L1_2 CCOMP_2 VIN EN VOUT VOUT TRK EAO TRK EAO REA2_2 REA1_2 ( ) LLINE CIN_INT + CIN_EXT • rEQ_IN RLINE > (5) (6)RLINE << rEQ_IN Table 3 — PI332x-00 Inductor pairing Product System Value (nH) MFR Part Number Max Operating Temp (°C) PI3323-00 230 Eaton FP2207R1-R230-R 125 Pulse PA4792.231HLT PI3325-00 230 Eaton FP2207R1-R230-R 125 Pulse PA4792.231HLT

ZVS Regulators Rev 1.6 Page 29 of 36 02/2021 PI332x-00 Input filter case 2 — Inductive source and local, external input decoupling capacitance with significant R CIN_EXT ESR (i.e., electrolytic type): In order to simplify the analysis in this case, the voltage source impedance can be modeled as a simple inductor L LINE. Notice that the high performance ceramic capacitors CIN_INT within the PI332x-00 should be included in the external electrolytic capacitance value for this purpose. The stability criteria will be: Equation 8 shows that if the aggregate ESR is too small – for example by using very high quality input capacitors (CIN_EXT ) – the system will be under-damped and may even become destabilized. As noted, an octave of design margin in satisfying Equation 7 should be considered the minimum. When applying an electrolytic capacitor for input filter damping the ESR value must be chosen to avoid loss of converter efficiency and excessive power dissipation in the electrolytic capacitor. VDR Bias Regulator The VDR internal bias regulator is a ZVS switching regulator that resides internal to the PI332x-00 SiP. It is intended primarily to power the internal controller and driver circuitry. The power capability of this regulator is sized for the PI332x-00, with adequate reserve for the application it was intended for. It may be used for as a pullup source for open collector applications and for other very low power uses with the following restrictions: 1. The total external loading on VDR must be less than I VDR. 2. No direct connection is allowed. Any noise source that can disturb the VDR voltage can also affect the internal controller operation. A series impedance is required between the VDR pin and any external circuitry. 3. All loads must be locally decoupled using a 0.1μF ceramic capacitor. This capacitor must be connected to the VDR output through a series resistor no smaller than 1kΩ, which forms a low-pass filter. Additional System Design Considerations 1. Inductive loads: As with all power electronic applications, consideration must be given to driving inductive loads that may be exposed to a fault in the system which could result in consequences beyond the scope of the power supply primary protection mechanisms. An inductive load could be a filter, fan motor or even excessively long cables. Consider an instantaneous short circuit through an un-damped inductance that occurs when the output capacitors are already at an initial condition of fully charged. The only thing that limits the current is the inductance of the short circuit and any series resistance. Even if the power supply is off at the time of the short circuit, the current could ramp up in the external inductor and store considerable energy. The release of this energy will result in considerable ringing, with the possibility of ringing nodes connected to the output voltage below ground. The system designer should plan for this by considering the use of other external circuit protection such as load switches, fuses and transient voltage protectors. The inductive filters should be critically damped to avoid excessive ringing or damaging voltages. Adding a high-current Schottky diode from the output voltage to PGND close to the PI332x-00 is recommended for these applications. 2. Low-voltage operation: There is no isolation from an SELV (Safety-Extra-Low-Voltage) power system. Powering low voltage loads from input voltages as high as 60V may require additional consideration to protect low voltage circuits from excessive voltage in the event of a short circuit from input to output. A fast TVS (transient voltage suppressor) gating an external load switch is an example of such protection. Table 5 — Recommended input and output capacitor components Manufacturer Part Number Value Description Murata GRM32ER71A476KE15 47µF 47μF 10V 1210 X7R Murata GRM32ER71A476K 4.7µF 4.7μF 80V 1210 X7R Murata GRM32EC70J107ME15K 100µF 100μF 6.3V 1210 X7S Product Load Current (A) CIN COUT CIN Ripple Current (IRMS) COUT Ripple Current (IRMS) VIN Ripple (mVpp) VOUT Ripple (mVpp) Load Step (% Rating) (1A/µs) Transient Deviation Excluding Ripple (mVpk) VOUT Recovery Time (µs) PI3323-00 22 8 x 4.7µF 8 x 100µF 10.85 14.5 540 67 50 – 100 110 < 90 PI3325-00 20 6 x 4.7µF 12 x 47µF 10.43 13.25 512 55.7 50 – 100 90 < 80 Table 6 — Recommended input and output capacitor quantity and performance at nominal line, nominal trim. (7)rEQ_IN > RCIN_EXT LLINE CIN_INT • RCIN_EXT < rEQ_IN (8)

ZVS Regulators Rev 1.6 Page 31 of 36 02/2021 PI332x-00 L L Recommended receiving footprint for PI332x-00 10 x 14mm package. All pads should have a final copper size of 0.55 x 0.55mm, whether they are solder-mask defined or copper defined, on a 1 x 1mm grid. All stencil openings are 0.45mm when using either a 5mil or 6mil stencil. LGA Recommended PCB Footprint and Stencil

ZVS Regulators Rev 1.6 Page 32 of 36 02/2021 PI332x-00 A L D E AND POSITION A A2 D E A M A M DETAIL A DETAIL B G E D A L DETAIL B K SOLDER MASK METALLIZED PAD SEATING PLANE DETAIL A M A M

ZVS Regulators Rev 1.6 Page 33 of 36 02/2021 PI332x-00 e e b PIN 1 FOR PCB LAND PATTERN BB 10.5x14.5mm SiP DIMENSIONSAL REFERENCES REF. MIN. NOM. MAX. b 0.59 0.64 0.69 D1 13.00 BSC. E1 9.00 BSC. e 1.00 BSC. BGA Recommended PCB Footprint and Stencil

ZVS Regulators Rev 1.6 Page 34 of 36 02/2021 PI332x-00 D E PIN 1 INDEX CORNER B A DETAIL A e e DETAIL B PIN 1 INDEX CORNER ABCDEFGHJK aaa C (4X) A DETAIL DETAIL A SCALE 25 : 1 SEATING PLANE ddd C bbb C C e DETAIL B nX Øb 4 BUMPS UP VIEWBUMPS DOWN VIEW

0.25 M C A B

0.1 M C

NOTES: ALL DIMENSIONS ARE IN MILLIMETERS.1. 'e' REPRESENTS THE BASIC SOLDER BALL GRID PITCH.2. 'M' REPRESENTS THE BASIC SOLDER BALL MATRIX SIZE.3. AND SYMBOL 'n' IS THE NUMBER OF BALLS AFTER DEPOPULATING. 'b' IS MEASURABLE AT THE MAXIMUM SOLDER BALL DIAMETER AFTER REFLOW4. PARALLEL TO PRIMARY DATUM C . DIMENSION 'ddd' IS MEASURED PARALLEL TO PRIMARY DATUM C .5. PRIMARY DATUM C AND SEATING PLANE ARE DEFINED BY THE SPERICAL 6. CROWNS OF THE SOLDER BALLS. THE OVERALL PACKAGE THICKNESS "A" ALREADY CONSIDERS COLLAPSE BALLS7. DIMENSIONING AND TOLERANCING PER ASME Y14.5M 1994.8. REFERENCE TO JEDEC MO-234B.9. RoHS COMPLIANT PER CST-0001 LATEST REVISION.10. DIMENSIONAL REFERENCES REF. MIN. NOM. MAX. A 2.96 3.05 3.14 A1 0.44 0.49 0.54 A3 1.95 2.00 2.05 D 14.50 D1 13.00 BSC E 10.50 E1 9.00 BSC b 0.59 0.64 0.69 aaa 0.20 bbb 0.25 ddd 0.15 e 1.00 BSC MD/ME 14/10 n 110

ZVS Regulators Rev 1.6 Page 35 of 36 02/2021 PI332x-00

Revision History

Revision Date Description Page Number(s) 1.0 12/05/17 Initial release n/a 1.1 02/06/18 Added typical start-up waveforms 14 1.2 07/25/19 Updated figure 28 Removed note 1.3 04/17/20 Added PI3323-00 part numbers, and BGIZ, BGMZ, BGMP options Updated PI3325 enabled input quiescent current Added BGA drawings 1, 3, 8 – 14, 22, 26, 28, 29 33, 34 1.4 06/22/20 Updated to add recommended Pulse Electronics inductor 28 1.5 08/12/20 Updated terminology 27 1.6 02/22/21 Updated to include PI3323-00-LGMZ, PI3325-00-LGMZ 1, 3, 7, 8, 9, 15, 16 Please note: Pages added in Rev 1.3.

ZVS Regulators Rev 1.6 Page 36 of 36 02/2021 PI332x-00 Contact Us: http://www.vicorpower.com/contact-us Vicor Corporation

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