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controller, all within a integration Switching increases p class powe external in complete D Devi PI3311‐X PI3312‐X PI3301‐X PI3302‐X PI3303‐X PI3305‐X Table 1 ‐ PI3 higher 18A c and Vout >1 The Zero enables hi switching switching f external density, an line and lo high switc input volta its 20ns m conversion I2C is a trade ration • picorpo 8V to 36 ption X is a family o C‐DC ZVS‐Bu power switch a high density n of a high (ZVS) topolog point of load p er efficiency. T nductor and m DC‐DC switchin ce Ou Set 0‐LGIZ 1.0V 0‐LGIZ 2.5V 0‐LGIZ 3.3V 0‐LGIZ 5.0V 0‐LGIZ 12V 0‐LGIZ 15V 33XX Portfolio. A current, output 15. Voltage Switc igh frequency losses and ma frequency ope filtering com nd enables ve oad transients hing frequency age without sa inimum on‐tim ns up to 36Vin. mark of NXP Semico ower.com 6Vin Coo of high efficien uck regulator hes, and suppo System‐in‐Pac performance gy, within the performance p The PI33XX re minimal capaci ng mode buck utput Voltage Range 1.00 to 1.4 2.0 to 3.1 2.3 to 4.1 3.3 to 6.5 6.5 to 13.0 10.0 to 16.0 Additional versio voltages (Vout) ching (ZVS) ar operation wh aximizing effici ration reduces mponents, im ery fast dynam s. The PI33XX y all the way u acrificing effici me, supports la nductors PI33XX‐X0‐LGIZ ol‐Power ncy, wide inpu rs integratin ort component ckage (SiP). Th e Zero‐Voltag PI33XX series roviding best i equires only a itors to form regulator. Iout Max 10A 10A 10A 10A 0 8A ons available for of 1.5 to 1.9V, rchitecture als hile minimizin iency. The hig s the size of th proves powe mic response t series sustain up to the rate iency and, wit arge step dow Z Family Datashe r® ZVS B ut ng ts e ge n n a r o g h e er o ns d h n Feat H Z W V H U P P In O O F ‐4 O App H C A H Pack 1 eet Rev Buck Reg tures High efficiency ZVS‐Buck Topo Wide input volt Very‐Fast trans High accuracy p User adjustable Power‐up into Parallel capable nput Over/Und Output Overvo Over Temperat Fast and slow c 40°C to 125°C Optional I2C fun Vout margi Fault repor Enable and Phase dela regulators) plications High efficiency Computing, Com Automotive Eq High voltage ba kage Inform 10mm x 14mm
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2012 Page
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PI3311‐X0 Electric PI3311‐ PI3312‐X0 Electric PI3312‐ PI3301‐X0 Electric PI3301‐ PI3302‐X0 Electric PI3302‐ PI3303‐X0 Electric PI3303‐ PI3305‐X0 Electric PI3305‐ Functiona ration • picorpo ts Maximum Ra 0 (1.0 VOUT) cal Specificati ‐X0 Typical Ch 0 (2.5 Vout) E cal Specificati ‐X0 Typical Ch 0 (3.3 Vout) E cal Specificati ‐X0 Typical Ch 0 (5.0Vout) El cal Specificati ‐X0 Typical Ch 0 (12Vout) Ele cal Specificati ‐X0 Typical Ch 0 (15 Vout) El cal Specificati ‐X0 Typical Ch al Description ower.com atings at 25°C Electrical Cha haracteristics Electrical Char haracteristics Electrical Char haracteristic . ectrical Chara haracteristics ectrical Chara haracteristics ectrical Chara haracteristics PI33XX‐X0‐LGIZ aracteristics . racteristics . 10 racteristics . 14 acteristics .. 18 acteristics ... 2 acteristics .. 2 Z Family Datashe EN Sw Ou Sof Re Ou Inp Inp Ou Ov Pu Va Pa r I2C Appli Ou Sof Ind Inp Layou Recom Packa Warr eet Rev ABLE (EN) .... witching Frequ utput Voltage mote Sensing utput Current put Under‐Vo put Over Volt utput Over Vo ver Temperatu lse Skip Mode riable Freque rallel Operati C Bus (PI33XX‐ cation Descri utput Voltage ft‐Start Adjus ductor Pairing put and Outp ut Guidelines mmended PC age Drawings Trimming .... Limit Protect oltage Lockou age Lockout . oltage Protect ure Protectio ency Operatio ‐20 and PI33X Programmin st and Trackin ut Filter Cons CB Footprint a XX‐21 only) ... siderations .... and Stencil .... 2 of 39
PI3311‐0 PI3312‐0 PI3301‐0 PI3302‐0 PI3303‐0 PI3305‐0 Higher C PI3311‐0 PI3312‐0 PI3301‐0 I2C Func PI3311‐2 PI3312‐2 PI3301‐2 PI3302‐2 PI3303‐2 PI3305‐2 PI3311‐2 PI3312‐2 PI3301‐2 *Please con PI33XX ration • picorpo nformatio Power 0‐LGIZ 0‐LGIZ 0‐LGIZ 0‐LGIZ 0‐LGIZ 0‐LGIZ Current Versio 1‐LGIZ 1‐LGIZ 1‐LGIZ tionality & P 0‐LGIZ 0‐LGIZ 0‐LGIZ 0‐LGIZ 0‐LGIZ 0‐LGIZ 1‐LGIZ 1‐LGIZ 1‐LGIZ ntact Picor for av Efficiency ower.com n Output R Set 1.0V 1 2.5V 2. 3.3V 2 5.0V 3 12V 6 15V 10 ons* 1.0V 1 2.5V 2 3.3V 2 rogrammabil 1.0V 1 2.5V 2 3.3V 2 5.0V 3 12V 6 15V 10 1.0V 1 2.5V 2 3.3V 2 vailability PI33XX‐X0‐LGIZ Range Range .00 to 1.4V .0V to 3.1V 2.3 to 4.1V 3.3 to 6.5V .5 to 13.0V 0.0 to 16.0V 1.0 to 1.4V 2.0 to 3.1V 2.3 to 4.1V lity* 1.0 to 1.4V 2.0 to 3.1V 2.3 to 4.1V .30 to 6.5V .5 to 13.0V 0.0 to 16.0V 1.0 to 1.4V 2.0 to 3.1V 2.3 to 4.1V Z Family Datashe Iout Max 10A 10m 10A 10m 10A 10m 10A 10m 8A 10m 8A 10m 18A 10m 18A 10m 18A 10m 10A 10m 10A 10m 10A 10m 10A 10m 8A 10m 8A 10m 18A 10m 18A 10m 18A 10m eet Rev Package mm x 14mm 12 mm x 14mm 12 mm x 14mm 12 mm x 14mm 12 mm x 14mm 12 mm x 14mm 12 mm x 14mm 12 mm x 14mm 12 mm x 14mm 12 mm x 14mm 12 mm x 14mm 12 mm x 14mm 12 mm x 14mm 12 mm x 14mm 12 mm x 14mm 12 mm x 14mm 12 mm x 14mm 12 mm x 14mm 12 23‐pin LGA 23‐pin LGA 23‐pin LGA 23‐pin LGA 23‐pin LGA 23‐pin LGA 23‐pin LGA 23‐pin LGA 23‐pin LGA 23‐pin LGA 23‐pin LGA 23‐pin LGA 23‐pin LGA 23‐pin LGA 23‐pin LGA 23‐pin LGA 23‐pin LGA 23‐pin LGA
ration • picorpo scription Number Block 1 Block 2 Block 3 Block 5 Block 4 K3, A4 e Pin‐Out 123‐Lead LGA ( Top TJmax = 125 °C, ower.com
Description
Signal ground: communicatio Power ground Input voltage: Output voltage Switching nod Parallel Good: Error amp out Enable Input: Asserted low, r Remote Sense Adjust input: A the output volt Soft‐start and to decrease th No Connect: L Synchronizatio other converte Synchronizatio impedance dig Data Line: Con Clock Line: Con Tri‐state Addre Tri‐state Addre 10mm x 14mm) view θJA = 22 °C/W PI33XX‐X0‐LGIZ : Internal logic g n returns. SGND : VIN and VOUT and sense for U e: and sense for e: and ZVS sens Used for paralle put: External co Regulator enabl regulator output e: High side conn An external resis tage up or down track input: An e rate of rise du Leave pins floati on output: Outp ers. on input: Synchr gital input node a nnect to SGND f nnect to SGND f ess : No connect ess : No connect Z Family Datashe round for EA, TR D and PGND are power returns UVLO, OVLO and r power switches e for power swit el timing manag onnection for add e control. Assert t disabled. Polar nection. Connec stor may be con n external capaci ring soft‐start. ng. puts a low signal ronize to the fall and should alwa for PI33XX‐10 an for PI33XX‐10 an t for PI33XX‐10 a t for PI33XX‐10 a eet Rev RK, SYNCI, SYNCO star connected w feed forward ra s and feed‐forw tches gement intended ditional compen ted high or left f rity is programm ct to output regu nected between itor may be conn for ½ of the min ling edge of exte ays be connected nd ‐11. For use w nd ‐11. For use w and ‐11. For use and ‐11. For use Block 1: B2‐ Block 2: A8‐ F4‐ Block 3: G1 Block 4: A1 Block 5: A6 O, ADJ and I2C (o within the regul amp ard ramp d for lead regula nsation and curr floating – regula mable via I2C inte ulation point. n ADJ pin and SG nected between nimum period fo ernal clock frequ d to SGND when with PI33XX‐20 a with PI33XX‐20 a e with PI33XX‐20 e with PI33XX‐20 ‐4, C2‐4, D2‐3 2‐3, J1‐3, K1‐2 ‐10, B8‐10, C8‐ ‐10, G4‐10, H4 2‐14, H12‐14, 12‐14, B12‐14, 2‐14, 6‐7, B6‐7, C6‐7, options) lator package. ator. ent sharing. ator enabled; erface. GND or VOUT to n TRK pin and SG or synchronizatio uency. SYNCI is n not in use. and ‐21 only. and ‐21 only. 0 and ‐21 only. 0 and ‐21 only. 3, E2‐3, F1‐3, ‐10, D8‐10, E4‐ 4‐10, J4‐10, K6‐ J12‐14, K12‐14 C12‐14, D12‐1 , D6‐7 4 of 39 trim GND on of a high G2‐3, ‐10, ‐10 14,
Note: All VIN VS1 VOUT SGND PGD, SYN Storage T Operating Soldering ESD Ratin V ration • picorpo te Maximu voltage nodes NCO, SYNCI, EN Temperature g Junction Tem g Temperature ng (I2C pi VIN PGND SYNCO PGD VC EN SYNCI Power Control ower.com um Ratings s are reference , EAO, ADJ, TR mperature for 20 second ins SCL, SDA, AD CC Mem PI33XX‐X0‐LGIZ s at 25°C ed to PGND RK, ADR1, ADR2 s Figure 1: Sim R0, and ADR1 on 1 Q2 Imory ZVS Contro Z Family Datashe 2, SCL, SDA mplified Block D nly active for PI3 Interface l eet Rev See r Diagram 33XX‐20 and PI3 ‐0.7V to 36V ‐0.7 to 36V, ‐ relevant produ ‐0.3V to 5 ‐65°C ‐40°C 33XX‐21 versions TRK EAO ADJ VS1 VOUT REM ‐4V for 5ns uct section 100mA 5.5V / 5mA C to 150°C C to 140°C 260°C 2kV HBM Vout 5 of 39
PI3311‐ Electrical Unless oth Paramete Efficiency Output Output Vo Output Vo Output Vo Line Regu Load Regu Output Vo Continuou Current Li Input Cur Input Curr Inrush Inp Input Curr (Fault Con Protection UVLO Thre UVLO Hys OVLO Thr OVLO Hys UVLO/OV UVLO/OV OVP Over‐Tem Over‐Tem Hysteresis Timing Switching Fault Rest ration • picorpo ‐X0 (1.0 VO Specification erwise specifie er oltage oltage Total Re oltage Range lation ulation oltage Ripple us Output Curr mit rent rent put Current At rent At Output ndition) n eshold steresis eshold steresis LO Fault Delay LO Response T mperature Fault mperature Rest s Frequency tart Delay ower.com OUT) Elect ns ed: ‐40C < TJ < egulation rent Range Soft Start t Short y Time Time t Threshold tart PI33XX‐X0‐LGIZ rical Chara < 125C, Vin =2 Symbol VOUT_DC VOUT_DC VOUT_DC ∆VOUT(∆VIN) ∆VOUT(∆IOUT) VOUT_AC IOUT_DC IOUT_CL IIN_DC IIN_SS IIN_Short VUVLO VUVLO_HYS VOVLO VOVLO_HYS tf_DLY tf VOVP VOTP VOTP_HYS fS tFR_DLY Z Family Datashe acteristics 24V, L1=120nH Min 0.987 10.2 7.08 130 eet Rev H Typ Max 87.7 1.0 1.0 1.013 1.0 1.4 0.1 0.15 0.1 0.15 476 200 300 7.45 7.82 0.37 38.4 40 0.77 128 500 135 140 380 % Vi Io V 0 V ‐ 4 V % @ % @ mVp‐p Io A Se A mA Vi Io mA Vi Ci mA V V V V Cycles N s c ns + % A kHz Vi (1) ms in = 24V, TC = 2 out = 10 A 0 °C <TJ <70°C 40 °C <TJ <125° @ 25°C, 2V<Vin<36V @ 25°C, .5A<Iout<10A ut=5A, Cout=8x 0MHz BW ee Iout vs. TA Cu in = 24V, TC = 2 out=10A in=24V, Iout=0 in=4x4.7µF ML Number of the switching frequ cycles +1% overdrive Above VOUT in ≥ 18V, Iout ≤ 6 of 39 25°C, C 100μF, urves 25°C, LCC e uency ≤ 8A
PI3311‐ (continu Unless oth Paramete Input Pow Input Volt Input Volt Input Quie Soft Start TRK Active TRK Offse Charge Cu Discharge Soft‐Start Enable High Thre Low Thres Threshold Enable Pu Enable Pu Source Cu Sink Curre Sync In (S Synchroni SYNCI Thr SYNCI Pro Sync Out SYNCO Hig SYNCO Lo SYNCO Ris SYNCO Fa Note 1: Re ration • picorpo ‐X0 Electric ued) erwise specifie er wer tage tage Slew Rate escent Current And Tracking e Range (Nomi t Voltage / Dis urrent (Soft – S Current (Fault Time shold shold d Hysteresis ll‐Up Voltage ll‐Down Voltag urrent ent YNCI) ization Frequen reshold ogrammable Ph (SYNCO) gh w se Time ll Time efer to Switchin ower.com cal Specific ed: ‐40C < TJ < t Function inal) able Threshold Start) ge ncy Range hase Shift ng Frequency v PI33XX‐X0‐LGIZ cations < 125C, Vin =2 Symbol VIN_DC VIN_SR IQ_VIN VTRK d VTRK_OV ITRK ITRK_DIS tSS VEN_HI VEN_LO VEN_HYS VEN_PU VEN_PD IEN_SO IEN_SK ∆fSYNCI VSYNCI ∆φSYNCI VSYNCO_HI VSYNCO_LO tSYNCO_RT tSYNCO_FT vs. Iout graph Z Family Datashe 24V, Min Typ ‐70 ‐ 0.9 0.7 0 100 2 4.5 eet Rev p Max 24 36 2.5 40 60 ‐50 ‐ 30 6.8 2.2 2.6 1 1.1 0.8 0.9 200 300 ‐50 110 2.5 ‐ 270 5.2 0.5 10 20 10 20 V V/μs mA Di En V mV µA mA ms CT V V mV V V uA uA W se fr V V So V S ns 2 ns 2 TRK = 0 With respect to et switching equency ource 1mA. Sink 1mA. 20pF load 20pF load 7 of 39 the
PI3311‐ Efficiency Ambient
0 LFM, Si
L1 = 120n 100 Efficiency [%] Load Current [A] 100 150 200 250 300 350 400 450 500 550 Switching Frequency [kHz] ration • picorpo ‐X0 Typica y at 25°C Temperature P Only g frequency vs nH 123 85 9 Ambient 24V 36V 1 234 12Vin 24Vin 36Vin ower.com l Characte vs. Load Curre s load current 456 7 Iout [A] 951 0 5 t Temperature [⁰C V V 567 LOAD [A] PI33XX‐X0‐LGIZ ristics 33110 ent Curve 331103 331105 7 89 1 0 12Vin 24Vin 36Vin 115 125 89 1 0 Z Family Datashe To Tra Loa Co Ou Vo 2.0 Co Power Loss [W] eet Rev otal Power Los ansient Respo ad Step: 2A to 7 out = 8X 100 µF C utput ripple: V out = 50mV/Div 0us/Div out = 8X 100 µF 0.5 1.5 012 Power oss [W] s (including ex onse: 24V to 1. 7A at 5A/us Ceramic Vin =24V, Vout v F Ceramic 345 Iout [ = 1.0V at 10A 678 9 [A] 12Vin 24Vin 8 of 39 nents) 331102 331104 A 331106 9 10
(contin Output ri Vout = 50 2.0us/Div Cout = 8X ration • picorpo 1‐X0 Typica nued) ipple: Vin =24V 0mV/Div v X 100 µF Ceram ower.com al Characte V, Vout = 1.0V mic PI33XX‐X0‐LGIZ eristics at 5A 331 Z Family Datashe 1107 Sh Vo Iin td eet Rev hort circuit test out = 500mV/D n = 500mA/Div delay_fault = 1m t Div =Ch2 = Ch4 ms
PI3312‐ Electrical Unless oth Paramete Efficiency Output Output Vo Output Vo Output Vo Line Regu Load Regu Output Vo Continuou Current Li Input Cur Input Curr Soft‐Start Input Curr Condition Protection UVLO Thre UVLO Hys OVLO Thr OVLO Hys UVLO/OV UVLO/OV OVP Thres Over‐Tem Over‐Tem Timing Switching Fault Rest ration • picorpo ‐X0 (2.5 Vo Specification erwise specifie er oltage oltage Total Re oltage Range lation ulation oltage Ripple us Output Curr mit rent rent Current rent At Output n eshold steresis eshold steresis LO Fault Delay LO Response T shold mperature Faul mperature Rest Frequency tart Delay ower.com out) Electri ns ed: ‐40C < TJ < egulation rent Range t Short (Fault y Time Time lt Threshold tart Hysteresis PI33XX‐X0‐LGIZ ical Charac < 125C, Vin = 2 Symbol VOUT_DC VOUT_DC VOUT_DC ∆VOUT(∆VIN) ∆VOUT(∆IOUT) VOUT_AC IOUT_DC IOUT_CL IIN_DC IIN_SS IIN_Short VUVLO VUVLO_HYS VOVLO VOVLO_HYS tf_DLY tf VOVP VOTP s VOTP_HYS fS tFR_DLY Z Family Datashe cteristics 24V, L1=200 nH Min T 2.465 2 2.0 2 7.08 7 37 3 130 1 eet Rev H Typ Max 91.3 2.50 2.50 2.535 2.5 3.1 0.1 0.15 0.1 0.15 1.14 200 300 7.45 7.82 0.37 38.4 40 0.77 128 500 135 140 500 % Vi Io V 0 V ‐ 4 V % @ % @ mVp‐p Io Co A A A Vi Io mA Vi Ci mA V V V V Cycles N s c ns + % A kHz Vi ms
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in = 24V, TC = 2 out = 10 A 0 °C <TJ <70°C 40 °C <TJ <125° @ 25°C 12V<Vin @ 25°C, .5A<Iout<10A out=5A, out=4x100μF, 0MHz BW in = 24V, TC = 2 out=10A in=24V, Iout=0 in=4x4.7µF ML Number of the switching frequ cycles +1% overdrive Above VOUT n ≥ 18V, Iout ≤ 8A 10 of 39 25°C, C n<36V 25°C, LCC e uency (1)
PI3312‐ (continu Unless oth Paramete Input Pow Input Volt Input Volt Input Quie Soft Start TRK Active TRK Offse Charge Cu Discharge Soft‐Start Enable Enable Hig Enable Lo Enable Th Enable Pu Enable Pu Source Cu Sink Curre Sync In (S Synchroni SYNCI Thr SYNCI Pro Sync Out SYNCO Hig SYNCO Lo SYNCO Ris SYNCO Fa ration • picorpo ‐X0 Electric ued) erwise specifie er wer tage tage Slew Rate escent Current And Tracking e Range (Nomi t Voltage / Dis urrent (Soft –St Current (Fault Time gh Threshold w Threshold reshold Hyster ll‐Up Voltage ll‐Down Voltag urrent ent YNCI) ization Frequen reshold ogrammable Ph (SYNCO) gh w se Time ll Time ower.com cal Specific ed: ‐40C < TJ < t Function inal) able Threshold tart) resis ge ncy Range hase Shift PI33XX‐X0‐LGIZ cations < 125C, Vin =2 Symbol VIN_DC VIN_SR IQ_VIN VTRK d VTRK_OV ITRK ITRK_DIS tSS VEN_HI VEN_LO VEN_HYS VEN_PU VEN_PD IEN_SO IEN_SK ∆fSYNCI VSYNCI ∆φSYNCI VSYNCO_HI VSYNCO_LO tSYNCO_RT tSYNCO_FT Z Family Datashe 24V, Min Typ ‐70 ‐ 0.9 0.7 0 100 2 4.5 eet Rev p Max 24 36 2.5 40 60 ‐50 ‐ 30 6.8 2.2 2.6 1 1.1 0.8 0.9 200 300 ‐50 110 2.5 270 5.2 0.5 10 20 10 20 V V/μs mA Di En V mV µA mA ms CT V V mV V V uA uA W se fr V V So V S ns 2 ns 2 TRK = 0, 0A< Iou With respect to et switching equency ource 1mA. Sink 1mA. 20pF load 20pF load 11 of 39 ut ≤ 8A the
PI3312‐ Efficiency a L1=200nH Ambient T
0 LFM, SiP
L1 = 200nH 50% 55% 60% 65% 70% 75% 80% 85% 90% 95% Efficiency [%] Output Current [A] 100 200 300 400 500 600 Freq. [KHz] ration • picorpo ‐X0 Typica at 25°C emperature vs Only frequency vs. 0 123 85 95 Ambient 24V 36V 234 12V 24V 36V ower.com l Characte s. Load Curren load current 4567 LOAD [A] 105 1 1 Temperature [°C] 567 Load [A] PI33XX‐X0‐LGIZ ristics 331201 nt Curve 331203 331205 89 1 0 12V 24V 36V 151 2 5 89 1 0 Z Family Datashe Tota Trans Vou Iout 200 Cou Out Vou 2.0u Cou Power Loss [W] eet Rev al Power Loss sient Response ut = 100mV/Div t = 2A/Div. = C 0us/Div. ut = 4 x 100µF C tput ripple: Vi ut = 20mV/Div. us/Div. ut = 4 x 100µF C 0.00 1.00 2.00 3.00 4.00 01 2 (including ext e: 24V to 2.5V v. = Ch 1 h 4 Ceramic in = 24V and V Ceramic 2 345 LOAD [ 12V 24V 36V Vout = 2.5V at 1 6789 [A] 12 of 39 ents) 331202 ad Step 331204 10A 331206
PI3312‐ (continu Output rip Vout = 20m 2.0us/Div. Cout = 4 x ration • picorpo ‐X0 Typical ued) ple: Vin = 24V mV/Div. 100µF Ceramic ower.com l Characte V and Vout = 2 c PI33XX‐X0‐LGIZ ristics .5V at 5A 331207 Z Family Datashe Sho Vout Iin = 5 tdela eet Rev ort circuit test = 1V/Div. = Ch 500mA/Div. = ay_fault = 1ms
PI3301‐ Electrical Unless oth Paramete Efficiency Output Output Vo Output Vo Output Vo Line Regu Load Regu Output Vo Continuou Current Li Input Cur Input Curr Soft‐Start Input Curr Condition Protection UVLO Thre UVLO Hys OVLO Thr OVLO Hys UVLO/OV UVLO/OV OVP Over‐Tem Over‐Tem Timing Switching Fault Rest ration • picorpo ‐X0 (3.3 Vo Specification erwise specifie er oltage oltage Total Re oltage Range lation ulation oltage Ripple us Output Curr mit rent rent Input Current rent At Output n eshold steresis eshold steresis LO Fault Delay LO Response T mperature Faul mperature Rest Frequency tart Delay ower.com out) Electri ns ed: ‐40C < TJ < egulation rent Range t Short (Fault y Time Time lt Threshold tart Hysteresis PI33XX‐X0‐LGIZ ical Charac < 125C, Vin =2 Symbol VOUT_DC VOUT_DC VOUT_DC ∆VOUT(∆VIN) ∆VOUT(∆IOUT) VOUT_AC IOUT_DC IOUT_CL IIN_DC IIN_SS IIN_Short VUVLO VUVLO_HYS VOVLO VOVLO_HYS tf_DLY tf VOVP VOTP s VOTP_HYS fS tFR_DLY Z Family Datashe cteristics 24V, L1=200 nH Min T 3.25 3 2.3 3 7.08 7 37 3 130 1 eet Rev H Typ Max 92.2 3.30 3.30 3.36 3.3 4.1 0.10 0.15 0.10 0.15 37.5 1.49 200 300 7.45 7.82 0.37 38.4 40.0 0.77 128 500 135 140 650 % Vi Io V 0 V ‐ 4 V % @ % @ mVp‐p Io Co A A A Vi Io mA Vi Ci mA V V V V Cycles N s c ns + % A kHz Vi (1) ms in = 24V, TC = 2 out = 10 A 0 °C <TJ <70°C 40 °C <TJ <125° @ 25°C 12V<Vin @ 25°C, .5A<Iout<10A out=5A, out=4x100μF, 0MHz BW in = 24V, TC = 2 out=10A in=24V, Iout=0 in=4x4.7µF ML Number of the switching frequ cycles +1% overdrive Above VOUT in ≥ 12V, Iout ≤ 14 of 39 25°C, C n<36V 25°C, LCC e uency ≤ 10A
PI3301‐ (continu Unless oth Paramete Input Pow Input Volt Input Volt Input Quie Soft Start TRK Active TRK Offse Charge Cu Discharge Soft‐Start Enable Enable Hig Enable Lo Enable Th Enable Pu Enable Pu Source Cu Sink Curre Sync In (S Synchroni SYNCI Thr SYNCI Pro Sync Out SYNCO Hig SYNCO Lo SYNCO Ris SYNCO Fa ration • picorpo ‐X0 Electric ued) erwise specifie er wer tage tage Slew Rate escent Current And Tracking e Range (Nomi t Voltage / Dis urrent (Soft –St Current (Fault Time gh Threshold w Threshold reshold Hyster ll‐Up Voltage ll‐Down Voltag urrent ent YNCI) ization Frequen reshold ogrammable Ph (SYNCO) gh w se Time ll Time ower.com cal Specific ed: ‐40C < TJ < t Function inal) able Threshold tart) resis ge ncy Range hase Shift PI33XX‐X0‐LGIZ cations < 125C, Vin =2 Symbol VIN_DC VIN_SR IQ_VIN VTRK d VTRK_OV ITRK ITRK_DIS tSS VEN_HI VEN_LO VEN_HYS VEN_PU VEN_PD IEN_SO IEN_SK ∆fSYNCI VSYNCI ∆φSYNCI VSYNCO_HI VSYNCO_LO tSYNCO_RT tSYNCO_FT Z Family Datashe 24V, Min Typ ‐70 ‐ 0.9 0.7 0 100 2 4.5 eet Rev p Max 24 36 2.5 40 60 ‐50 ‐ 30 6.8 2.2 2.6 1 1.1 0.8 0.9 200 300 ‐50 110 2.5 270 5.2 0.5 10 20 10 20 V V/μs mA Di En V mV µA mA ms N Io V V mV V V uA uA W se fr V V So V S ns 2 ns 2 out ≤ 8A With respect to et switching equency ource 1mA. Sink 1mA. 20pF load 20pF load 15 of 39 K, 0A< the
PI3301‐ Efficiency a L1=200nH Ambient T L1 = 200nH 50% 55% 60% 65% 70% 75% 80% 85% 90% 95% 100% Efficiency [%] Output Current [A] 100 200 300 400 500 600 700 Frequency (KHz) ration • picorpo ‐X0 Typica at 25°C Temperature v P Package Only frequency vs. 0 123 85 95 Ambient 24V 36V 234 12V 24V 36V ower.com l Characte vs. Load Curren load current 4567 LOAD [A] 105 1 t Temperature [°C 567 Load (A) PI33XX‐X0‐LGIZ ristic 330101 nt Curve 330103 330105 89 1 0 115 125 89 1 0 Z Family Datashe Tota Tra Loa Cou Out Vou 2.0 Co u Power Loss (W) eet Rev al Power Loss (in ansient Respon ad Step: 2A to 7 ut = 4 x 100µF tput ripple: Vi ut = 50mV/Div us/Div ut = 4 x 100µF 0.00 1.00 2.00 3.00 4.00 Power Loss (W) nse: 24V to 3.3 Ceramic n = 24V, Vout Ceramic 2 345 LOAD 12V 24V 36V al components) = 3.3V at 10A 678 9 (A) 16 of 39 330102 330104 330106 9 10
PI3301‐ (contin Output rip Vout = 50m 2.0us/Div Cout = 4 x ration • picorpo ‐X0 Typica ued) pple Vin = 24V, mV/Div 100µF Cerami ower.com l Characte , Vout = 3.3V a c PI33XX‐X0‐LGIZ eristic at 5A 330107 Z Family Datashe Sho tdela eet Rev ort circuit test ay_fault = 1ms
PI3302‐ Electrical Unless oth Paramete Efficiency Efficiency Output Output Vo Output Vo Output Vo Line Regu Load Regu Output Vo Continuou Current Li Input Cur Input Curr Inrush Inp Input Curr Condition Protection UVLO Thre UVLO Hys OVLO Thr OVLO Hys UVLO/OV UVLO/OV OVP Over‐Tem Over‐Tem Timing Switching Fault Rest ration • picorpo ‐X0 (5.0Vo Specification erwise specifie er y oltage oltage Total Re oltage Range lation ulation oltage Ripple us Output Curr mit rent rent put Current At rent At Output n eshold steresis eshold steresis LO Fault Delay LO Response T mperature Fault mperature Resta Frequency tart Delay ower.com ut) Electric ns ed: ‐40C < TJ < egulation rent Range Startup t Short (Fault y Time Time t Threshold art Hysteresis PI33XX‐X0‐LGIZ cal Charac < 125C, Vin =2 Symbol VOUT_DC ∆VOUT(∆VIN ∆VOUT(∆IOUT VOUT_AC IOUT_DC IOUT_CL IIN_DC IIN_SS IIN_Short VUVLO VUVLO_HYS VOVLO VOVLO_HYS tf_DLY tf VOVP VOTP VOTP_HYS fS tFR_DLY Z Family Datashe cteristics 24V, L1=200nH Min T 4.93 3.3 10.2 1 7.08 7 37 3 130 1 eet Rev H Typ Max 93.9 5.00 5.00 5.07 5.0 6.5 0.1 0.15 0.1 0.15 11.2 12.6 2.23 100 300 7.45 7.82 0.37 38.4 40 0.77 128 500 135 140 1.0 % Vi Io V 0 V ‐ 4 V % @ % @ mVp‐p Io Co BW A A A Vi Io mA Vi Ci mA V V V V Cycles N s c ns + % A MHz Vi (1) ms in = 24V, TC = 2 out=10A 0 °C <TJ <70°C 40 °C <TJ <125° @ 25°C 12V<Vin @ 25°C, .5A<Iout<10A out=5A, out=4x47μF20 W in = 24V, TC = 2 out=10A in=24V, Iout=0 in=4x4.7µF ML Number of the switching frequ cycles +1% overdrive Above VOUT in ≥ 18V, Iout ≤ 18 of 39 25°C, C n<36V MHz 25°C, LCC e uency ≤ 10A
PI3302‐ (continu Unless oth Paramete Input Pow Input Volt Input Volt Input Quie Soft Start TRK Active TRK Offse Charge Cu Discharge Soft‐Start Enable Enable Hig Enable Lo Enable Th Enable Pu Enable Pu Source Cu Sink Curre Sync In (S Synchroni SYNCI Thr SYNCI Pro Sync Out SYNCO Hig SYNCO Lo SYNCO Ris SYNCO Fa ration • picorpo ‐X0 Electric ued) erwise specifie er wer tage tage Slew Rate escent Current And Tracking e Range (Nomi t Voltage / Dis urrent (Soft –St Current (Fault Time gh Threshold w Threshold reshold Hyster ll‐Up Voltage ll‐Down Voltag urrent ent YNCI) ization Frequen reshold ogrammable Ph (SYNCO) gh w se Time ll Time ower.com cal Specific ed: ‐40C < TJ < t Function inal) able Threshold tart) resis ge ncy Range hase Shift PI33XX‐X0‐LGIZ cations < 125C, Vin =2 Symbol VIN_DC VIN_SR IQ_VIN VTRK d VTRK_OV ITRK ITRK_DIS tSS VEN_HI VEN_LO VEN_HYS VEN_PU VEN_PD IEN_SO IEN_SK ∆fSYNCI VSYNCI ∆φSYNCI VSYNCO_HI VSYNCO_LO tSYNCO_RT tSYNCO_FT Z Family Datashe 24V, Min T ‐70 ‐ 0.9 0.7 0 100 2 4.5 eet Rev Typ Max 24 36 2.5 40 60 ‐50 ‐ 30 6.8 2.2 2.6 1 1.1 0.8 0.9 200 300 ‐50 110 2.5 270 5.2 0.5 10 20 10 20 V V/μs mA Di En V mV µA mA ms N Io V V mV V V uA uA W se fr V V So V S ns 2 ns 2 out ≤ 8A With respect to et switching equency ource 1mA. Sink 1mA. 20pF load 20pF load 19 of 39 s K, 0A< the
PI3302‐ Efficiency a L1=200nH Ambient T L1=200nH 100 Efficiency [%] Output Current [A] 0.2 0.4 0.6 0.8 1.2 Frequency [MHz] ration • picorpo ‐X0 Typica at 25°C Temperature v Only frequency vs. 1234 60 70 80 Ambient 10V 24V 36V 234 12V 24V 36V ower.com l Characte vs. Load Curren load current 567 8 Iout [A] 12Vin 24Vin 36Vin 90 100 1 Temperature [°C] 567 Load [A] PI33XX‐X0‐LGIZ ristics 330201 nt Curve 330203 330205 8 91 0 n n n 110 120 89 1 0 Z Family Datashe Tota Tran Load Cou 5A/ u Out Vou 1.0 u Cou Power Loss [W] eet Rev al Power Loss (in nsient Response d Step: 2A to 7A t = 4 X 47uF Cer us tput ripple: Vin ut = 50mV/Div us/Div t = 4 X 47uF Cer 0.5 1.5 2.5 3.5 4.5 012 e: 24V to 5V A ramic n = 24V, Vout ramic 345 Iout [A PL (12V) PL (24V) PL (36V)
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al components) 330 = 5.0V at 10A 6789 20 of 39 330202 0204 330206
(contin Output rip Vout = 50m 1.0us/Div Cout = 4 X 4 ration • picorpo ‐X0 Typica ued) pple Vin = 24V, mV/Div 47uF Ceramic ower.com l Characte , Vout = 5.0V a PI33XX‐X0‐LGIZ eristic at 5A 330207 Z Family Datashe Sho tdela eet Rev ort circuit test ay_fault = 1ms
PI3303‐ Electrical Unless oth Paramete Efficiency Output Output Vo Output Vo Output Vo Line Regu Load Regu Output Vo Continuou Current Li Input Cur Input Curr Inrush Inp Input Curr Condition Protection UVLO Thre UVLO Hys OVLO Thr OVLO Hys UVLO/OV UVLO/OV OVP Over‐Tem Over‐Tem Timing Switching Fault Rest ration • picorpo ‐X0 (12Vou Specification erwise specifie er oltage oltage Total Re oltage Range lation ulation oltage Ripple us Output Curr mit rent rent put Current At rent At Output n eshold steresis eshold steresis LO Fault Delay LO Response T mperature Fault mperature Resta Frequency tart Delay ower.com ut) Electric ns ed: ‐40C < TJ < egulation rent Range Startup t Short (Fault y Time Time t Threshold art Hysteresis PI33XX‐X0‐LGIZ cal Charact < 125C, Vin =2 Symbol VOUT_DC VOUT_DC VOUT_DC ∆VOUT(∆VIN) ∆VOUT(∆IOUT) VOUT_AC IOUT_DC IOUT_CL IIN_DC IIN_SS IIN_Short VUVLO VUVLO_HYS VOVLO VOVLO_HYS tf_DLY tf VOVP VOTP VOTP_HYS fS tFR_DLY Z Family Datashe teristics 24V, L1=230nH Min T 11.82 1 6.5 8.1 13.57 14 37 3 130 1 eet Rev H Typ Max 96.5 12.0 12.0 12.18 12 13.0 0.1 0.15 0.1 0.15 4.15 200 300 4.29 15.0 0.37 38.4 40 0.77 128 500 135 140 1.4 % Vi Io V 0 V ‐ 4 V % @ % @ mVp‐p Io Co BW A A A Vi Io mA Vi Ci mA V V V V Cycles N s c ns + % A MHz Vi (1) ms in = 24V, TC = 2 out=8A 0 °C <TJ <70°C 40 °C <TJ <125° @ 25°C 16V<Vin @ 25°C, .5A<Iout<8A out=4A, out=4x22μF, 2 W in = 24V, TC = 2 out=8A in=24V, Iout=0 in=4x4.7µF ML Number of the switching frequ cycles +1% overdrive Above VOUT in ≥ 18V, Iout ≤ 22 of 39 25°C, C n<36V 0MHz 25°C, LCC e uency ≤ 8A
PI3303‐ (continu Unless oth Paramete Input Pow Input Volt Input Volt Input Quie Soft Start TRK Active TRK Offse Charge Cu Discharge Soft‐Start Enable Enable Hig Enable Lo Enable Th Enable Pu Enable Pu Source Cu Sink Curre Sync In (S Synchroni SYNCI Thr SYNCI Pro Sync Out SYNCO Hig SYNCO Lo SYNCO Ris SYNCO Fa ration • picorpo ‐X0 Electric ued) erwise specifie er wer tage tage Slew Rate escent Current And Tracking e Range (Nomi t Voltage / Dis urrent (Soft –St Current (Fault Time gh Threshold w Threshold reshold Hyster ll‐Up Voltage ll‐Down Voltag urrent ent YNCI) ization Frequen reshold ogrammable Ph (SYNCO) gh w se Time ll Time ower.com cal Specific ed: ‐40C < TJ < t Function inal) able Threshold tart) resis ge ncy Range hase Shift PI33XX‐X0‐LGIZ cations < 125C, Vin =2 Symbol VIN_DC VIN_SR IQ_VIN VTRK d VTRK_OV ITRK ITRK_DIS tSS VEN_HI VEN_LO VEN_HYS VEN_PU VEN_PD IEN_SO IEN_SK ∆fSYNCI VSYNCI ∆φSYNCI VSYNCO_HI VSYNCO_LO tSYNCO_RT tSYNCO_FT Z Family Datashe 24V, Min Typ 15.5 ‐70 ‐ 0.9 0.7 0 100 2 4.5 eet Rev p Max 24 36 2.5 40 60 ‐50 ‐ 30 6.8 2.2 2.6 1 1.1 0.8 0.9 200 300 ‐50 110 2.5 270 5.2 0.5 10 20 10 20 V V/μs mA Di En V mV µA mA ms N Io V V mV V V uA uA W se fr V V So V S ns 2 ns 2 out ≤ 8A With respect to et switching equency ource 1mA. Sink 1mA. 20pF load 20pF load 23 of 39 , 0A< the
PI3303‐ Efficiency a L1=230nH Ambient T O LFM SiP Switching fr 100 Efficiency [%] Load Current [A] 0.2 0.4 0.6 0.8 1.2 1.4 1.6 Frequency [MHz] ration • picorpo ‐X0 Typica t 25° Temperature v P Only requency vs. Loa
123 Iou
ower.com l Characte s. Load Curren ad current 456ut [A] 18Vin, 12Vo 24Vin, 12Vo 36Vin, 12Vo 90 100 1 1 nt Temperature [° 456 Load [A] PI33XX‐X0‐LGIZ ristics 330301 nt Curve 330303 330305 out out out 101 2 0 °C] Z Family Datashe Tota Tran Loa Cou Vou 1.0u Cou Power Loss [W] eet Rev al Power Loss (in nsient Response d Step: 2A to 6 ut = 4 X 22uF C A Output Rippl ut = 50mV/Div us/Div ut = 4 X 22uF C 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 e: 24V to 12V 6A, 5A/us Ceramic le: Vin = 24V, V Ceramic 234 Iout [A al components) Vout = 12V at 8 567 24Vin 12Vout 36Vin, 12Vout 24 of 39 330302 330304 330306
PI3303‐ (continu 4A Output Vout = 50m 1.0us/Div Cout = 4 X ration • picorpo ‐X0 Typica ued) t Ripple mV/Div 22uF Ceramic ower.com l Characte PI33XX‐X0‐LGIZ ristics 330307 Z Family Datashe Sho tdela eet Rev ort circuit test ay_fault = 1ms
PI3305‐ Electrical Unless oth Paramete Efficiency Output Output Vo Output Vo Output Vo Line Regu Load Regu Output Vo Continuou Current Li Input Cur Input Curr Inrush Inp Input Curr Condition Protection UVLO Thre UVLO Hys OVLO Thr OVLO Hys UVLO/OV UVLO/OV OVP Over‐Tem Over‐Tem Timing Switching Fault Rest ration • picorpo ‐X0 (15 Vo Specification erwise specifie er oltage oltage Total Re oltage Range lation ulation oltage Ripple us Output Curr mit rent rent put Current At rent At Output n eshold steresis eshold steresis LO Fault Delay LO Response T mperature Fault mperature Resta Frequency tart Delay ower.com ut) Electric ns ed: ‐40C < TJ < egulation rent Range Startup t Short (Fault y Time Time t Threshold art Hysteresis PI33XX‐X0‐LGIZ cal Charac < 125C, Vin =2 Symbol VOUT_DC ∆VOUT(∆VIN) ∆VOUT(∆IOUT) VOUT_AC IOUT_DC IOUT_CL IIN_DC IIN_SS IIN_Short VUVLO VUVLO_HYS VOVLO VOVLO_HYS tf_DLY tf VOVP VOTP VOTP_HYS fS tFR_DLY Z Family Datashe cteristics 24V, L1=230nH Min T 14.78 1 10.0 8.1 16.38 1 37 3 130 1 eet Rev H Typ Max 97.2 15.0 15.0 15.23 15 16 0.1 0.15 0.1 0.15 4.12 200 300 17.2 18.1 0.37 38.4 40 0.77 128 500 135 140 1.5 % Vi Io V 10 V ‐ 4 V % @ % @ mVp‐p Io Co A A A Vi Io mA Vi Ci mA V V V V Cycles N s c ns + % A MHz Vi (1) ms in = 24V, TC = 2 out = 10 A 0 °C <TJ <70°C 40 °C <TJ <125° @ 25°C 8.5V<Vin<36V @ 25°C, 0.5A<Io A out=4A, out=4x22μF, 0MHz BW in = 24V, TC = 2 out=8A in=24V, Iout=0 in=4x4.7µF ML Number of the switching frequ cycles +1% overdrive Above Vout in ≥ 18.1V, Iou 26 of 39 25°C, C out< 25°C, LCC e uency t ≤ 8A
PI3305‐ (continu Unless oth Paramete Input Pow Input Volt Input Volt Input Quie Soft Start TRK Active TRK Offse Charge Cu Discharge Soft‐Start Enable Enable Hig Enable Lo Enable Th Enable Pu Enable Pu Source Cu Sink Curre Sync In (S Synchroni SYNCI Thr SYNCI Pro Sync Out SYNCO Hig SYNCO Lo SYNCO Ris SYNCO Fa ration • picorpo ‐X0 Electric ued) erwise specifie er wer tage tage Slew Rate escent Current And Tracking e Range (Nomi t Voltage / Dis urrent (Soft –St Current (Fault Time gh Threshold w Threshold reshold Hyster ll‐Up Voltage ll‐Down Voltag urrent ent YNCI) ization Frequen reshold ogrammable Ph (SYNCO) gh w se Time ll Time ower.com cal Specific ed: ‐40C < TJ < t Function inal) able Threshold tart) resis ge ncy Range hase Shift PI33XX‐X0‐LGIZ cations < 125C, Vin =2 Symbol VIN_DC VIN_SR IQ_VIN VTRK d VTRK_OV ITRK ITRK_DIS tSS VEN_HI VEN_LO VEN_HYS VEN_PU VEN_PD IEN_SO IEN_SK ∆fSYNCI VSYNCI ∆φSYNCI VSYNCO_HI VSYNCO_LO tSYNCO_RT tSYNCO_FT Z Family Datashe 24V, Min T 18.6 ‐70 ‐ 0.9 0.7 0 100 2 4.5 eet Rev Typ Max 24 36 2.5 40 60 ‐50 ‐ 30 6.8 2.2 2.6 1 1.1 0.8 0.9 200 300 ‐50 110 2.5 270 5.2 0.5 10 20 10 20 V V/μs mA Di En V mV µA mA ms N Io V V mV V V uA uA W se fr V V So V S ns 2 ns 2 out ≤ 8A With respect to et switching equency ource 1mA. Sink 1mA. 20pF load 20pF load 27 of 39 s , 0A< the
PI3305‐ Efficiency a L1=230nH Ambient T O LFM, SiP Switching f 100 Efficiency [%] Output Current [A] 0.2 0.4 0.6 0.8 1.2 1.4 1.6 Frequency (MHz) ration • picorpo ‐X0 Typica t 25°C Temperature v P Only frequency vs. l 123 18.6V 24V 36V 60 70 8 0 Ambie 18.6V 24V 36V 18.6V 24V 36V ower.com l Characte s. Load Curren oad current LOAD [A] 0 90 100 ent Temperature [ 45 6 Load (A) PI33XX‐X0‐LGIZ ristics 330501 nt Curve 330503 330505 678 110 120 [°C] 6 78 Z Family Datashe Tota Tran Load 5A/u Cou Out Vou 1us Cou Power Loss [W] eet Rev al Power Loss (in nsient Response d Step: 2A to 6A us ut = 4x22µF Cera tput ripple: Vin ut = 100mV/Div s/Div ut = 4x22µF Ce 0.0 1.0 2.0 3.0 4.0 5.0 e: 24 to 15V A amic n = 24V, Vout v ramic 234 LOAD [A] 18.6V 24V 36V al components) = 15V at 8A 567 28 of 39 330502 330504 330506
PI3305‐ (continu Output rip Vout = 100 1us/Div Cout = 4x2 ration • picorpo ‐X0 Typica ued) pple: Vin = 24V 0mV/Div 22µF Ceramic ower.com l Characte V, Vout = 15V a PI33XX‐X0‐LGIZ ristics at 4A 330507 Z Family Datashe Sho eet Rev ort circuit test
ENABLE (E EN is the e referenced converter positive log asserted Pulling EN will disable The EN inp and PI33X When the logic asser regulator o
1.0 Vdc w
d synchroniz preset sw PI33XX‐21 programm ration • picorpo onal Descri X is a family o . The PI33XX h within a pre mum output cu external power re 2 ‐ ZVS‐Buck operation, Figu onents require e required. EN) enable pin of d to SGND and on or off. T gic assertion. high, the co pin below 0. e the regulator put polarity can XX‐21 versions EN pin polarity rtion; and if th output is enab with respect output. g Frequency S input allows switching freq d to SGND. ze the unit bet itching freque versions onl ed via I2C bus w ower.com ption of highly integ as a set output escribed range urrent are cha r inductor (see with required co re 2 shows the ed. No addition the converter d permits the u The EN defau If the EN pin is nverter outpu
8 Vdc with re
r output. n be programm only) via the y is programm he EN pin is le bled. Pulling th to SGND, w Synchronizati the user to s quency by an The exter tween 50% an ency (fS). For y, the phase with respect to PI33XX‐X0‐LGIZ rated ZVS‐Buc t voltage that i e. Performanc racterized wit Table 5). omponents e connections nal design or r. The EN Pin i user to turn th lt polarity is s left floating o ut is enabled espect to SGN med (PI33XX‐2 e I2C data bus med for negativ eft floating, th e EN pin abov will disable th ion synchronize th external cloc nal clock ca nd 110% of th PI33XX‐20 an delay can b o the clock Z Family Datashe ck is ce h is e a or D ve e ve e e ck n e d be applie regula interle The P to the phase parall for fu circuit sync w When provid regula regula parall Outp The P the p pin to a resis the vo P P P P P P Table version and Vo Soft‐S The P ramp outpu from ramp in th detail eet Rev ed at SYNCI ators to be eaving mode. PI33XX default e falling edge o e shift from eling of two P urther user pro try. The user with the extern n using the in des a 5V clock ators. Therefor ator and have el and interlea put Voltage Tr PI33XX output reset output b o SGND and ca stor from ADJ oltage ranges f Device PI3311‐X0‐LGIZ PI3312‐X0‐LGIZ PI3301‐X0‐LGIZ PI3302‐X0‐LGIZ PI3303‐X0‐LGIZ PI3305‐X0‐LGIZ 2 ‐ PI33XX fam ns available for out >15V. Start I33XX includes the output ut voltage. Co the TRK pin to period. See, “ e Application pin. Phase d paralleled a for SYNCI is t of the applied SYNCO. Th PI33XX device ogramming or can change th nal clock rising nternal oscillat k that can be re, one PI33XX e additional aved. rimming voltage can b by connecting n be trimmed pin to VOUT. for the PI33XX Out Set 1.0V 2.5V 3.3V 5.0V 12V 15V mily output volta output voltages s an internal so voltage in 2m onnecting an o SGND will in “Soft Start Adju ns Description
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edge. tor, the SYNC used to sync X can act as th PI33XXs runn be trimmed up a resistor fro down by conn The Table 2 d family. put Voltage Range 1.00 to 1.4 2.0 to 3.1 2.3 to 4.1 3.3 to 6.5 6.5 to 13.0 10.0 to 16.0 age ranges. Add s (Vout) of 1.5 t oft‐start capac ms from 0V t external cap ncrease the st ustment and T section for 30 of 39 PI33XX in an espect g 180° r the e need c clock rity to CO pin other e lead ing in p from m ADJ necting defines ditional to 1.9V citor to to full pacitor tart‐up Track,” more
regulator’s current ex a slow curr is shutdow After Fault initiated. indefinitely Fast Curre regulator i the output sudden low a high ind and stop s then initiat Both the F in a Fault (PI33XX‐20 bus. Input Und If VIN falls (UVLO) thr the interna current cy within 128 normal op system wi fault. The s reestablish UVLO faul read and c only) via I2 ration • picorpo Sensing al 100Ω resisto VOUT pin to p t open. With R 00mV above it d reference no urrent Limit P as two metho ut short or ove ent Limit prot m sourcing s maximum r ceeds the Curr rent limit fault wn which elim t Restart Delay This restart y until the exce ent Limit prot inductor curre t from supplyin w impedance ductor current witching until te a soft‐start c Fast and Slow c t Register and 0 and PI33XX‐2 der‐Voltage L s below the i reshold, but re al bias supply, ycle and stop 8 switching cy peration. If th ll enter a low system will res hed and after t is stored in cleared (PI33X 2C data bus. ower.com or is connected provide regula REM open, the ts set point. C ode to be regul Protection ods implement er current cond tection: preve current high ated current. rent Limit (IOUT t is initiated an minates output y (tFR_DLY), a so cycle will essive load is r tection: PI33XX ent pulse‐by‐pu ng very high c short. If the re pulse, it will Fault Restart cycle. current limit fa d can be rea 21 versions on Lockout nput Under V emains high en the PI33XX wi switching. I cles, the PI33 is time limit is w power state start once the the Fault Res a Fault Regist XX‐20 and PI33 PI33XX‐X0‐LGIZ d between REM ation when th e converter wi Connect REM t ated. ted to protec dition. ents the outpu her than th If the outpu T_CL) for 1024us nd the regulato t current flow oft‐start cycle i be repeate emoved. X monitors th ulse to preven urrent due to egulator sense initiate a fau Delay ends an aults are store ad and cleare nly) via I2C dat Voltage Lockou nough to powe ill complete th f VIN recover XX will resum s exceeded, th e and initiate input voltage i start Delay. A ter and can b 3XX‐21 version Z Family Datashe M e ill o ct ut e ut or is d e nt a es lt d d d ta ut er e rs e e a is A be ns Input If VIN thresh PI33X switch cycles Other and s opera the O The O be re versio Outp The P Voltag voltag excee will co issue once thres h fault i cleare I2C da Over The i preve ther m Protec regula enter soft‐st Over‐T OTP fa and c via I2C Pulse PI33X light l EAO f condit single eet Rev t Over Voltag exceeds the in hold (VOVLO), w XX will compl hing. If VIN s, the PI33XX rwise, the syst sets an OVLO ation when the VLO threshold OVLO fault is s ead and clea ons only) via I2C put Over Volta PI33XX family ge Protection ge sensitive eds 20% of its omplete the c an OVP fault. the output hold and afte is stored in a F ed (PI33XX‐20 ata bus. Temperature nternal packa ent system co mal maximum ction Thresho ator will comp a low power tart when the Temperature ault is stored i leared (PI33XX C data bus. e Skip Mode ( XX features a P loads. The reg falls below a tions and com e pulses or sev fault. The s e input voltage d and after the stored in a Fau ared (PI33XX‐ C data bus. age Protectio y is equipped (OVP) to preve devices. If t set regulated current cycle, The system w voltage falls er Fault Restar Fault Register a and PI33XX‐2 e Protection age temperatu omponents fr m. If the old (OTP) is e plete the curr r mode, set a e internal temp Restart Hyste in a Fault Regis X‐20 and PI33X (PSM) PSM to achiev gulators are se PSM thresho mponent value veral consecut tage Lockout ( roller is runnin ent cycle and thin 128 swi normal oper r a low power system will re e falls below 9 Fault Restart ult Register an ‐20 and PI33 on with output ent damage to he output v value, the reg stop switchin will resume ope s below the rt Delay. The and can be rea 21 versions on ure is monitor rom reaching Over Tempe xceeded (VOTP ent switching fault flag, an perature falls eresis (VOTP_HYS ster and can b XX‐21 versions ve high efficie tup to skip pu old. Dependi s, this may re tive pulses fol 31 of 39 OVLO) ng, the d stop itching ration. r state esume 98% of Delay. nd can 3XX‐21 t Over o input voltage gulator ng and eration OVP e OVP ad and ly) via red to their erature P), the cycle, nd will below S). The e read s only) ncy at ulses if ng on sult in llowed
efficiency. rises above Variable F Each PI33X frequency, (see Table and load application accommod stretching preserved range ther Parallel O Paralleling increase t power rail By connec module to equally. W connected during so f released t Also, any f other regu ration • picorpo ed pulses. S ate drive pow The regulator e the Skip Mod Frequency Op XX is preprogr , with respect 5), to operate variations. ns, the base date these ext the frequen throughout t refore maintain Operation multiple PI33 the output cu and reduce ou Figure 3 ‐ PI33X cting the EAO ogether the u When the TR together, the ft‐start and a o allow the u fault event in a ulators. The tw ower.com Skipping cycle wer and impro r will leave PSM de threshold. peration rammed to a to the power e at peak efficie At low line frequency w treme operatin ncy, the ZVS the total inpu ning optimum 3XX modules c urrent capabil utput voltage r XX parallel opera pins and SGN units will sha RK pins of e e units will tra ll unit EN pin units to start any regulator wo regulators PI33XX‐X0‐LGIZ es significantl oves light loa M once the EAO base operatin stage inducto ency across lin and high loa will stretch t ng ranges. B S operation ut line voltag efficiency. can be used t ity of a singl ripple. ation ND pins of eac re the curren each unit ar ack each othe ns have to b (See Figure 3 will disable th will be out o Z Family Datashe ly d O ng or e d o By is ge o e h nt re er e e of phase to Sw To pr the e Good regula be p regula config SYNCI open‐ regula system config the fly enter Multi‐ and P single how t please Multi‐ I2C Bu PI33X interfa polari frequ e one ti Also, t Vout develo and n PI33X telem Fault eet Rev e with each ot itching Freque ovide synchro ntire operatio (PGD) pin m ator’s SYNCI p laced betwee ator’s SYNCI p guration, at sy I low forcing t ‐loop startup ators reach reg m is now guration which y, when any of variable frequ ‐phasing three PI33XX‐21 onl e‐phase design to program p e refer to P ‐Phase Design us (PI33XX‐2 XX‐20 and PI ace that enabl ity (from high ency synchro ime programm the PI33XX‐20 margining v opment (settin not retained b XX‐21 also hav metry: registry list: Over temp Fast/Slow c Output volt Input overv Input unde in and a 2.5kΩ en SYNCO ret pin, as shown ystem soft‐star the lead regula p synchroniza gulation, SYNC synchronized h allows the s f the individua uency mode in e regulators is y) with no c n. For more hase delays w icor applicatio Procedure. 20 and PI33XX 33XX‐21 prov les the user to h to low asser nization phas mable options t 0 and PI33XX‐2 via I2C that ngs stored in v y the device). ve the option erature protec current limit tage high voltage ervoltage ization). ween regulator y range, the P nected to the Ω Resistor, R1, turn and the in Figure 3. rt, the PGD pin ator to initiali ation. Onc e CI is released an in a closed ystem to adju l regulators be the loop. possible (PI33 hange to the information within the regu on note PI33 X‐21 only) vide an I2C program the E rtion) and swi e/delay. Thes to the device. 21 allow for dy is useful d volatile memor The PI33XX‐2 for extended ction 32 of 39 (refer s over Parallel e lead , must e lead In this n pulls ze the e the nd the d‐loop ust, on egin to 3XX‐20 basic about ulator, 3XX‐2X digital EN pin itching se are ynamic during ry only 20 and d fault
PI33XX‐2X Applica Output Vo The PI33X common o and 15V. to offset a maximum connected device’s o nominal s PI3311‐X0 of 1V). PI PI PI PI PI PI Table The remot to the VO voltage off voltage div Fig ration • picorpo information a please refer I2C Interface G tion Descr oltage Progra X family of B output voltages A post‐packag ny resistor div output accur from the ADJ utput can be set voltage (w which can on Device I3311‐X0‐LGIZ I3312‐X0‐LGIZ I3301‐X0‐LGIZ I3302‐X0‐LGIZ I3303‐X0‐LGIZ I3305‐X0‐LGIZ e 3 ‐ PI33XX fam te pin (REM) s UT pin, if not fset. Figure 4 s vider network. ure 4 ‐ Internal r ower.com about how to to Picor app Guide. ription amming uck Regulator s: 1.0V, 2.5V, 3 ge trim step is ider network e acy. With a J pin to SGND varied above with the exce nly be above t Output Vo Set R 1.0V 1.0 2.5V 2. 3.3V 2. 5.0V 3. 12V 6.5 15V 10. mily output voltag should always used, to prev shows the inte resistor divider n PI33XX‐X0‐LGIZ utilize the I2C plication note rs provides six 3.3V, 5.0V, 12V s implemented errors ensuring single resistor or REM, each or below the eption of the he set voltage oltage Range 00 to 1.4 0 to 3.1 3 to 4.1 3 to 6.5 5 to 13.0 0 to 16.0 ge ranges be connected vent an output ernal feedback network Z Family Datashe C e x V d g r h e e e d t k R1, R R_low the d outp regul PI3 PI3 PI3 PI3 PI3 PI3 By c range adjus or R equa value ௪ If, f o shou For t and u the P divid R1= these as fo The avail a eet Rev R2, R3 and R4 w and R_high designer can a ut. The in lator is listed b Device 3311‐X0‐LGIZ 3312‐X0‐LGIZ 3301‐X0‐LGIZ 3302‐X0‐LGIZ 3303‐X0‐LGIZ 3305‐X0‐LGIZ Table 4 ‐ PI choosing an o es stated in sted up or dow R_low value, ations can be u es: ௪ ൌ 1 ݐݑܸ or example, a uld choose the this example, use Equation ( PI3302’s outp er network 4.53Ωk, R2=1.1 e values in to llows: ൌሺ6 value calcula able for purch 1.5k 1.0k 2.61k 1.13 4.53k 1.13 11.0k 1.0k 14.0k 1.0k I33XX Internal d output voltage Table 3, VO wn by selectin respectively used to calculat 1ሻെቀ 1 െ1ሻെቀ 1 6.0V output e proper regu we will selec (1) to calculate ut. From Ta values for 13kΩ, and R3 Equation (1), .0െ1 ሻ 4݇െቀ 1 1.1 ated is ideal hase; therefor l 1.0 % resisto resistors for y VOUT to a d or value for R3 R n 0 1 k 2.0k 1 k 3.0k 1 k 3.0k 1 k 3.0k 1 k 3.0k 1 divider values e value withi OUT can simp g the proper R y. The foll te R_high and ܴ ݀݊ܽ is needed, the ulator from Ta ct the PI3302 e R_high to inc able 4, the re the PI3302 = 3.0kΩ. Ins R_high is calc 1݇ቁ and may n e, select a sta 33 of 39 ors and which desired each 100 100 100 100 100 100 in the ply be R_high lowing R_low ሺ1ሻ ሺ2ሻ e user able 3. (5.0V) crease esistor‐ are: serting ulated ot be andard
1% value c 1%, resisto by using th Soft‐Start The TRK regulator’s regulators internal 10 a minimum PI33XX reg capacitor t increased used to ca soft‐start t Where, tTR internal ch for limits). There is tracking proportion startup, s together. connected at the sa m For Direct highest ou the maste through a the slave’s ration • picorpo close to the v or is a standar he voltage divid t Adjust and T pin offers a s soft‐start tim . The soft‐sta 00nF and a fixe m startup tim gulators. By a to the TRK pin further. The alculate the pr times: RK is the soft‐s harge current ( typically eith implemented nal tracking be simply conne This type regulators to e time (see Fig Figure 5 ‐ PI33X Tracking, cho utput voltage r to the TRK divider (Figur s feedback divid VOU VOU Maste VOUT (a) (b) ower.com alue calculate rd value. Che c der equation. Tracking a means to me or to track w art slope is co ed charge curr me of 2ms (t dding an addit n, the soft‐star following equ oper capacitor start time and see Electrical C her proportio within a etween severa ect all devic of tracking startup and re gure 5 (a)). XX tracking meth oose the regu as the maste pin of the ot re 6) with the der (see Table UT 1 UT 2 er VOUT T 2 PI33XX‐X0‐LGIZ d. A 1.56kΩ, ck your results increase the with additiona ntrolled by an rent to provide ypical) for al tional externa rt time can be uation can be r for a desired x10ିଽ, ITRK is a 50uA Characteristics nal or direct design. For l regulators at es TRK pins will force al each regulation hods lator with the r and connect her regulators same ratio as 4 for values). t Z Family Datashe s e l n e l l e e d A s t r t s l n e t s s Figu All co with demo shou toget Indu The indu c perfo value devic Coiltr eet Rev ure 6 ‐ Voltage d onnected regu this metho onstrated in Fi uld have the ther to work p uctor Pairing PI33XX utiliz ctor has been ormance. Tabl e and part n ce and are m ronics. Device PI3311‐X0‐LGIZ PI3312‐X0‐LGIZ PI3301‐X0‐LGIZ PI3302‐X0‐LGIZ PI3303‐X0‐LGIZ PI3305‐X0‐LGIZ Table 5 PI S ulators’ soft‐st od. Direct t igure 5 (b). Al ir Enable (EN properly. zes an exter optimized for le 5 details th number utilize manufactured b Inductor [nH] 120 200 200 200 230 230 ‐ PI33XX Inducto Master VO R R SGND TRK I33XX Slave N) pins conn rnal inductor. maximum effi he specific ind ed for each P by Cooper Bu Inductor Part Number TBD‐120‐R FPT705‐200‐R FPT705‐200‐R FPT705‐200‐R FPT705‐230‐R FPT705‐230‐R or pairing OUT 34 of 39 acking l track ng is ulators nected . This ciency ductor PI33XX ssman R R R R R
converter, average c replenishin been chose Device VIN PI3311 PI3312 PI3301 PI3302 PI3303 PI3305 ration • picorpo d Output Filte X requires inp as low impe to ensure p decoupling f ll draw nearly om the low im main high s e time the high d from the b e is high at the the bulk capa current into ng the cerami en to be 100µF N ILOAD (A) CINPU Bulk Elec 4 10 100µ 50V 4 10 100µ 50V 10 100µ 50V5 4 10 100µ 50V 4 8 100µ 50V 4 8 100µ 50V MURATA PAR GRM188R71C GRM319R71H GRM31CR60J ower.com er Considerat put bulk storag dance ceram proper start for the powe y all of the h mpedance cera ide MOSFET side MOSFET bulk capacitor e switching fre acitor must su the convert c capacitors. T F so that the P UT k CINPUT Ceramic X5R µF V 4X4.7µF 50V µF V 4X4.7µF µF V 4X4.7µF µF V 4X4.7µF µF V 4X4.7µF µF V 4X4.7µF Table RT NUMBER C105KA12D 1 H104KA01D 0 107ME39L 1 Ta PI33XX‐X0‐LGIZ tions ge capacitance ic X5R input up and high er stage. The high frequency mic capacitors is conducting is off, they are r. If the input equency of the pply all of the ter, including This value has I33XX can COUTPUT Ceramic X5R CINP Ripp Curre (IRM 8X100µF 2X1 µF 1X0.1 µF 0.5 4X100µF 2X1 µF 1X0.1 µF 4X100µF 2X1 µF 1X0.1 µF 1.0 4X100µF 2X1 µF 1X0.1 µF 1.2 4X22µF 2X1 µF 1X0.1 µF 1.3 4X22µF 2X1 µF 1X0.1 µF 1.3 6 ‐ Recommend 0.1uF 50V 1206 X 100uF 6.3V 1206 ble 7 ‐ Capacitor Z Family Datashe e t h e y s e t e e g s start outp soft impe capa rippl e not b capa reco m used tran s capa Tabl e ceram PUT ple ent MS) COUTPUT Ripple Current (IRMS) 5 0.8 1.75 05 1.625 2 1.5 3 1.36 8 1.2 ded input and ou N MURATA R GRM31C X7R GRM31C
6 X5R GRM31C
citor, and inp e 7 includes th mic capacitors Input Ripple (mVpp) Outpu Rippl (mVpp 120 20 100 15 150 50 100 24 200 40 125 33 220 50 140 30 275 100 150 60 280 150 160 75 utput capacitanc A PART NUMBE CR71H475KA12K CR61A476ME15 CR61E226KE15L part numbers used. Table put and outpu ous models a se, RMS rip put and outp he recommend ut e Transient Deviation (mVpk) ‐/+40 ‐/+80 ‐/+100 ‐/+170 ‐/+300 ‐/+400 ce ER DESCRIP K 4.7uF 50V 1 L 47uF 10V 1 22uF 25V 1 Hz. The ESR fo ely 20mΩ. The s small, so it s commended ce e 6 shows ut capacitors as well as exp pple currents put ripple vol ded input and o Recovery Time (µs) L S (Sle 40 (5 25 (10 20 (10 30 (5 30 (10 30 (10 PTION
1206 X7R
206 X5R
ltages. output Load Step (A) ew/µs) A/µs) 0A/µs) 0A/µs) A/µs) 0A/µs) 0A/µs)
below. The path b particular flowing thr Figure 10, length bet shorter pa parasitics c Fig ration • picorpo Guidelines ze maximum nce from a tions are n and minimizin proper compo esistance and i buck converter tial areas of h are the circui Figure 9 ‐ Typi between the C importance s rough both of t schematically tween input a ath lessens th can have on th gure 10 ‐ Curren ower.com s efficiency and PI33XX de ecessary. Re ng high curren onent placeme nductance. r circuit is show igh parasitic in t return paths ical Buck Conver OUT and CIN c since the AC them when Q1 y, shows the and output ca e effects that e PI33XX perfo nt flow: Q1 close PI33XX‐X0‐LGIZ d a low noise esign, layout educing trace nt loop returns ent will reduce wn in Figure 9 nductance and s, shown as LR rter capacitors is of currents are 1 is turned on. reduced trace apacitors. The t copper trace ormance. ed Z Family Datashe e t e s e d R f e e e e Whe curre to re and induc CIN i induc when betw minim The r Figur COUT curre used eet Rev n Q1 is on an ent is used to echarge the C Q2 is on, the ctor and the C s also being re ctance is imp n Q1 turns o ween the CIN mize switching Figure 11 recommended re 11, illustrate T (and VIN an ent. This optim on the PI33XX Figure 12 ‐ placem nd Q2 is off, th satisfy the sta OUT capacitor e load current COUT capacito echarged by th ortant to min ff. Also, the loop and CO g and GND nois 1 ‐ Current flow: d component p es the tight pa nd VOUT) for mized layout X evaluation bo ‐ Recommended ment and metal rs. When Q1 t is supplied b r. During this p e VIN. Low CIN nimize peak v e difference in OUT loop is vi se. : Q2 closed placement, sho ath between CI the high AC is the same t oard. d component routing 36 of 39 f CIN’s ad and is off by the period N loop voltage n area ital to own in IN and return that is
1mm grid. ration • picorpo mended PC 3 details the re pper size of 0.5 All stencil ope ower.com CB Footpri Figu commended r 55mm x 0.55m enings are 0.55 PI33XX‐X0‐LGIZ int and Ste ure 13 ‐ Recomm receiving footp mm, whether t 5mm when usi Z Family Datashe encil ended Receiving print for PI33XX they are solde ng a 6mil sten eet Rev g PCB footprint. X 10mm x 14m er‐mask define cil. mm package. A ed or copper d defined, on a 1 37 of 39 d have 1mm x
ration • picorpo e Drawing ower.com s PI33XX‐X0‐LGIZ Z Family Datashe eet Rev SY MBOL M A 2 b 0 L 0 D E e L1 0 aaa bbb ccc ddd eee 2.50 2.56 -- -- -- -- 0.50 0.55 0.50 0.55 0.1 0 0.1 5 1 4.00 BSC 1 0.00 BSC 1 3.00 BSC
9.00 BSC
1 .00 BSC 2.62 0.05 2.57 0.60 0,60 0.20 0.1 0 0.1 0 0.08 0.1 0 0.08 38 of 39
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25 Fron
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