PI2EQX5864 PERICOM | Alldatasheet

Document overview

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  • PDF pages: 18

Technical content

Features

  • Up to 5.0Gbps PCI Express Gen-2 Serial Re-driver
  • Supporting 8 differential channels or 4 lanes of PCIe Interface
  • I 2C confi guration controls (3.3V Tolerant)
  • Adjustable receiver equalization and transmitter de-emphasis and output levels
  • Variable input an output termination
  • 1:2 channel broadcast
  • Channel loop-back
  • Electrical Idle fully supported
  • Receiver detect and individual output control
  • Single supply voltage, 1.2V ± 0.05V
  • Power down modes
  • Packaging: 56-contact TQFN, Pb-free & Green

Description

Pericom Semiconductor’s PI2EQX5864 is a low power, PCI-express compliant signal re-driver. The device provides programmable equalization, amplifi cation, and de-emphasis by using 8 select bits, to optimize performance over a variety of physical mediums by reducing Inter-symbol interference. PI2EQX5864 supports eight 100-Ohm Differential CML data I/O’s between the Protocol ASIC to a switch fabric, across a backplane, or extends the signals across other distant data pathways on the user’s platform. The integrated equalization circuitry provides fl exibility with signal integrity of the PCI-express signal before the re-driver, whereas the integrated de-emphasis circuitry provides fl exibility with signal integrity of the signal after the re-driver. In addition to providing signal re-conditioning, Pericom’s PI2EQX5864 also provides power management Stand-by mode operated by a Bus Enable pin. Pin Confi guration 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 VDD A0RX+ A0RX- B0TX+ B0TX- VDD A1RX+ A1RX- B1TX+ B1TX- VDD A2RX+ A2RX- B2TX+ B2TX- VDD A3RX+ A3RX- B3TX+ B3TX- A0TX+ A0TX- VDD B0RX+ B0RX- A1TX+ A1TX- VDD B1RX+ B1RX- A2TX+ A2TX- VDD B2RX+ B2RX- VDD A3TX+ A3TX- B3RX+ B3RX- VDD RXD_B MODE RES_B# LB# GND GND RES_A# SCL SDA PRSNT2# RXD_A VDD A B xyRx+ xyRx- xyTx+ xyTx- xxTx- xxTx+ xyRx+ xyRx- Equalizer Equalizer Input/nonmarkingreturnlevel/nonmarkingreturndetect to/nonmarkingreturncontrol/nonmarkingreturnlogic Output Controls Output Controls Input/nonmarkingreturnlevel/nonmarkingreturndetect to/nonmarkingreturncontrol/nonmarkingreturnlogic Data/nonmarkingreturnLane/nonmarkingreturnRepeats/nonmarkingreturn4/nonmarkingreturnTimes Control/nonmarkingreturnregisters &/nonmarkingreturnlogic Power Management I2C/nonmarkingreturnControl SDA SCL Mode LB# RES_x RXD_x Ax 07-0277

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5.0Gbps 4-Lane PCI Express GenII Re-Driver with Equalization, Emphasis and I2C Control Pin Description Pin # Pin Name Type Description Data Signals A0RX+, A0RX- I I CML inputs for Channel A0, with internal 50-Ohm pull down during normal operation, and >200K-Ohm otherwise. A0TX+, A0TX- O O CML outputs for Channel A0, with internal 50-Ohm pull up during normal opera- tion and 2K-Ohm pull up otherwise. A1RX+, A1RX- I I CML inputs for Channel A1, with internal 50-Ohm pull down during normal operation, and >200K-Ohm otherwise. A1TX+, A1TX- O O CML outputs for Channel A1, with internal 50-Ohm pull up during normal opera- tion and 2K-Ohm pull up otherwise. A2RX+, A2RX- I I CML inputs for Channel A2, with internal 50-Ohm pull down during normal operation, and >200K-Ohm otherwise. A2TX+, A2TX- O O CML outputs for Channel A2, with internal 50-Ohm pull up during normal opera- tion and 2K-Ohm pull up otherwise. A3RX+, A3RX- I I CML inputs for Channel A3 with internal 50-Ohm pull down during normal operation, and >200K-Ohm otherwise. A3TX+, A3TX- O O CML outputs for Channel A3, with internal 50-Ohm pull up during normal opera- tion and and 2K-Ohm pull up otherwise. B0RX+, B0RX- I I CML inputs for Channel B0, with internal 50-Ohm pull down during normal operation, and >200K-Ohm otherwise. B0TX+, B0TX- O O CML outputs for Channel B0, with internal 50-Ohm pull up during normal opera- tion and 2K-Ohm pull up otherwise. B1RX+, B1RX- I I CML inputs for Channel B1, with internal 50-Ohm pull down during normal operation, and >200K-Ohm otherwise. B1TX+, B1TX- O O CML outputs for Channel B1, with internal 50-Ohm pull up during normal opera- tion and 2K-Ohm pull up otherwise. B2RX+, B2RX- I I CML inputs for Channel B2, with internal 50-Ohm pull down during normal operation, and >200K-Ohm otherwise. B2TX+, B2TX- O O CML outputs for Channel B2, with internal 50-Ohm pull up during normal opera- tion and 2K-Ohm pull up otherwise. B3RX+, B3RX- I I CML inputs for Channel B3, with internal 50-Ohm pull down during normal operation, and >200K-Ohm otherwise. B3TX+, B3TX- O O CML outputs for Channel B3, with internal 50-Ohm pull up during normal opera- tion and 2K-Ohm pull up otherwise. Control Signals 26, 27, 25 A0, A1, A4 I I2C programmable address bit A0, A1 and A4. 28 LB# I Loopback control input. Input with innernal 100K-Ohm oull-up resistor. LB# = High or open for normal operation. LB# = Low for loopback connection of A_RX to A_TX and B_TX. 23 Mode I Enables I2C control when LOW. Has internal 100K-Ohm pull-up resistor. A LVCMOS high level selects input pins control, and disables I 2C operation. Note, during startup, input status of the control pin (LB#, RES_A/B#, RXD_A/B) will be latched to set the initial register state.

51 PRSNT2# I Input with internal 100K-Ohm pull-up resistor, card present is an active low

signal to indicate the existence of a receiver, and will enable all channels, need to tie low for normal operation. (Continued on Next Page) 07-0277

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5.0Gbps 4-Lane PCI Express GenII Re-Driver with Equalization, Emphasis and I2C Control

54 RES_A# I RES_A# is an active low channel reset input for Channel A0, A1, A2 and A3 with

internal 100K-Ohm pull-up resistor. When low, receiver detection cycle is reset, and normal detection cycle is carry on after the pin goes high.

24 RES_B# I RES_B# is an active low channel reset input for Channel B0, B1, B2 and B3 with

internal 100K-Ohm pull-up resistor. When low, receiver detection cycle is reset, and normal detection cycle is carry on after the pin goes high.

50 RXD_A I Receiver detect enable input for Channel A0, A1, A2 and A3 with internal 100K-

Ohm pull-up resistor.

22 RXD_B I Receiver detect enable input for Channel B0, B1, B2 and B3 with internal 100K-

Ohm pull-up resistor. 53 SCL I/O I 2C SCL clock input. Up to 3.3V input tolerance. 52 SDA I/O I 2C SDA data input. Up to 3.3V input tolerance 55, 56, Center Pad GND PWR Supply Ground 34, 39, 44, 49 VDD PWR 1.2V Supply V oltage DESCRIPTION of OPERATION Confi guration Modes Device confi guration can be performed in two ways depending on the state of the MODE input. MODE determines whether IC confi guration status is from the input pins or via I2C control. When MODE is set high, the confi guration input pins set the confi gura- tion operating state as stored in confi guration registers. While MODE is set high, changes to these control registers are disabled and the initial condition is protected from any changes to insuring a known operating state. When the MODE pin is low, reprogramming of these control registers via I2C is allowed. Note that the MODE pin is not latched, and is always active to enable or disable I2C access. During initial power-on, the value at the confi guration input pins: LB#, RES_A#, RES_B#,RXD_A and RXD_B, will be latched to the confi guration registers as initial startup states. Equalizer Confi guration The PI2EQX5864 input equalizer compensates for signal attenuation and Inter-Symbol Interference (ISI) resulting from long signal traces or cables, vias, signal crosstalk and other factors, by boosting the gain of high-frequency signal components. Because either too little, or too much, signal compensation may be non-optimal eight levels are provided to adjust for any application. Equalizer confi guration can be programmed via I 2C when the mode pin is low. Each group of four channels, A and B, has separate equalization control, and all four channels within the group are assigned the same confi guration state. The Equalizer Selection table below describes the register state and associated operation of the equalizer. Equalizer Selection SEL2_[A:B] SEL1_[A:B] SEL0_[A:B] @1.25GHz @2.5GHz 0 0 0 0.5dB 1.2dB 0 0 1 0.6dB 1.5dB 0 1 0 1.0dB 2.6dB 0 1 1 1.9dB 4.3dB 1 0 0 2.8dB 5.8dB 1 0 1 3.6dB 7.1dB 1 1 0 5.0dB 9.0dB 1 1 1 7.7dB 12.3dB 07-0277

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5.0Gbps 4-Lane PCI Express GenII Re-Driver with Equalization, Emphasis and I2C Control Output Confi guration The PI2EQX5864 provides fl exible output strength and emphasis controls to provide the optimum signal to pre-compensate for losses across long trace or noisy environments so that the receiver gets a clean with good eye opening. Control of output confi gura- tion is grouped for the A and B channels, so that each channel within the group has the same setting. Output confi guration can be set via I2C when the mode pin is LOW. The Output Swing Control table shows available confi guration settings for output level control, as specifi ed by the SELx_y registers. Output Swing Control S1_[A:B] S0_[A:B] Swing (Diff. VPP) 001 V 0 1 0.5V 1 0 0.7V 1 1 0.9V Output De-emphasis Adjustment D2_[A:B] D1_[A:B] D0_[A:B] De-emphasis 0000 dB 0 0 1 -2.5dB 0 1 0 -3.5dB 0 1 1 -4.5dB 1 0 0 -5.5dB 1 0 1 -6.5dB 1 1 0 -7.5dB 1 1 1 -8.5dB Emphasis settings are determined by the state of the Dx_y input pins and confi guration registers, as shown below. De-Emphasis is selected as the default power-on mode in following the PCI Express specifi cation, but can be changed to Pre-emphasis via repro- gramming the Loopback and Emphasis Control register using the I2C interface. Card Present Function The PRSNT2# input allows direct control of the number of active lanes using the PRSNT2# signal from a PCI Express connector or cable. PRSNT2# is a level sensitive input pin, and controls both directions of the receiver detect function. The receiver detect state machine is only active when PRSNT2# is low, otherwise, the input termination will be high-impedance and output termination will be 2K-Ohm. See the I/O operation table for more information. Input Level Detect An input level detect and output squelch function is provided on each channel to eliminate re-transmission of input noise. A continu- ous signal level below the Vth- threshold causes the output driver to go to a high-impredance state, so that both the positive and nega- tive output signal are pulled to VDD by the internal pull-up resistors. This feature supports L0S PCI Express Electrical Idle state. 07-0277

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5.0Gbps 4-Lane PCI Express GenII Re-Driver with Equalization, Emphasis and I2C Control Receiver Detect Automatic Receiver Detection is a feature that can set the number of active channels. By sensing the presence of a load device on the output, the channel can be automatically enabled for operation. This allows the PI2EQX5864 to confi gure itself properly depending on the devices it is communicating with, whether it is a 4-lane, 3-lane, 2-lane or just 1-lane device or adapter card. Receiver Detect is enabled by the RXD_A, or RXD_B pins, or alternatively via I2C programming. When RXD_A or RXD_B is set to low, the Receiver Detect operation for that group of channels is disabled, and those channels go directly to 50-Ohm input termi- nation to ground and 50-Ohm output termination to Vdd (for a valid differential channel input level) or to 2K-Ohm (if the signal level is less than the threshold level). The RES_A#, and RES_B# inputs are used to reset the receiver detect state machine to its initial state. RES_A# and RES_B# control the received detect reset for the A and B group of channels respectively. The start of the receiver detect cycle starts when RES_A# or RES_B# transitions from low to high. When a Receiver Detect cycle begins the differential channel pins are enabled with a 2K-Ohm pullup to Vdd. A 50-Ohm Receiver termination will change the pin level. This pin level is evaluated after a fi xed time-out, and the channel is then set into the proper operating state. The register bits RX50_Ax and RX50_Bx represent the receiver detect result for their specifi c channels. The I/O operation table summarizes the relationships and operation of receiver detect and other signals involved with I/O control. I/O Operation Control Control Inputs Detection States Data Channel I/O PD# PRSNT2# RXD_x RES_x# RX50 SIG_x Input Termination Output Termination Mode

0 X X X X X Hi-Z Hi-Z Full IC power down, all chan-

1 1 X X X X Hi-Z Hi-Z No receiver (defi ned by PRSNT2#), all channels disabled 1 0 0 0 X X Hi-Z 2K-Ohm pull-up Channel disabled, output pulls to Vdd. Receiver detect reset 1 0 0 1 X 0 50-Ohm pull- down 2K-Ohm pull-up Channel enabled, no input signal, output pulls to Vdd. Receiver detect disabled 1 0 0 1 X 1 50-Ohm pull- down 50-Ohm pull-up Channel enabled, valid input signal detected, output driv- ing. Receiver detect disabled. 1 0 1 0 X X Hi-Z 2K-Ohm pull-up Channel disabled. Receiver detect reset. 1 0 1 1 0 X Hi-Z 2K-Ohm pull-up Channel disabled, output pulls to Vdd. Receiver detect enabled, no receiver detected. 1 0 1 1 1 0 50-Ohm pull- down 2K-Ohm pull-up Channel inactive, output pulls to Vdd. Receiver detect en- abled, receiver detected. No input signal 1 0 1 1 1 1 50-Ohm pull- down 50-Ohm pull-up Channel active, valid input signal detected, output driv- ing. Receiver detect enabled, load detected. 07-0277

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5.0Gbps 4-Lane PCI Express GenII Re-Driver with Equalization, Emphasis and I2C Control Mux Function Solid: LB_A0B0#=1 Dashed: LB_A0B0#=0 Demux Function Solid: LB=0 Dashed: LB=1 Normal Operation Loopback Mode LB#=0 LB#=1 ODIS_AO = 1 INDIS_BO = 1 Loopback Modes Loopback Operation Each lane of the 5864 provides a loopback mode for test purposes which is controlled by a strapping pin and I2C register bit. The LB# pin controls all lanes together. When this pin is high normal data mode is enabled. When LB# is low the loopback mode is enabled. The fi gure below diagrams this operation. Loopback is not intended to be dynamically switched, and the normal system application is to initialize to one confi guration or the other. The Loopback mode can also support mux/demux operation. Using I2C confi guration, unused inputs and outputs can be disabled to minimize power and unnecessary noise. I2C Operation The 5806 I2C controller operates as a slave device, supporting standard rate operation of 100Kbps, with 7-bit addressing mode, with support for offset byte-write and read. The data byte format is 8 bit bytes. The bytes must be accessed in sequential order from the lowest to the highest byte with the ability to stop after any complete byte has been transferred. Address bits A4, A1 and A0 are pro- grammable to support multiple chips environment. The data is loaded until a Stop sequence is issued. Note that the I2C inputs, SCL and SDA operate at 1.2V logic levels and are 3.3V tolerant. 07-0277

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5.0Gbps 4-Lane PCI Express GenII Re-Driver with Equalization, Emphasis and I2C Control Confi guration Register Summary Byte Mnemonic Function

0 SIG Signal Detect, indicates valid input signal level

1 RX50 Receiver Detect Output, indicates whether a receiver load was detected

2 LBEC Loopback and Emphasis Control, provides for control of the loopback function and emphasis mode (pre- emphasis or de-emphasis)

3 INDIS Channel Input Disable, controls whether s channels input buffer is enabled or disabled

4 OUTDIS Channel Output Disable: Controls whether a channels output buffer is enabled or disabled

5 RESET Channel Reset

6 PWR Power Down Control, enables power down for each channel individually

7 RXDE Receiver Detect Enable, controls the receiver detect operation

8 AEOC A-Channels Equalizer and Output Control

9 BEOC B-Channels Equalizer and Output Control

10 RSVD Reserved

11 RSVD Reserved

Byte 0 - Signal Detect (SIG) SIG_xy=0=low input signal, SIG_xy=1=valid input signal Bit 7 6 5 4 3 2 1 0 Name SIG_A0 SIG_B0 SIG_A1 SIG_B1 SIG_A2 SIG_B2 SIG_A3 SIG_B3 Type R R R R R R R R Power-on State XX X X X XX X Note: R=Read only, W=Write only, R/W=Read and Write, X=Undefi ned, rsvd=reserved for future use The Signal Detect register provides information on the instantaneous status of the channel input from the Input Level Threshold Detect circuit. If the input level falls below the Vth- level the relevant SIG_xy bit will be 0, indicating a low-level noise or electri- cal idle input, resulting in the outputs going to the high-impedance off state or squelch mode. If the input level is above Vth-, then SIG_xy is 1, indicating a valid input signal, and active signal recovery operation. Byte 1 - Receiver Detect Output Register (RX50) RX50_xy = 1 = load detected, RX50_xy = 0 = No reciever found Bit 7 6 5 4 3 2 1 0 Name RX50_A0 RX50_B0 RX50_A1 RX50_B1 RX50_A2 RX50_B2 RX50_A3 RX50_B3 Type R R R R R R R R Power-on State XXX X XXXX Note: R=Read only, W=Write only, R/W=Read and Write, X=Undefi ned, rsvd=reserved for future use The RX50_xy bits report the result of a receiver detection cycle. One bit is assigned for each channel of the device. RX50_xy is at a logic 1 level indicating a load and receiver was detected. When RX50_xy is 0 then a load device was not detected. The RX50 register is read-only, and is undefi ned after power-up until a Receiver Detection cycle completes. 07-0277

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5.0Gbps 4-Lane PCI Express GenII Re-Driver with Equalization, Emphasis and I2C Control BYTE 3 - Channel Input Disable (INDIS) INDIS_xy=0=enable input, INDIS_xy=1=disable input Bit 7 6 5 4 3 2 1 0 Name INDIS_A0 INDIS_B0 INDIS_A1 INDIS_B1 INDIS_A2 INDIS_B2 INDIS_A3 INDIS_ Type R/W R/W R/W R/W R/W R/W R/W R/W Power-on State 000000 0 0 Note: R=Read only, W=Write only, R/W=Read and Write, X=Undefi ned, rsvd=reserved for future use The Channel Input Disable register, provides control over the input buffer of each channel independently. When and INDIS_xy bit is logic 1, then the input buffer is switched off and the input termination is high impedance. This feature can be used for PCB testing, and when only one input is used during Loopback as a demux function. When INDIS_xy is at a logic 0 state then the input buffer is enabled (normal operating mode). BYTE 4 - Channel Output Disable (OUTDIS) ODIS_xy=0=enable output, ODIS_xy=1=disable output Bit 7 6 5 4 3 2 1 0 Name ODIS_A0 ODIS_B0 ODIS_A1 ODIS_B1 ODIS_A2 ODIS_B2 ODIS_ ODIS_ Type R/W R/W R/W R/W R/W R/W R/W R/W Power-on State 00 0 0 0 0 0 0 Note: R=Read only, W=Write only, R/W=Read and Write, X=Undefi ned, rsvd=reserved for future use The Channel Output Disable register, allows control over the output buffer of each channel independently. When and OUTDIS_xy bit is logic 1, then the output buffer is switched off and the termination is high impedance. This feature can be used for PCB testing, and when only one output is used during Loopback as a mux function. When INDIS_xy is at a logic 0 state then the input buffer is enabled (normal operating mode). Byte 2 - Loopback and Emphasis Control Register (LBEC) LB_xyxy#=0=loopback mode, LB_xyxy#=1=normal mode, DE_x=0=pre-emphasis, DE_x=1=de-emphasis Bit 7 6 5 4 3 2 1 0 Name LB_A0B0# LB_A1B1# LB_A2B2# LB_A3B3# DE_A DE_B rsvd rsvd Type R/W R/W R/W R/W R/W R/W R R Power-on State LB# LB# LB# LB# 1 1 X X Note: R=Read only, W=Write only, R/W=Read and Write, X=Undefi ned, rsvd=reserved for future use Individual control for each lane is provided for the loopback function via this register. 07-0277

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5.0Gbps 4-Lane PCI Express GenII Re-Driver with Equalization, Emphasis and I2C Control BYTE 6 - Power Down Control (PWR) PD_xy# =0=channel off/power down, PD_xy# =1=normal operation, Latch from PD# input at startup Bit 7 6 5 4 3 2 1 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Power-on State 11111 11 1 Note: R=Read only, W=Write only, R/W=Read and Write, X=Undefi ned, rsvd=reserved for future use The Power Down Control register allows for individual control over each channel for power savings. When PD_xy# is logic 0 the channel is turned off. When PD_xy# is 1 then the channel is enabled for normal operation. BYTE 7 - Receiver Detect Enable (RXD) RXD_xy =0=channel off/power down, RXD_xy =1=normal operation, Latch from PD# input at startup Bit 7 6 5 4 3 2 1 0 Name RXD_A0 RXD_B0 RXD_A1 RXD_B1 RXD_A2 RXD_B2 RXD_A3 RXD_B3 Type R/W R/W R/W R/W R/W R/W R/W R/W Power-on State 11 1 1 1 1 11 Note: R=Read only, W=Write only, R/W=Read and Write, X=Undefi ned, rsvd=reserved for future use The Receiver Detect Enable register allows for control of the receiver detect state machine for each individual channel. When RXD_xy is set to 0, then the receiver detect function is disabled. When RXD_xy is logic 1, then the receiver detect state machine is enabled for operation. The initial state of the register bits are determined by the RXD_A and RXD_B input pins during power-up. BYTE 8 - A-Channels Equalizer and Output Control (AEOC) SELx_A: Equalizer confi guration, Dx_A: Emphasis control, Sx_A: Output level control (see Confi guration Table) Bit 7 6 5 4 3 2 1 0 Name SEL0_A SEL1_A SEL2_A D0_A D1_A D2_A S0_A S1_A Type R/W R/W R/W R/W R/W R/W R/W R/W Power-on State 11 1 1 1 1 11 Note: R=Read only, W=Write only, R/W=Read and Write, X=Undefi ned, rsvd=reserved for future use BYTE 5 - Channel Reset (RESET) RES_xy# =0=reset, RES_xy# =1=normal operation. Latch from RES_A# & RES_B# inputs at startup Bit 7 6 5 4 3 2 1 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Power-on State 11111 11 1 Note: R=Read only, W=Write only, R/W=Read and Write, X=Undefi ned, rsvd=reserved for future use The Channel Reset register allows for restart of an individual channels Receiver Detect function. A transition from 0 to 1 initiates a new Receiver Detect cycle (if the channel is enabled and receiver detect is enabled). While static at 0 or 1, the RES_zy# bit will have no effect on operation. The Channel Reset bits are read/write allowing the current state to be checked. 07-0277

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5.0Gbps 4-Lane PCI Express GenII Re-Driver with Equalization, Emphasis and I2C Control The A-Channels Equalizer and Output Control register is used to control the confi guration of the input equalizer and output emphasis and levels of the four A channels. These register bits are loaded from the input confi guration pins of the same name at power-on. These bits may be changed if the MODE# input is set to allow I2C confi guration. Please refer to the tables (1) Equalizer Confi gura- tion, (2) Output Swing Confi guration and (3) Output Emphasis Confi guration earlier in this document for setting information. All four A channels get the same confi guration settings. BYTE 9 - B-Channels Equalizer and Output Control (BEOC) SELx_B: Equalizer confi guration, Dx_B: Emphasis control, Sx_B: Output level control (see Confi guration Table) Bit 7 6 5 4 3 2 1 0 Name SEL0_B SEL1_B SEL2_B D0_B D1_B D2_B S0_B S1_B Type R/W R/W R/W R/W R/W R/W R/W R/W Power-on State 11 1 1 1 1 11 Note: R=Read only, W=Write only, R/W=Read and Write, X=Undefi ned, rsvd=reserved for future use The B-Channels Equalizer and Output Control register is used to control the confi guration of the input equalizer and output emphasis and levels of the four B channels. These register bits are loaded from the input confi guration pins of the same name at power-on. These bits may be changed if the MODE# input is set to allow I2C confi guration. Please refer to the tables (1) Equalizer Confi gura- tion, (2) Output Swing Confi guration and (3) Output Emphasis Confi guration earlier in this document for setting information. All four B channels get the same confi guration settings. BYTE 10 - Reserved BYTE 11 - Reserved Reserved Bytes 10 and 11 are also visible via the I2C interface. These bytes are R/W, are initialized to 0 at power up, are used for IC manufacturing test purposes and should not be changed for normal operation. I C2 Start & Stop Conditions A HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition. A LOW to HIGH transition on the SDA line while SCL is HIGH defi nes a STOP condition, as shown in the fi gure below. 07-0277

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5.0Gbps 4-Lane PCI Express GenII Re-Driver with Equalization, Emphasis and I2C Control 1./nonmarkingreturnRead/nonmarkingreturnsequencestart R/nonmarkingreturn//nonmarkingreturnW ACK ACK ACK NO/nonmarkingreturnACK stop DEV/nonmarkingreturnSEL DATA/nonmarkingreturnOUT DATA/nonmarkingreturnOUT/nonmarkingreturnN ACK ACK ACK DATA/nonmarkingreturnIN/nonmarkingreturnNDATA/nonmarkingreturnIN/nonmarkingreturn1 ACKACK R/nonmarkingreturn//nonmarkingreturnW start stop 2./nonmarkingreturnWrite/nonmarkingreturnsequence 3./nonmarkingreturnCombined/nonmarkingreturnsequence DUMMY/nonmarkingreturnBYTEACKACK R/nonmarkingreturn//nonmarkingreturnW start DATA/nonmarkingreturnOUT/nonmarkingreturn1 ACKACK R/nonmarkingreturn//nonmarkingreturnW start ACK NO/nonmarkingreturnACKDATA/nonmarkingreturnOUT/nonmarkingreturnN stop Notes: 1. only block read and block write from the lowest byte are supported for this application. 2. for some I2C application, an offset address byte will be presented at the second byte in write command, which is called dummy byte here and will be simply ignored in this application for correct interoperation. PI2EQX5864 I C Master2 PI2EQX5864 DEV/nonmarkingreturnSELDUMMY BYTE DEV/nonmarkingreturnSEL DEV/nonmarkingreturnSEL PI2EQX5864 I C Master2 PI2EQX5864 I C Master2 I2C Data Transfer 07-0277

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5.0Gbps 4-Lane PCI Express GenII Re-Driver with Equalization, Emphasis and I2C Control Maximum Ratings (Above which useful life may be impaired. For user guidelines, not tested.) DD +0.5V AC/DC Electrical Characteristics Power Supply Characteristics (VDD = 1.2 ±0.05V , TA = 0 TO 70°C) Symbol Parameter Conditions Min. Typ. Max. Units IDDactive Power supply current - active All channels switching 800 mA IDDstandby Power supply current - standby PD_xy# all 0 5 10. mA I DD-channel Power supply current - per channel, Active 50 mA AC Performance Characteristics (VDD = 1.2 ±0.05V , TA = 0 TO 70°C) Symbol Parameter Conditions Min. Typ. Max. Units Tpd Channel latency from input to output 750 ps CML Receiver Input (VDD = 1.2 ±0.05V , TA = 0 TO 70°C) Symbol Parameter Conditions Min. Typ. Max. Units ZRX-DIFF- DC DC Differential Input Impedance 80 100 120 Ohms ZRX-DC DC Input Impedance 40 50 60 Ohms VRX-DIFFP- P Differential Input Peak-to-peak V oltage 0.175 1.200 V VRX-CM- ACP AC Peak Common Mode Input V oltage 150 mV Vth- Signal detect thresh- old voltage 100 150 mV Note: Stresses greater than those listed under MAX I MUM RAT- INGS may cause permanent damage to the de vice. This is a stress rating only and func tion al op er a tion of the device at these or any other conditions above those indicated in the operational sections of this spec i fi ca tion is not implied. Exposure to absolute max i mum rating con di tions for ex- tended periods may affect re li abil i ty. 07-0277

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5.0Gbps 4-Lane PCI Express GenII Re-Driver with Equalization, Emphasis and I2C Control Equalizer Symbol Parameter Conditions Min. Typ. Max. Units JRS-T Residual jitter Total 0.3 Ulp-p JRS-D Residual jitter Deterministic 0.2 Ulp-p JRM Random jitter Note 2 1.5 psrms Notes 1. K28.7 pattern is applied differentially at point A as shown in AC test circuit (see fi gure). 2. Total jitter does not include the signal source jitter. Total jitter (TJ) = (14.1 × RJ + DJ) where RJ is random RMS jitter and DJ is maximum deter- ministic jitter. Signal source is a K28.5 ± pattern (00 1111 1010 11 0000 0101) for the deterministic jitter test and K28.7 (0011111000) or equivalent for random jitter test. Residual jitter is that which remains after equalizing media-induced losses of the environment of Figure 1 or its equivalent. The deterministic jitter at point B must be from media-induced loss, and not from clock source modulation. Jitter is measured at 0V at point C of the AC test circuit (see fi gure). CML Transmitter Output (VDD = 1.2V ± 0.05V , TA = 0 to 70°C) Symbol Parameter Conditions Min. Typ. Max. Units ZOUT Output resistance Single ended 40 50 60 Ohms ZTX-DIFF-DC DC Differential TX Impedance 80 100 120 Ohms VDIFFP Output V oltage Swing, Differential |VTX-D+ - VTX-D-| 200 1000 mVp- p V TX-DIFFP-P Differential Peak-to- peak Ouput V oltage VTX-DIFFP-P = 2 * | VTX- D+ - VTX-D- | 0.4 2.0 V V TX-C Common-Mode V oltage | VTX-D+ + VTX-D- | / 2 VDD- 0.3 V t F, tR Transition Time 20% to 80% (3) 150 ps CTX(1) AC Coupling Capacitor 75 200 nF Notes: 1. Recommended external coupling capacitor. Digital I/O DC Specifi cations (VDD = 1.2V ± 0.05V , TA = 0 to 70°C) Symbol Parameter Conditions Min. Typ. Max. Units VIH DC input logic high VDD/2 +0.2 VDD+0.3 V VIL DC input logic low -0.3 VDD/2 -0.2 V VOH DC output logic high I OH = 4mA VDD- 0.4 V V OL DC output logic low I OL = 4mA 0.4 V Vhys Hysteresis of Schmitt trigger input 0.2 V I IH(1) Input high current 250 uA IIL1(2) Input low current -250 uA IIL2(3) Input low current -500 uA Notes: 1. Includes input signals A1, A2, A4, LB#, MODE#, PRSNT2#, RES_[A:B]#, RXD_[A:B], SCL, SDA 2. For control inputs without pullups: A1, A2, A4, SCL, SDA 3. Control inputs with pull-ups include: LB#, MODE#, PRSNT2#, RES_[A:B]#, RXD_[A:B] 07-0277

14 PS8934A 01/21/08

5.0Gbps 4-Lane PCI Express GenII Re-Driver with Equalization, Emphasis and I2C Control SDA and SCL I/O for I2C-bus (VDD = 1.2 ± 0.05v, TA = 0 to 70°C) Symbol Parameter Conditions Min. Typ. Max. Units VIH DC input logic high 1.1 3.6 V VIL DC input logic low -0.3 0.7 V VOL DC output logic low IOL = 3mA 0.4 V Vhys Hysteresis of Schmitt trigger input 0.2 V Characteristics of the SDA and SCL bus lines for F/S-mode I2C-bus devices(1) Symbol Parameter Conditions Min. Typ. Max. Unit fSCL SCL clock frequency 0 100 kHz tHD;STA Hold time (repeated) START condition. After this period, the fi rst clock pulse is generated 4.0 – μs tLOW LOW period of the SCL clock 4.7 – μs tHIGH HIGH period of the SCL clock 4.0 – μs tSU;STA Set-up time for a repeated START condition 4.7 – μs tHD;DAT Data hold time 5.0 – μs tSU;DAT Data set-up time 250 – ns tr Rise time of both SDA and SCL signals – 100 ns tf Fall time of both SDA and SCL signals 300 ns tSU;STO Set-up time for STOP condition 4.0 – μs tBUF Buss free time between a STOP and STOP condition 4.7 – μs C b Capacitive load for each bus line – 400 pF Notes: 1. All values referred to V IHmin and VILmax levels. 2. A device must initially provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the undefi ned region of the falling edge of SCL. 07-0277

15 PS8934A 01/21/08

5.0Gbps 4-Lane PCI Express GenII Re-Driver with Equalization, Emphasis and I2C Control Figure 10 - Equalizer Response Characteristics SDA SCL tf S tHD;STA tLOW tHD;DAT tSU;DAT HIGH tSU;STA tHD;STA Sr tSU;STO P S tf tr tBUF START STOP START I2C Timing Channel Latency, 5.0 Gbps 07-0277

16 PS8934A 01/21/08

5.0Gbps 4-Lane PCI Express GenII Re-Driver with Equalization, Emphasis and I2C Control Output Level Settings (1V left, and 0.5V right at 5.0 Gbps) 0.0 dB (Dx = 000) –3.5 dB (Dx = 010) Output De-emphasis Characteristics 07-0277

17 PS8934A 01/21/08

5.0Gbps 4-Lane PCI Express GenII Re-Driver with Equalization, Emphasis and I2C Control Eye Diagrams 5.0Gbps (input left, output right) Data Waveforms, 2.5Gbps (left) & 5.0Gbps (right) AB C FR4 Signal Source SmA Connector SmA Connector ≤30IN In Out D.U.T. AC Test Circuit Referenced in the Electrical Characteristic Table 07-0277

18 PS8934A 01/21/08

5.0Gbps 4-Lane PCI Express GenII Re-Driver with Equalization, Emphasis and I2C Control Packaging Mechanical: 56-Contact TQFN (ZF) DESCRIPTION: 56-contact, Thin Fine Pitch Quad Flat No-lead (TQFN) PACKAGE CODE: ZF56 DOCUMENT CONTROL #: PD-2024 REVISION: B DATE: 03/03/06

Ordering Information

Ordering Number Package Code Package Description PI2EQX5864ZFE ZF Pb-free & Green 56-Contact TQFN Notes:

  • Thermal characteristics can be found on the company web site at www.pericom.com/packaging/
  • E = Pb-free and Green
  • X suffi x = Tape/Reel Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com 07-0277