PI2EQX4402 PERICOM | Alldatasheet

Document overview

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Technical content

Features

  • Two High Speed PCI Express lanes
  • Supports PCI Express data rates (2.5 Gbps) on each lane
  • Adjustable Transmiter De-Emphasis & Amplitude
  • Adjustable Receiver Equalization
  • Two Spread Spectrum Reference Clock Buffer Outputs
  • 100Ω Differential CML I/O’s
  • Low Power (100mW per Channel)
  • Standby Mode – Power Down State
  • VDD Operating Range: 1.8V +/-0.1V
  • Packaging (Pb-free & Green): - 84-ball LFBGA

Description

Pericom Semiconductor’s PI2EQX4402 is a low power, PCI Express compliant signal re-driver. The device provides programmable equalization, amplification, and de-emphasis by using 7 select bits, SEL[0:6], to optimize performance over a variety of physical mediums by reducing Inter-symbol interference. PI2EQX4402 supports four 100 Differential CML data I/O’s between the Protocol ASIC to a switch fabric, across a backplane, or extends the signals across other distant data pathways on the user’s platform. The integrated equalization circuitry provides flexibility with signal integrity of the PCI Express signal before the re-driver. Whereas the integrated de-emphasis circuitry provides flexibility with signal integrity of the PCI Express signal after the re-driver. In addition to providing signal re-conditioning, Pericom’s PI2EQX4402 also provides power management Stand-by mode operated by a Bus Enable pin. Block Diagram PI2EQX4402 2.5Gbps x2 Lane Serial PCI Express Repeater/Equalizer Pin Description (Top View) (/!+ '#!&!'- *.%$1!+ .""!+

2.5Gbps x2 Lane Serial PCI Express Repeater / Equalizer Pin Description Pin # Pin Name I/O B1, F1, D2, E2, B3, F3, H4, B8, F8, B10, F10 VDD PWR 1.8V Supply Voltage AI+ I Positive CML Input Channel A with internal 50Ω pull down AI- I Negative CML Input Channel A with internal 50Ω pull down E1, J1, F2, E3, J3, H7, E8, J8, D9, E9, F9, E10, J10 GND PWR Supply Ground BI+ I Positive CML Input Channel B with internal 50Ω pull down BI- I Negative CML Input Channel B with internal 50Ω pull down CI+ I Positive CML Input Channel C with internal 50Ω pull down CI- I Negative CML Input Channel C with internal 50Ω pull down DI+ I Positive CML Input Channel D with internal 50Ω pull down DI- I Negative CML Input Channel D with internal 50Ω pull down A3, B4, B5 SEL[0:2]_A I Selection pins for equalizer (see Amplifier Configuration Table) w/ 50KΩ internal pull up A4, C4, C5 SEL[0:2]_B I G2, J2, J4 SEL[0:2]_C I H2, K2, J5 SEL[0:2]_D I B6, A5 SEL[3:4]_A I Selection pins for amplifier (see Amplifier Configuration Table) w/ 50KΩ internal pull up C6, A6 SEL[3:4]_B I K3, K4 SEL[3:4]_C I J6, J9 SEL[3:4]_D I B7, A7 SEL[5:6]_A I Selection pins for De-Emphasis (See De-Emphasis Configuration Table) w/ 50KΩ internal pull up C7, A8 SEL[5:6]_B I K9, G9 SEL[5:6]_C I K10, H9 SEL[5:6]_D I C10 AO+ O Positive CML Output Channel A internal 50Ω pull up during normal operation and 2KΩ pull up otherwise. D10 AO- O Negative CML Output Channel A with internal 50Ω pull up during normal opera­ tion and 2KΩ pull up otherwise. BO+ O Positive CML Output Channel B with internal 50Ω pull up during normal opera­ tion and 2KΩ pull up otherwise. BO- O Negative CMLOutput Channel B with internal 50Ω pull up during normal opera­ tion and 2KΩ pull up otherwise. G10 CO+ O Positive CMLOutput Channel C with internal 50Ω pull up during normal operation and 2KΩ pull up otherwise. H10 CO- O Negative CMLOutput Channel C with internal 50Ω pull up during normal opera­ tion and 2KΩ pull up otherwise. DO+ O Positive CMLOutput Channel D with internal 50Ω pull up during normal operation and 2KΩ pull up otherwise. DO- O Negative CMLOutput Channel D with internal 50Ω pull up during normal opera­ tion and 2KΩ pull up otherwise. A9, A10, B9, C9 EN_ [A,B,C,D] I EN_[A:D] is the enable pin with internal 50KΩ pull up resistor. A LVCMOS high provides normal operation. A LVCMOS low selects a low power down mode.

2.5Gbps x2 Lane Serial PCI Express Repeater / Equalizer Output Swing Control SEL3_[A:D] SEL4_[A:D] Swing 0.8x 1.2x 1.4x Equalizer Selection SEL0_[A:D] SEL1_[A:D] SEL2_[A:D] Compliance Channel No Equalization [0:1.5dB] @ 1.25 GHz [0:2.5dB] @ 1.25 GHz [0:3.5dB] @ 1.25 GHz [0:4.5dB] @ 1.25 GHz [0:5.5dB] @ 1.25 GHz [0:6.5dB] @ 1.25 GHz [0:7.5dB] @ 1.25 GHz Output De-emphasis Adjustment SEL5_[A:D] SEL6_[A:D] De-emphasis 0dB -2.5dB -3.5dB -4.5dB Note: Stresses greater than those listed under MAXIMUM RAT­ INGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for ex­ tended periods may affect reliability. Maximum Ratings (Above which useful life may be impaired. For user guidelines, not tested.) Pin Description (Continued) Pin # Pin Name I/O I Differential Input Reference Clock CKIN+ I K5, K6 OUT0+, OUT0- O Differential Reference Clock Output K7, K8 OUT1+, OUT1- O IREF O External 475Ω resistor connection to set the differential output current EN_CLK I Enable output clock pin with internal 50KΩ pull up resistor A1, A2, B2, C2 NC N/A No connect pins. For normal operation, leave pins floating Inputs Outputs EN_[A, B, C, D] O+ / O- High Normal output Low No output Inputs Clock Outputs EN_CLK High Clock output Low No clock output

K28.7 pattern is applied differentially at point A as shown in Figure 1. Figure 1. Test Condition Referenced in the Electrical Characteristic Table

2.5Gbps x2 Lane Serial PCI Express Repeater / Equalizer AC/DC Electrical Characteristics for 2.5 Gbps x2 Lane Repeater/Equalizer (TA = 0 to 70˚C) Symbol Parameter Conditions Min. Typ. Max. Units CML Transmitter Output (100Ω differential) VDIFFP Output Voltage Swing Differential Swing | VTX-D+ - VTX-D- | 400 900 mVp-p VTX-C Common-Mode Voltage | VTX-D+ + VTX-D- | / 2 VDD- 0.3 tF, tR Transition Time 20% to 80% (1) 150 ps ZOUT Output resistance Single ended Ω ZTX-DIFF-DC DC Differential TX Impedance 100 120 Ω CTX AC Coupling Capacitor 200 nF VTX-DIFFP-P Differential Peak-to-peak Ouput Voltage VTX-DIFFP-P = 2 * | VTX-D+ - VTX-D- | 0.8 1.8 V LVCMOS Control Pins VIH Input High Voltage 0.65 × VDD VDD V VIL Input Low Voltage 0.35 × VDD IIH Input High Current 250 µA IIL Input Low Current 500 Note: Using K28.7 (0011111000) pattern)

Measurement taken from Single Ended waveform.

  1. Measurement taken from Differential waveform.

Test configuration is RS = 33.2Ω, Rp = 49.9Ω, and 2pF. Figure 2. Configuration test load board termination

  • TLA and TLB are 3” transmission lines. Rs 33Ω Rs 33Ω Rp 49.9Ω 475Ω Rp 49.9Ω 2pF 2pF Clock# Clock TLA TLB CLKBUF

2.5Gbps x2 Lane Serial PCI Express Repeater / Equalizer Packaging Mechanical: 84-Ball LFBGA (NB) 7.20 BSC. 7.20 BSC. 0.40 BSC. 0.40 BSC. 0.50 ± 0.05

0.80 BSC

Ordering Information

Pb-free & Green 84-Ball LFBGA Notes:

  • Thermal characteristics can be found on the company web site at www.pericom.com/packaging/
  • E = Pb-free & Green
  • X suffix = Tape/Reel Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com