PI29FCT520T PERICOM | Alldatasheet

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I0,I1 CLK OCTAL REGISTER A1 OCTAL REGISTER A2 OCTAL REGISTER B1 OCTAL REGISTER B2 MUX MUX D0–D7 Y0–Y7 OE S0,S1 Logic Block Diagram 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123 PI29FCT520T/2520T PI29FCT521T Fast CMOS Multilevel Pipeline Registers Product Description: Pericom Semiconductor’s PI29FCT series of logic circuits are pro-duced in the Company’s advanced 0.8 micron CMOS technology, achieving industry leading speed grades. The PI29FCT520T/2520T and PI29FCT521T are multilevel pipeline registers containing four 8-bit positive triggered registers which can be configured as a dual 2-level or a single 4-level pipeline. These products are designed for use as temporary storage or for storage delays in pipelined systems. The PI29FCT521T differs from the PI29FCT520T/2520T only in the way data is loaded into and between registers in the dual 2-level operation. When data is entered into the first level (I = 2 or I = 1) of the PI29FCT520T/2520T, the existing data in the first level is moved to the second level. In the PI29FCT521T, these instructions simply overwrite the data in the first level. Transfer of data to the second level is achieved using the 4-level shift instruction (I = 0) causing the first level to change. In either part, I = 3 shift instruction puts the registers on hold. Device models available upon request. Product Features: PI29FCT520T and PI29FCT521T are pinout and function compatible with IDT29FCT520/521, QS29FCT520/521 and AMD's Am29520/521 Four 8-bit high-speed registers Hold, Transfer, and load instructions Dual two-level or single four-level pipeline operation TTL input and output levels, reducing problematic "ground bounce" High output drive IOL = 48 mA Extremely low static power (1 mW, typ.) Industrial operating temperature range: –40°C to +85°C FCT (2xxxT) has a 25Ω series resistor. Packages available: – 24-pin 300 mil wide plastic DIP (P24) – 24-pin 150 mil wide plastic QSOP (Q24) – 24-pin 150 mil wide plastic TQSOP (R24) – 24-pin 300 mil wide plastic SOIC (S24) FCT520.pm6 12/18/96, 4:44 PM

MULTILEVEL PIPELINE REGISTERS PS2002B 12/10/96 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123 Product Pin Description Pin Name

Description

Output Enable Input (Active LOW) for 3-State Output Port CLK Clock Input. Enter data into registers on LOW-to-HIGH transistions I0,I1 Instruction Inputs S0,S1 Multiplexer Select. Inputs either register A1, A2, B1, or B2 data to be avaialbe at the output ports Dx Register Inputs Yx Register Outputs GND Ground VCC Power Product Pin Configuration CLK GND 24-PIN P24 Q24 R24 S24 Register Register Selection PI29FCT520/T2520T Data Loading DUAL 2-LEVEL SINGLE 4-LEVEL I = 0 I = 1 I = 2 NOTE: I = 3 FOR HOLD PI29FCT521T Data Loading DUAL 2-LEVEL SINGLE 4-LEVEL I = 0 I = 1 I = 2 NOTE: I = 3 FOR HOLD VCC OE FCT520.pm6 12/18/96, 4:44 PM

MULTILEVEL PIPELINE REGISTERS PS2002B 12/10/96 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Capacitance (TA = 25°C, f = 1 MHz) Parameters(4) Max. Units CIN Input Capacitance VIN = 0V pF COUT Output Capacitance VOUT = 0V pF Notes: 1. For conditions show as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading. 3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. 4. This parameter is determined by device characterization but is not production tested. Parameters Test Conditions(1) Min. Typ(2) Max. Units VOH Output HIGH Voltage VCC = MIN., VIN = VIH OR VIL IOH = –15.0 mA 2.4 3.0 V VOL Output LOW Voltage VCC = MIN., VIN = VIH OR VIL IOL = 48 mA 0.3 0.50 V IOL = 12 mA (25Ω series) 0.3 0.50 V VIH Input HIGH Voltage Guaranteed Logic HIGH Level 2.0 V VIL Input LOW Voltage Guaranteed Logic LOW Level 0.8 V IIH Input HIGH Current VCC = MAX. VIN = VCC µA IIL Input LOW Current VCC = MAX. VIN = GND µA IOZH High Impedance VCC = MAX. VOUT = 2.7V µA IOZL Output Current VOUT = 0.5V µA VIK Clamp Diode Voltage VCC = MIN., IIN = –18 mA –0.7 –1.2 V IOS Short Circuit Current VCC = MAX.(3), VOUT = GND –60 –120 mA IOFF Power Down Disable VCC = GND, VOUT = 4.5V 100 µA VH Input Hysteresis 200 mV FCT520.pm6 12/18/96, 4:44 PM

MULTILEVEL PIPELINE REGISTERS PS2002B 12/10/96 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123 Power Supply Characteristics Parameters Description Test Conditions(1) Min. Typ(2) Max. Units ICC Quiescent Power VCC = Max. VIN = GND or VCC 0.1 µA Supply Current ∆ICC Supply Current per VCC = Max. VIN = 3.4V(3) 0.5 2.0 mA Input @ TTL HIGH ICCD Supply Current per VCC = Max., VIN = GND 0.15 0.25 mA/ Input per MHz(4) Outputs Open VIN = VCC MHz OE = GND One Input Toggling 50% Duty Cycle IC Total Power Supply VCC = Max., VIN = GND 1.5 3.5(5) mA Current(5) Outputs Open VIN = VCC fCP = 10 MHZ 50% Duty Cycle OE = GND VIN = 3.4V 2.0 5.5(5) One Bit Toggling VIN = GND fI = 5 MH 50% Duty Cycle VCC = Max., VIN = GND 3.8 7.3(5) Outputs Open VIN = VCC fCP = 10 MHZ 50% Duty Cycle OE = GND VIN = 3.4V 6.0 16.3(5) Eight Bits Toggling VIN = GND fI = 5 MHz 50% Duty Cycle Notes: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device. 2. Typical values are at Vcc = 5.0V, +25°C ambient. 3. Per TTL driven input (VIN = 3.4V, control inputs only); all other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply characteristics. 5. Values for these conditions are examples of the ICC formula. These limits are guAranteed but not tested. 6. IC =IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ∆ICC DHNT + ICCD (fCP/2 + fINI) ICC = Quiescent Current ∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices) fI = Input Frequency NI = Number of Inputs at fI All currents are in milliamps and all frequencies are in megahertz. FCT520.pm6 12/18/96, 4:44 PM

MULTILEVEL PIPELINE REGISTERS PS2002B 12/10/96 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123 PI29FCT520T/2520T Switching Characteristics over Operating Range FCT520AT/2520AT FCT520BT/2520BT Com. Com. Parameters Conditions(1) Min Max Min Max Unit tPLH Propagation Delay CL = 50 pF 2.0 14.0 2.0 7.5 ns tPHL CLK to YX RL = 500Ω tPLH Propagation Delay 2.0 13.0 2.0 7.5 ns tPHL S0 or S1 to YX tSU Setup Time HIGH 5.0 2.5 ns or LOW DX to CLK tH Hold Time HIGH 2.0 2.0 ns or LOW DX to CLK tSU Setup Time HIGH 5.0 4.0 ns or LOW I0 or I1 to CLK tH Hold Time HIGH 2.0 2.0 ns or LOW I0 or I1 to CLK tPZH Output Enable Time 1.5 12.0 1.5 7.0 ns tPZL OE to YX tPHZ Output Disable Time(3) 1.5 15.0 1.5 7.5 ns tPLZ OE to Yx tW Clock Pulse Width(3) 7.0 5.5 ns HIGH or LOW Notes: 1. See test circuit and wave forms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. This parameter is guaranteed but not production tested. PI29FCT521T Switching Characteristics over Operating Range FCT521AT FCT521BT Com. Com. Parameters Conditions(1) Min Max Min Max Unit tPLH Propagation Delay CL = 50 pF 2.0 14.0 2.0 7.5 ns tPHL CLK to YX RL = 500Ω tPLH Propagation Delay 2.0 13.0 2.0 7.5 ns tPHL S0 or S1 to YX tSU Setup Time HIGH 5.0 2.5 ns or LOW DX to CLK tH Hold Time HIGH 2.0 2.0 ns or LOW DX to CLK tSU Setup Time HIGH 5.0 4.0 ns or LOW I0 or I1 to CLK tH Hold Time HIGH 2.0 2.0 ns or LOW I0 or I1 to CLK tPZH Output Enable Time 1.5 12.0 1.5 7.0 ns tPZL OE to Yx tPHZ Output Disable Time(3) 1.5 15.0 1.5 7.5 ns tPLZ OE to Yx tW Clock Pulse Width(3) 7.0 5.5 ns HIGH or LOW Pericom Semiconductor Corporation 2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com FCT520.pm6 12/18/96, 4:44 PM