PF175B480C033FP-00

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Document overview

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• PDF pages: 20

Technical content

Features

• Isolated A C -to-DC converter w ith P FC
• Low profile
• P ow er Density: 24 3 W /in 3 3 3 0 W in 3 .67 in 2 footprint
• H igh efficiency (~93 % ) over w orld-w ide A C m ains °R ectified 85 – 264 V A C
• Secondary-side energy storage
• Sim plified m ounting and therm al m anagem ent
• SELV 4 8 V O utput °Efficient pow er distribution to P O L converters °3 ,000 VA C /4 ,24 2 VDC isolation
• P FC (TH D) exceeds EN61000-3 -2 requirem ents
• ZVS high frequency (M H z) sw itching
• Low profile, high density filtering
• 100°C baseplate operation Typical A pplications
• Telecom (W iM A X , P ow er A m plifiers, O ptical Sw itches)
• A utom atic Test Equipm ent (A TE)
• LED lighting
• H igh Efficiency Server P ow er
• O ffice equipm ent (P rinters, C opiers, P rojectors)
• Industrial Equipm ent (P rocess C ontrollers, M aterial H andling, Factory A utom ation)
• Sw itch M ode P ow er Supplies (SM P S) Product O verview The VI BR IC K ® P FM ® Isolated A C -DC C onverter w ith P FC is an A C -to- DC converter, operating from a rectified universal A C input to generate an isolated 4 8 Vdc output bus w ith pow er factor correction. W ith its ZVS high frequency A daptive C ell™ topology, the VI BR IC K P FM converter consistently delivers high efficiency across w orldw ide A C m ains. M odular P FM converters and dow nstream DC -DC VI BR IC K products support secondary-side energy storage and efficient pow er distribution at 4 8 V, providing superior pow er system perform ance and connectivity from the w all plug to the point-of-load.

VI BRICK ® PFM ® Rev 1.3 vicorpow er.com Page 2 of 20 1/2013 800 7 35 .6 200 PF1 7 5B48 0 C0 33FP-0 0 The A bsolute M axim um Ratings below are stress ratings only. O peration at or beyond these m axim um ratings can cause perm anent dam age to device. Electrical specifications do not apply w hen operating beyond rated operating conditions. Positive pin current represents current flow ing out of the pin. PA RA M ETER M IN M A X U N IT N O TES Input voltage (+In to -In) 0 600 Vpk 1 m s m ax Input voltage (+In to -In) 0 3 85 Vpk C ontinuous Input voltage slew rate -25 25 V/ µs C om m on M ode and Differential M ode R SV1 to –IN -0.3 5 .3 VDC Do not connect to this pin EN to –IN -0.3 5 .3 VDC 5 V tolerant 3 .3 V logic R SV3 to –IN -0.3 5 .3 VDC Do not connect to this pin O utput voltage (+O ut to -O ut) -0.5 5 7 .0 VDC O utput current 0.0 10.2 A TEM PERATU RE O perating junction -5 5 125 °C W orst case sem iconductor O perating tem perature -20 100 °C C -G rade; baseplate -4 0 100 °C T-G rade; baseplate -5 5 100 °C M -G rade; baseplate Storage tem perature -4 0 125 °C C -G rade -4 0 125 °C T-G rade -65 125 °C M -G rade D IELECTRIC W ITH STA N D Dielectric W ithstand Input – O utput 3 000 VR M S Dielectric W ithstand Input – Base 15 00 VR M S Dielectric W ithstand O utput – Base 15 00 VR M S 1 .0 A bsolute M axim um Ratings

1.0 A BSO LU TE M A XIM U M RA TIN G S

PFM® Converter Rectifier, Filter, Transient Protection 85 -

264 Vac

1.0V 100A

24 V 7A

PRM® Regulator PRM® Regulator 3.3V 6A 1.8V 8A 48 V Cool-Power® ZVS Buck Cool-Power® ZVS Buck VTM® Transformer +IN -IN +OUT +OUT -OUT -OUT Typical A pplication: U niversal A C Input, Q uad O utput, 300W Pow er Supply

VI BRICK ® PFM ® Rev 1.3 vicorpow er.com Page 3 of 20 1/2013 800 7 35 .6 200 PF1 7 5B48 0 C0 33FP-0 0 ATTRIBU TE SYM BO L CO N D ITIO N S / N O TES M IN TYP M A X U N IT PO W ER IN PU T SPECIFICATIO N Input voltage range, VIN 8 5 2 64 VR M S continuous operation Input voltage range, VIN 1 m s 600 Vtransient, non-operational (peak) Input voltage cell reconfiguration VIN -C R + 14 5 1 48 VR M S low -to-high threshold Input voltage cell reconfiguration VIN -C R - 1 32 13 5 VR M S high-to-low threshold Input voltage slew rate dVIN /dt C om m on M ode and Differential M ode -25 25 V/µs Input current (peak) IINR P 12 A Source line frequency range fline 4 7 63 H z P ow er factor P F Input pow er >100 W 0.9 - Input inductance, m axim um LIN Differential m ode inductance, com m on 1 m H m ode inductance m ay be higher Input capacitance, m axim um C IN A fter bridge rectifier, betw een +IN and - IN 1.5 µF N O LO A D SPECIFICATIO N Input pow er – no load, m axim um P NL EN floating, see Figure 6 1.1 1.5 W Input pow er – disabled, m axim um P Q EN pulled low , see Figure 7 1.6 W PO W ER O U TPU T SPECIFICATIO N O utput voltage set point VO UT Vin = 23 0 Vrm s, 10% Load 4 7 .5 4 9 5 0.5 V O utput voltage, no load VO UT -NL O ver all operating steady 46 5 1.5 55 Vstate line conditions O utput voltage range (transient) VO UT Non-faulting abnorm al line and load 30 55 Vtransient conditions O utput pow er P O UT See Figure 1, SO A 330 W VIN = 23 0 V, full load, 92 93 .5 %exclusive of input rectifier losses Efficiency h 85 V < V IN < 264 V, full load, 9 1 %exclusive of input rectifier losses

85 V < V IN < 264 V, 7 5 % load, 92 %exclusive of input rectifier losses

O utput voltage ripple, VO UT -P P -H F O ver all operating steady-state line and sw itching frequency load conditions, 20 M H z BW , m easured 100 30 0 m V at C 3 , Figure 29 O utput voltage ripple VO UT -P P -LF O ver all operating steady-state line and 3 .8 5V line frequency load conditions, 20 M H z BW O utput capacitance (external) C O UT -EX T 60 0 0 1 2 0 0 0 µF O utput turn-on delay TO N From V IN applied, EN floating 4 00 1 0 0 0 m s From EN pin release, V IN applied Start-up setpoint aquisition tim e Tss Full load 4 00 5 00 m s C ell reconfiguration response tim e TC R Full load 5 .5 11 m s Voltage deviation (transient) % V O UT -TR A NS 8% R ecovery tim e TTR A NS 25 0 5 00 m s Line regulation % V O UT -LINE Full load 0.5 1% Load regulation % V O UT -LO A D 10% to 100% load 0.5 1% O utput current (continuous) IO UT See Figure 1, SO A 6.9 A Specifications apply over all line and load conditions, 50 Hz and 6 0 Hz line frequencies, T C= 25°C, unless otherw ise noted. Boldface specifications apply over the tem perature range of the specified product grade. C O U T is 6 800 µF +/- 20% unless otherw ise specified. 2 .0 Electrical Characteristics

2.0 ELECTRICA L CH A RA CTERISTICS

VI BRICK ® PFM ® Rev 1.3 vicorpow er.com Page 5 of 20 1/2013 800 7 35 .6 200 PF1 7 5B48 0 C0 33FP-0 0

3.0 SIG N A L CH A RA CTERISTICS

3.0 Signal Characteristics

SIG N A L TYPE STATE ATTRIBU TE SYM BO L CO N D ITIO N S / N O TES M IN TYP M A X U N IT Startup EN enable threshold VEN _EN 2.3 1 V D IG ITA L IN PU T EN disable tim e tEN _DIS From any point in line cycle 9 1 6 m s Standby EN disable threshold VEN _DIS 0.99 V EN resistance to disable R EN _EX T M ax allow able resistance to -IN required 4.2 8 kΩto disable the m odule

• The EN pin enables and disables the P FM ® converter; w hen held below 0.8 V the unit w ill be disabled.
• The EN pin can reset the P FM converter after a latching O VP event.
• The EN pin voltage is 3 .3 V during norm al operation.
• The EN pin is referenced to the –IN pin of the converter. EN A BLE : EN No connections are required to these pins. In noisy enviornm ents, it is beneficial to add a 0.1 µF capacitor betw een each reserved pin and -IN. RESERVED : RSV1, RSV3 Specifications apply over all line and load conditions, 50 Hz and 6 0 Hz line frequencies, T C= 25°C, unless otherw ise noted. Boldface specifications apply over the tem perature range of the specified product grade. C O U T is 6 800 µF +/- 20% unless otherw ise specified.

VI BRICK ® PFM ® Rev 1.3 vicorpow er.com Page 6 of 20 1/2013 800 7 35 .6 200 PF1 7 5B48 0 C0 33FP-0 0 +OUT -OU T Prima ry & Se cond ary Powertrain +IN -I N Cell Conf ig ur ati on Co ntrolle r VEAO RSV3 EN RSV1 Modulator Input UVP & OVP Internal OTP / UTP Out put OV P Output OCP/SCP Enabl e PFC Cont rol Micro controller Fault Latch & Re se t L ogi c 3.3 V Q3 T Ref erence Volta ge wit h Ri pple Twice the Sup ply Fr equ ency Q1 T Q2 T Q4 T Auto Ranger Control VIN- B VIN-B Output Voltage with Offset Fault monitoring Error Amplifi er COUT-INT CIN -T CIN-B -I N -IN -I N -I N 49.9 kΩ Q3 B Q1 B Q2 B Q4 B VEA OPowertrain En abl e Adapti ve Cell ™ top olo gy Bott om Cell Top Cell -I N Microcontroller: Fault Monitoring and PFC Prima ry- side Volta ge Se nse Figure 3 — Functional block diagram 4 .0 FU N CTIO N A L BLO CK D IA G RA M

VI BRICK ® PFM ® Rev 1.3 vicorpow er.com Page 7 of 20 1/2013 800 7 35 .6 200 PF1 7 5B48 0 C0 33FP-0 0 Conditions that cause state transitions are show n along arrow s. Sub-sequence activities are listed inside the state bubbles. OPERAT IONAL VOUT Ra mp Up (tss) Regulate s VOUT Powertr ain : Act ive RNG: A uto PFC : Auto STAN DBY Po wer train : St oppe d RNG: Hig h Appli catio n of VIN EN = True and No Fault s LATCH ED FAULT Po wer trai n: Stopp ed RNG: Hi gh VIN > VIN- UVL O+ START UP SE QUENCE Li ne Freq uenc y Acqui sitio n Po wer trai n: Stopp ed RNG: Auto tON Expiry EN = Fals e or VIN Out of Rang e EN = False or VIN Out of Range NON LATCHED FAULT tOFF delay Po wer trai n: Stopp ed RNG: Hi gh Overtem p, Output Short, or Ov erlo ad Output OV P No Fault s EN Fall ing Edge Figure 4 — State diagram 5 .0 H IG H LEVEL FU N CTIO N A L STA TE D IA G RA M

VI BRICK ® PFM ® Rev 1.3 vicorpow er.com Page 8of 20 1/2013 800 7 35 .6 200 PF1 7 5B48 0 C0 33FP-0 0 VIN-RM S EN VOUT ILOAD VIN-OVLO+ Input Po wer On & UV Turn-on Ful l Load App lied EN Force d Low EN High Rang e Ch ang e LO to HI Rang e Ch ang e HI to LO Inp ut OV Turn-off Inp ut OV Turn-on Load Du mp Load Step Input Po wer Off & UV Turn-off In put Output tCR tON VIN-UVL O+ ≈30 VRMS 10% Load App lied tCR tTRANS (2 p lace s) VIN -OVLO- VIN-UVL O- VIN-C R+ VIN-CR- VOUT-NL VOU T tON tON tPOVP tUV LOtEN-DIS tSStSS VIN-RM S VOUT ILOAD tON VIN-UVL O+ tOC tOFF+tON tOFF+tON tOC ≥tOFF+tON VOU T-OVLO + tSOV P tON tSS VIN -UVLO- tSC tOFF+tON tOF F+tON EN tOC Input Po wer ON & UV Turn-o n Output OC Fault Outp ut OC Recovery Output OVP Faul t Togg le EN (O utput OVP Recovery) Out put OV P Fault Re cycle Inpu t Power (Ou tput OVP Re covery) Output SC Fault Outp ut SC Re covery OT F ault Re covery Lin e Drop-Out In put Power Off & UV Turn-off In put Output tON VIN-UVL O+ )))) )))) )))) M odule inputs are show n in blue ; M odule outputs are show n in brow n ; Tim ing diagram assum es resistive load, adjusted as show n in the diagram , except in the case of output O VP . Figure 5 — Tim ing diagram - * N egative current is externally forced and show n for the purpose of O VP protection scenario. 6 .0 TIM IN G D IA G RA M S

VI BRICK ® PFM ® Rev 1.3 vicorpow er.com Page 10 of 20 1/2013 800 7 35 .6 200 PF1 7 5B48 0 C0 33FP-0 0 Figure 12 – Typical startup w aveform , EN pin release, V IN = 24 0 V, RLO A D = 7.1 Ω, CO U T = 6 ,800 µF. Figure 13 – Line drop out, 50 Hz, 0° phase, V IN = 23 0 V, ILO A D = 6 .8A , C O U T = 6 ,800 µF. Figure 14 – Line drop out, 50 Hz, 9 0° phase, V IN = 23 0 V, ILO A D = 6 .8A , C O U T = 6 ,800 µF. Figure 15 – Typical conducted em issions, full load, 3 x0.4 7uF X caps +IN to -IN , no CM filter. C O U T = 6 ,800 µF, -O ut grounded. Current [mA] Input Current Harmonics vs. Input Voltage 100 200 300 400 500 600 700 800 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39

230 V, 50 Hz 1/3x EN61000-3-2, Class A EN61000-3-2, Class D

Figure 17 – Typical input current harm onics, full load vs. V IN . Figure 16 – Typical line current w aveform , V IN = 1 20 V, PLO A D = 3 3 0 W . 7 .0 A PPLICA TIO N CH A RA CTERISTICS (CO N TIN U ED ) The follow ing figures present typical perform ance at T C = 25ºC, unless otherw ise noted. See associated figures for general trend data.

VI BRICK ® PFM ® Rev 1.3 vicorpow er.com Page 11 of 20 1/2013 800 7 35 .6 200 PF1 7 5B48 0 C0 33FP-0 0 Load Current (A) Power Factor Power Factor vs. Load and VIN TCASE = 25°C V :IN 100 V, 60 Hz 120 V, 60 Hz 240 V, 50 Hz 0.80 0.82 0.84 0.86 0.88 0.90 0.92 0.94 0.96 0.98 Efficiency & Power Dissipation TCASE = -40°C Efficiency (%) Power Dissipation (W) Load Current (A)

100 V Power Diss 115 V Power Diss 240 V Power Diss

V :IN 100 V Eff 115 V Eff 240 V Eff Efficiency & Power Dissipation TCASE = 25°C Efficiency (%) Power Dissipation (W) Load Current (A) V :IN 100 V Eff 115 V Eff 240 V Eff Figure 18 – Typical pow er factor vs. V IN and I O U T . Figure 19 – VIN to V O U T efficiency and pow er dissipation vs. V IN and I O U T , T CA SE = -4 0ºC. Figure 20 – VIN to V O U T efficiency and pow er dissipation vs. V IN and I O U T , T CA SE = 25ºC. Efficiency & Power Dissipation TCASE = 100°C Efficiency (%) Power Dissipation (W) Load Current (A) V :IN 100 V Eff 115 V Eff 240 V Eff Figure 21 – VIN to V O U T efficiency and pow er dissipation vs. V IN and I O U T , T CA SE = 1 00ºC. 0.0 0.5 1.0 1.5 2.0 2.5 3.0 8 5 1 0 0 1 1 5 1 3 0 1 4 5 1 6 0 1 7 5 190 205 220 235 250 265 vs. applied voltage Effective internal input (CIN_INT) capacitance Input V oltage (V) Parallel Mode (Low) Series Mode (High) Effective capacitance (µF) Figure 23 – Effective input capacitance vs. V IN . Input Voltage ( VRMS ) Input Resistance ( Ω) Powertrain Equivalent Input Resistance (rEQ_IN ) vs. Input Voltage 100 120 140 85 100 115 130 145 160 175 190 205 220 235 250 265 Figure 22 – Dynam ic input resistance vs. V IN , I O U T = 6 .9 A . 7 .0 A PPLICA TIO N CH A RA CTERISTICS (CO N TIN U ED ) The follow ing figures present typical perform ance at T C = 25ºC, unless otherw ise noted. See associated figures for general trend data.

VI BRICK ® PFM ® Rev 1.3 vicorpow er.com Page 12 of 20 1/2013 800 7 35 .6 200 PF1 7 5B48 0 C0 33FP-0 0 ATTRIBU TE SYM BO L CO N D ITIO N S / N O TES M IN TYP M A X U N IT M ECH A N ICA L Length L 4 8.6 /[1.91] m m /[in] W idth W 4 8.7 /[1.92] m m /[in] H eight H 9.5 0 /[0.3 7 ] m m /[in] Volum e Vol 22.5 /[1.3 7 ] cm 3 /[in 3 ] W eight W 5 7 .5 /[2.03 ] g/[oz] P in m aterial C 10200 copper, full hard Underplate Nickel 100 15 0 µin P in finish P ure m atte tin, 200 3 00 w hisker resistant chem istry TH ERM A L O perating baseplate (case) A ny operating C G rade -20 tem perature TC condition T G rade -4 0 100 °C M G rade -5 5 Therm al resistance, baseplate 0.22 °C /Wto sink, flat greased surface Therm al resistance, baseplate 0.19 °C /Wto sink, therm al pad (3 6964 ) Therm al capacity 4 4 .5 W s /°C Therm al design See Section 10.9 A SSEM BLY ESD H BM H um an Body M odel, 1000 “JEDEC JESD 22-A 114 C .01” ESD rating ESD M M M achine M odel, N/A V“JEDEC JESD 22-A 115 B” ESD C DM C harged Device M odel, 4 00 “JEDEC JESD 22-C 101D” SO LD ERIN G See application note SA FETY & RELIA BILITY Telecordia Issue 2 - 2.5 1 M H rs M ethod I C ase 1; M TBF G round Benign, C ontrolled M IL-H DBK-217 4 .93 M H rs P lus P arts C ount - 25 °C ground Benign, Stationary cTUVus, U L /cUL, EN, IEC 6095 0-1 A gency approvals /standards C E, Low Voltage Directive; 2006/95 /EC C E M arked for Low Voltage Directive and R oH S R ecast Directive, as applicable EM I/EM C CO M PLIA N CE EN61000-3 -2: 2009, H arm onics H arm onic C urrent Em isions – C lass A Specifications apply over all line and load conditions, T C = 25°C, unless otherw ise noted. Soldering M ethods and P rocedure for Vicor P ow er M odules »

8.0 G EN ERA L CH A RA CTERISTICS

8 .0 G eneral Characteristics

VI BRICK ® PFM ® Rev 1.3 vicorpow er.com Page 13 of 20 1/2013 800 7 35 .6 200 PF1 7 5B48 0 C0 33FP-0 0 9 .0 PRO D U CT O U TLIN E D RA W IN G A N D RECO M M EN D ED PCB FO O TPRIN T 9 .1 M odule O utline Figure 24 — Product outline draw ing; Product outline draw ings are available in .pdf and .dxf form ats. 3 D m echanical m odels are available in .pdf and .step form ats. See http://w w w .vicorpow er.com /cm s/hom e/technical_resources/M echanical_Draw ings/M odules for m ore details.

VI BRICK ® PFM ® Rev 1.3 vicorpow er.com Page 14 of 20 1/2013 800 7 35 .6 200 PF1 7 5B48 0 C0 33FP-0 0 9 .2 PCB M ounting Specifications Figure 25 — Recom m ended PCB pattern; Product outline draw ings are available in .pdf and .dxf form ats. 3 D m echanical m odels are available in .pdf and .step form ats. See http://w w w .vicorpow er.com /cm s/hom e/technical_resources/M echanical_Draw ings/M odules for m ore details. 9 .0 PRO D U CT O U TLIN E D RA W IN G A N D RECO M M EN D ED PCB FO O TPRIN T (CO N T.)

VI BRICK ® PFM ® Rev 1.3 vicorpow er.com Page 15 of 20 1/2013 800 7 35 .6 200 PF1 7 5B48 0 C0 33FP-0 0

10.0 PRO D U CT D ETA ILS A N D D ESIG N G U ID ELIN ES

1 0 .1 Building Blocks and System D esigns The VI BR IC K ® P FM ® Isolated A C -DC C onverter w ith P FC is a high efficiency A C -to-DC converter, operating from a rectified universal A C input to generate an isolated SELV 4 8 VDC output bus w ith pow er factor correction. It is a com ponent of an A C to DC pow er supply system such as the one show n in Figure 26 above. The input to the P FM converter is a rectified, sinusoidal A C source w ith a pow er factor m aintained by the converter w ith harm onics conform ing to IEC 61000-3 -2. Upstream filtering enables com pliance w ith the standards relevant to the application (Surge, EM I, etc.). The P FM converter uses secondary-side energy storage (at the SELV 4 8 V bus) and optional P R M ™ regulators to m aintain output hold up through line dropouts and brow nouts. Dow nstream regulators also provide tighter voltage regulation, if required. The P F17 5 B4 80C 03 3 FP -00 is designed for standalone operation; how ever, it m ay be part of a system that is paralleled by dow nstream DC /DC converters. P lease contact Vicor Sales or refer to our w ebsite, w w w .vicorpow er.com , for higher pow er applications.

10.1.1 Traditional P FC Topology

To cope w ith input voltages across w orldw ide A C m ains (85 -264 Vac), traditional A C -DC pow er supplies (Figure 27 ) use 2 pow er conversion stages: 1) a P FC boost stage to step up from a rectified input as low as 85 Vac to ~3 80 Vdc; and 2) a DC -DC dow n converter from 3 80 Vdc to a 4 8 V bus. The efficiency of the boost stage and of traditional pow er supplies is significantly com prom ised operating from w orldw ide A C lines as low as 85 Vac.

10.1.2 A daptive C ell™ Topology

W ith its single stage A daptive C ell™ topology, the P FM converter enables consistently high efficiency conversion from w orldw ide A C m ains to a 4 8 V bus and efficient secondary- side pow er distribution. 1 0 .2 Pow er Factor Correction The converter provides pow er factor correction over w orldw ide A C m ains. P ow er factor correction is disabled in low pow er m ode to im prove efficiency. It is disabled in transient m ode to allow quicker recovery upon input transients. Load transients that approach the line frequency should be filtered or avoided as these m ay reduce P FC . 1 0 .3 Sm all Signal Characteristics Figure 28 show s the sm all signal m odel of the converter. Because of its internal feedback loop and P FC m odulation, w ithin its regulation bandw idth (dynam ic response show n in figure 10) the converter’s output can be effectively m odeled w ith tw o sources in series and a passive filter:

• A constant, 4 9 Vdc voltage generator.
• A dependent voltage source, V R IP P LE , w hich outputs a variable am plitude sinew ave at a frequency tw ice the input line.
• A first order filter, R O UT C O UT _INT . O utput voltage stability is guaranteed as long as hold up capacitance C O UT and load fall w ithin the specified ranges. Input line stability needs to be verified at system design level. M agnitude of the dynam ic input im pedance r EQ _IN is provided in Figure 22. The input line im pedance can be m odeled as a series R LINE LLINE circuit. C eram ic decoupling capacitors w ill not significantly dam p the netw ork because of their low ESR ; therefore in order to guarantee stability the follow ing conditions m ust be verified: It is critical that the line source resistance be at least an octave low er than the converter’s dynam ic input im pedance, (2). H ow ever, R LINE cannot be m ade arbitrarily low otherw ise equation (1) is violated and the system w ill show instability, due to under-dam ped R LC input netw ork. RLINE > (1) LLINE (C IN _INT + CIN _EXT ) • rEQ _IN RLINE << (2) rEQ _IN Full Wave Rectifier

85 V – 264 Vac

48 Vdc

(Optional) +IN -IN +OUT PFM® Converter +OUT -OUT -OUT Figure 26 – 3 00 W U niversal A C to DC Supply Full Wave Rectifier EMI/TVS Filter Isolated DC / DC Converter

48 V Bus

Figure 27 – Traditional PFC A C to DC supply + + VIN rEQ _IN Vripple CIN _INT ROUT VOUT COUT _INT COUT _EXT RCOUT RLOAD 49V Figure 28 – PF1 75B 4 80C03 3 FP-00 A C sm all signal m odel

VI BRICK ® PFM ® Rev 1.3 vicorpow er.com Page 18 of 20 1/2013 800 7 35 .6 200 PF1 7 5B48 0 C0 33FP-0 0 10.0 PRO D U CT D ETA ILS A N D D ESIG N G U ID ELIN ES (CO N T.) In certain applications, the choice of bulk capacitance m ay be determ ined by hold up requirem ents and low frequency output voltage filtering requirem ents. Such applications m ay use the greater capacitance value determ ined from these requirem ents. The ripple current rating for the bulk capacitors can be determ ined from the follow ing equation: 10.7 .2 Sw itching Frequency Filtering O utput sw itching frequency voltage ripple is the function of the output bypass ceram ic capacitor. O utput bypass ceram ic capacitor values should be calculated based on sw itching frequency voltage ripple. Norm ally bypass capacitors w ith low ESR are used w ith a sufficient voltage rating. O utput bypass ceram ic capacitor value for allow able peak-to- peak sw itching frequency voltage ripple can be determ ined by: 1 0 .8 EM I Filtering and Transient Voltage Suppression

10.8.1 EM I Filtering

The P FM ® Isolated A C -DC C onverter w ith P FC is designed such that it w ill com ply w ith EN 5 5 022 C lass B w ith m oderate upstream filtering and output to earth Y-capacitance. If one of the outputs is connected to earth ground, an additional sm all output com m on m ode choke is also required. In such a situation, the output sw itching ripple show n in figure 8 should be expected at the output of the filter. In cases w here other m eans are used to control radiated em issions, and m ore ripple can be tolerated, the output filter can be sim plified by rem oval of the com m on m ode inductor, and C 5 , w hich is used to reduce the Q of the LC resonant tank. The em issions spectrum w ithout input filtering is show n in Figure 15 in Section 7 .0.

10.8.2 Transient Voltage Suppression

In order to com ply w ith line transient specifications such as those for surge (i.e. EN 61000-4 -5 ) and fast transient (i.e. EN 61000-4 -4 fast transient /“burst”), an upstream transient voltage suppression circuit is needed. C onsult factory for m ore inform ation. 1 0 .9 Therm al D esign Therm al m anagem ent of internally dissipated heat should m axim ize heat rem oved from the baseplate surface, since the baseplate represents the low est aggregate therm al im pedance to internal com ponents. The baseplate tem perature should be m aintained below 100°C . C ooling of the system P C B should be provided to keep the leads below 100°C , and to control m axim um P C B tem peratures in the area of the converter. 1 0 .1 0 Pow ering a Constant Pow er Load W hen the output voltage of the P FM converter is applied to the input of the P R M ® regulator, the regulator turns on and acts as a constant-pow er load. W hen the P FM converter’s output voltage reaches the input undervoltage turn on of the regulator, the regulator w ill attem pt to start. H ow ever, the current dem and of the P R M regulator at the undervoltage turn on point and the hold up capacitor charging current m ay force the P FM converter into current lim it. In this case, the unit m ay shut dow n and restart repeatedly. In order to prevent this m ultiple restart scenario, it is necessary to delay enabling a constant-pow er load w hen pow ered up by the P FM converter based upstream A C to 4 8 V frontend until after the output set point of the P FM converter is reached. This can be achieved by 1) keeping the dow nstream constant-pow er load off during pow er up sequence and 2) turning the dow nstream constant-pow er load on after the output voltage of the converter reaches 4 8 V steady state. A fter the initial startup, the output of the P FM converter can be allow ed to fall to 3 0 V during a line dropout at full load. In this case, the circuit should not disable the P R M regulator if the input voltage falls after it is turned on; therefore, som e form of hysteresis or latching is needed on the enable signal for the constant pow er load. The output capacitance of the P FM converter should also be sized appropriately for a constant pow er load to prevent collapse of the output voltage of the P FM converter during line dropout (see Section 10.6, H old up C apacitance). A constant-pow er load can be turned off after com pletion of the required hold up tim e during the pow er- dow n sequence or can be allow ed to turn off w hen it reaches its ow n undervoltage shutdow n point. The tim ing diagram in Figure 3 1 show s the output voltage of the P FM converter and the P C pin voltage and output voltage of the P R M regulator for the pow er up and pow er dow n sequence. It is recom m ended to keep the tim e delay approxim ately 10 to 20 m s. C3 = Q TOT / VOUT-PP -HF – COUT-INT where: VOUT-PP -HF Allowable peak to peak output switching frequency voltage ripple in volts QTOT The total output charge per switching cycle at full load, maximum 13.5 µC COUT_INT The module internal effective capacitance C3 Required output bypass ceramic capacitor (6) 0.8 * P OUT / VOUT (5) Iripple = ~

VI BRICK ® PFM ® Rev 1.3 vicorpow er.com Page 19 of 20 1/2013 800 7 35 .6 200 PF1 7 5B48 0 C0 33FP-0 0 10.0 PRO D U CT D ETA ILS A N D D ESIG N G U ID ELIN ES (CO N T.) Special care should be taken w hen enabling the constant- pow er load near the auto-ranger threshold, especially w ith an inductive source upstream of the P FM ® converter. A load current spike m ay cause a large input voltage transient, resulting in a range change w hich could tem porarily reduce the available pow er (see Section 10.11, A daptive C ell™ Topology). 1 0 .1 1 A daptive Cell™ Topology The A daptive C ell topology utilizes m agnetically coupled “top” and “bottom ” prim ary cells that are adaptively configured in series or parallel by a configuration controller com prised of an array of sw itches. A m icrocontroller m onitors operating conditions and defines the configuration of the top and bottom cells through a range control signal. A com parator inside the m icrocontroller m onitors the line voltage and com pares it to an internal voltage reference. If the input voltage of the P FM converter crosses above the positive going cell reconfiguration threshold voltage, the output of the com parator transitions, causing sw itches S 1 and S 2 to open and sw itch S 3 to close (see Figure 3 ). W ith the top cell and bottom cell configured in series, the unit operates in “high” range and input capacitances C IN -Tand C IN -Bare in series. If the peak of input voltage of the unit falls below the negative-going range threshold voltage for tw o line cycles, the cell configuration controller opens sw itch S 3 and closes sw itches S 1 and S 2. W ith the top cell and bottom cells configured in parallel, the unit operates in “low ” range and input capacitances C IN -Tand C IN -Bare in parallel. P ow er processing is held off w hile transitioning betw een ranges and the output voltage of the unit m ay tem porarily droop. External output hold up capacitance should be sized to support pow er delivery to the load during cell reconfiguration. The m inim um specified external output capacitance of 6000 µF is sufficient to provide adequate ride-through during cell reconfiguration for typical applications. PFM™ Converter PRM™ Regulator PRM UV Turn on 49V – 3% PRM™ Regulator VOUT tDELAY tHOLD -UP VOUT PC Figure 31 – PRM ® Enable Hold off W aveform s

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