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High Voltage Subscriber Line IC HV-SLIC PEB/F 4065 Version 3.0 Data Sheet 03.98 DS 1 http://ww w.siem ens.de/ Se miconductor/
SLICOFI® is a registered trademark of SIEMENS AG. For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide: see our webpage at http:/ /www.siemens.de/Semiconductor/address/address.htm. PEB/F 4065 Revision History: Current Version: 03.98 Previous Version: 01.96 Page (in previous Version) Page (in current Version) Subjects (major changes since last revision) Edition 03.98 Published by Siemens AG, HL SP, Balanstraße 73,
81541 München
© Siemens AG 1998. All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Siemens Office, Semiconductor Group. Siemens AG is an approved CECC manufacturer. Packing Please use the recycling operators known to you. We can also help you – get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. Components used in life-support devices or systems must be expressly authorized for such purpose! Critical components 1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2 with the express written approval of the Semiconductor Group of Siemens AG. 1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be en- dangered.
Semiconductor Group 3 1998-03-01
Semiconductor Group 4 1998-03-01 High Voltage Subscriber Line IC HV-SLIC PEB/F 4065 Version 1.1 SPT Type Ordering Code Package PEB/F 4065 on request P-DSO-20-5
1 Overview
The High Voltage Subscriber Line IC PEB 4065 is a rugged and reliable interface between the telephone line and the SLICOFI, a low voltage Subscriber Line Interface and Codec Filter IC. It is fabricated in a Smart Power Technology offering a breakthrough voltage of at least 170 V. The PEB 4065 provides battery feeding between – 24 V and – 80 V and internal ringing injection with a differential ring voltage up to 85 Vrms. In order to achieve these high amplitudes an auxiliary positive battery voltage is used during ringing. This voltage can also be applied in order to drive very long telephone lines. The SLIC is designed for a voltage feeding – current sensing line interface concept and provides sensing of transversal and longitudinal current on both wires. A power-down mode offers reduced power consumption at full functionality; in the power denial mode the device is switched off turning the line outputs to a high impedance state.
1.1 Features
- High voltage line feeding
- Internal ring and metering signal injection
- Sensing of transversal and longitudinal line current
- Reliable 170 V Smart Power Technology
- Battery voltage – 24 V … – 80 V
- Boosted battery mode for long telephone lines and up to 85 Vrms balanced ringing
- Polarity reversal
- Small P-DSO-20-5 power package
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1.2 Functional Description
The PEB 4065 supports AC and DC control loops based on feeding a voltage Vab to the line and sensing the transversal line current Iab (Figure 2). It converts a unipolar input voltage V2W into a differential output voltage Vab with an AC receiving gain of Gr = V abAC /V 2WAC = 40. This is accomplished by converting the input voltage to a current which is used to transpose the low voltage signals of the interface to the high voltage line feeding section. This current is reconverted to two voltages of opposite phase which are referenced to the positive and negative supply voltage, respectively. Thus the differential DC line-voltage in all normal polarity modes except ringing is related to the input voltage by VabDC = V BAT – V HINT + Vfix–4 0× V2WDC VBAT negative battery voltage VHINT internal positive supply voltage Vfix internal voltage drop of supply filter (appr. 2 V). Depending on the operation mode, V HINT is switched either to VH (VHINT = VH –1V ) o r t o BGND ( VHINT = – 0.5 V) via the supply switch. ITB10371 Buffer Buffer Current sensor Differential Supply Control V/I Converter Reference Switch I/V-Converter Supply V PDN AGNDBATVV BIM SS V DDV RING TIP Vab BGND HINTV aΙ Ιb VBAT VH ΙTL Ι
Semiconductor Group 6 1998-03-01 Controlled by C2, the polarity of V ab can be reversed and the DC-line-voltage then is VabDC =–( VBAT – VHINT + V fix–4 0× V 2WDC ). The transversal and longitudinal currents are measured in the buffers and scaled images are provided at the IT and IL pin, respectively: IT =(Ia + Ib)/100 =Iab/50 IL =–( Ia – Ib)/100 = –ILong/50. The PEB 4065 operates in four modes controlled by ternary logic signals at the C1 and C2 input. Additionally, in the active modes a polarity reversal of the output voltage can be programmed (see Table 1). Power down (PD): Power consumption is reduced by decreasing bias current levels. All functions operate at some small performance reductions. In this mode each of the line outputs can be programmed to show high impedance. HI b switches off the TIP buffer, while the current through the RING output still can be measured by IT or IL. Programming HI a reverses the polarity and switches off the RING buffer. Conversation (CONV): This is the regular transmit and receive mode for voiceband and teletax. The line driving section is operated between V BAT and BGND. Boosted battery (BB): In order to drive longer telephone lines an auxiliary positive battery voltage VH is used, enabling a higher DC-voltage across the line. Ringing (RING): This mode also uses the auxiliary voltage VH in order to provide a balanced ring signal of up to 85 Vrms. The ring tone without any DC-component has to be switched to the V2W input. Internally a DC-voltage is superimposed. This voltage is proportional to the total supply voltage VH – VBAT and amounts to typically 23 V at V H – VBAT = 120 V. The current sensing functions are available for ring trip detection. The Power Denial (PDN) state is intended to reduce power consumption of the linecard to a minimum: the PEB 4065 is switched off completely by connecting the PDN pin to V DD , no operation is available. With respect to the output impedance of TIP and RING two PDN-modes have to be distinguished. A resistive one (PDNR) provides a connection of 15 kΩ each from TIP to BGND and RING to VBAT , respectively, while the outputs of the buffers show high impedance (Figure 3). The other mode (PDNH) offers high impedance at TIP and RING. It is entered when, in addition to connecting PDN to VDD , the programming inputs C1, C2 are tied to V IL. All other combinations of C1, C2 yield the resistive power denial state PDNR.
Semiconductor Group 7 1998-03-01 NP Normal Polarity RP...Reverse Polarity HI a RP Ring wire set to high impedance HI b NP Tip wire set to high impedance Figure 2 Definition of Output Current Directions Table 1 Programming of Operation Modes C2 (Pin 13) V IL V IZ V IH C1 (Pin 12) V IL RING RP RING NP HI a RP V IZ BB RP BB NP HI b NP V IH CONV RP CONV NP PD NP ITS10372 Buffer Buffer ΙLong LongΙ Ιa bΙ Ιab abV RING TIP LZ Ιab = (aΙ + Ιb) /2 ) /2bΙ-Ιa= (LongΙ Z L
Semiconductor Group 8 1998-03-01 Figure 3 TIP and RING Impedance in Power Denial ITS10373 HIZ HIZ TIP RING BGND VBAT TGR 15 kΩ PDNRPDNH PDNRPDNH Ω15 k R RB
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1.3 Pin Description
Figure 4 Pin Configuration (top view) Table 2 Pin Definition and Functions Pin No. Symbol Type Input (I) Output (O) Function 1, 10, 11, VBAT Supply Negative battery supply voltage (– 24 … – 80 V), referred to BGND
2 RING O Subscriber loop connection, negative wire in
normal polarity; direction of positive Ia current out of this pin
3 TIP O Subscriber loop connection, more positive wire in
normal polarity; direction of positive Ib current into this pin 4 – N.C. Not connected
5 VH Supply Auxiliary positive battery supply voltage
(0 … + 90 V) used in ringing and boosted battery mode
6 BGND Supply Battery ground: TIP, RING, VBAT and V H refer to this
7 VDD Supply Positive supply voltage (+ 5 V), referred to AGND
P-DSO-20-5 (11 mm) BATV RING TIP N.C. AGND C2 BGND AGND PDN 20 1 ITP10374 V H V DD V 2W V BIM V BATBATV V SS BATV Due to reverse bending of the leads, the numbering of the pins is also reversed. LΙ ΙT
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8 V 2W I Two wire input voltage; multiplied by + 20 and – 20,
respectively, it appears at the TIP and RING outputs
9 V BIM O Down scaled image of the total supply voltage
(VHINT – VBAT ); scaling factor 40
12 PDN I/O Power denial, reference output when connected to
ground via a resistor, switches the device off when connected to V DD 13, 16 AGND Supply Analog ground: VDD , VSS and all signal and control pins with exception of TIP and RING refer to AGND
14 C1 I/O Ternary logic input, controlling the operation mode;
in case of thermal overload this pin sinks a current of typ. 550µA
15 C2 I Ternary logic input, controlling the operation mode
IT O Current output representing the transversal current scaled down by 50; In normal polarity this pin sinks the IT current.
18 IL O Current output representing the longitudinal current
scaled down by 50; For Ilong flowing out of TIP and RING this pin sinks the IL current.
19 V SS Supply Negative supply voltage (– 5 V), referred to AGND
Table 2 Pin Definition and Functions (cont’d) Pin No. Symbol Type Input (I) Output (O) Function
Electrical Characteristics
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2 Electrical Characteristics
2.1 Absolute Maximum Ratings
Note: Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. 1) See Test Figure 10. Table 3 Parameter Symbol Limit Values Unit Condition min. max. Battery voltage V BAT – 90 0.5 V referred to BGND Auxiliary supply voltage V H – 0.5 90 V referred to BGND Total battery supply voltage, continuously V H – VBAT – 160 V – Total battery supply voltage, pulse < 1 ms V H – VBAT – 170 V – VDD supply voltage V DD – 0.4 5.5 V referred to AGND VSS supply voltage V SS – 5.5 0.4 V referred to AGND Ground voltage difference V BGND – VAGND –0 . 5 0 . 5 V – Junction temperatureTj – 150 °C – Input voltages V 2W , V C1 , V C2 VSS –0 . 3VDD +0 . 3 V – Voltages on current outputs V IT, V IL –3 . 5 VDD +0 . 3 V – Voltages on PDN V PDN –0 . 3 VDD +0 . 3 V – RING, TIP voltages, continuously V a, Vb VBAT –0 . 3VH +0 . 3 V – RING, TIP voltages, pulse < 1 ms1) V a, Vb VBAT –1 0 VH +1 0 V – RING, TIP voltages, pulse < 1µs V a, Vb VBAT –3 0 VH +3 0 V – ESD-voltage, all pins – – 1 kV Human body model
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2.2 Operating Range
Note: In the operating range the functions given in the circuit description are fulfilled.
2.3 Thermal Resistances
Parameter Symbol Limit Values Unit Condition min. max. Battery voltage VBAT – 80 – 24 V referred to BGND Auxiliary supply voltage VH 5 85 V referred to BGND Total battery supply voltageVH – VBAT – 150 V – V DD supply voltage VDD 4.75 5.25 V referred to AGND V SS supply voltage VSS – 5.25 – 4.75 V referred to AGND Ground voltage difference – – 0.3 0.3 V – Ambient temperature Tamb 0 –4 0 PEB 4065 PEF 4065 Voltage compliance IT, IL VIT, VIL –3 3 V – Input range V 2W V2W – 3.2 + 3.2 V RING – 3.2 0 V CONV, PD, BB Table 5 Parameter Symbol Limit Values Unit Condition Junction to case Rth, jC 5K / W – Junction to ambient Rth, jA 20 K/W with heatsink, typ.
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2.4 Electrical Parameters
Min/max values are valid within the full operating range. If PEB- and PEF-specifications are different, both values can be found in the respective column. Testing is performed according to the test figures with external circuitry as depicted in Figure 4. Unless otherwise stated, load impedance RL = 600Ω . Test temperatures are voltages refer to VBAT = – 70 V and VH =+6 0V .
- VSS current ISS PD – 0.3 0.4 mA 1
- VBAT current IBAT PD – 3.3 4.3/4.4 mA 1
- VH current IH PD – 1 10 µA 1
- VBAT current IBAT CONV – 4.0 5.8/5.9 mA 1
- VH current IH CONV – 1 10 µA 1
Semiconductor Group 14 1998-03-01 1) IBAT and IH depend on the value of V 2W : IBAT (V 2W )= IBAT(0) +|V2W |/440Ω typ. (PD, CONV, BB) IH (V 2W )= IH(0) +|V 2W |/440Ω typ. (BB) Boosted Battery Mode Normal and Reverse Polarity V 2W =–0 . 5V1) 15. VDD current IDD BB –0 . 8 1 . 0 m A 1 16. VSS current ISS BB – 1.7 2.0 mA 1 17. VBAT current IBAT BB – 4.0 6.1/6.2 mA 1 18. VH current IH BB – 3.0 4.8 mA 1 19. Quiescent power dissipation P Q BB – – 740 mW 1 Ringing Mode Normal and Reverse Polarity V 2W =0V 20. VDD current IDD RING – 2.3 2.6 mA 1 21. VSS current ISS RING – 2.8 3.2 mA 1 22. VBAT current IBAT RING – 8.8 12/12.5 mA 1 23. VH current IH RING – 7.1 10 mA 1 24. Quiescent power dissipation P Q RING – 1300 1500 mW 1 Table 6 Supply Currents and Power Dissipation (cont’d) No. Parameter Symbol Mode Limit Values Unit Test Fig.min. typ. max. PEB/PEF
Semiconductor Group 15 1998-03-01 Table 7 DC-Characteristics No. Parameter Symbol Mode Limit Values Unit Test Fig. Test Condition min. PEB/ PEF typ. max. PEB/ PEF Line Termination TIP, RING 25. Power down DC line voltage |Vab,DC|P D 4 6 4 9 5 2 V 2 V2W =–0 . 5V 26. PD – 14 – 11 – 8 V V2W =–2V 27. Conversation DC line voltage Vab,DC| CONV 65 66.5 68.5 V 2 V2W =0V 29. CONV – 14 – 12.2 – 10.4 V V2W =–2V 30. Ringing DC line voltage |Vab,DC| RING 22.1 25 27.7 V 2 V2W =0V 31. Output current limit |Ia,max|, |Ib,max| PD others 130 130/ 135 mA mA V2W =–0 . 5V Va, Vb acc. to Test Figure 3 32. Loop open resistance TIP to BGND RTG PDNR 12/11 15 18/19 k Ω 9 Ib =2m A 33. Loop open resistance RING to VBAT RRB PDNR 12/11 15 18/19 k Ω Ia =2m A 34. Power denial output leakage current ILeak,a PDNH – 30 – 30 µA– VBAT < Va < VH 35. ILeak,b –3 0 – 3 0 µA VBAT < Va < VH 36. High impedance output leakage current ILeak,a HI a – 30 – 30 µA– VBAT < Va < VH-3 37. Ileak,b HI b – 30 – 30 µA VBAT < Vb < VH-3
Semiconductor Group 16 1998-03-01 Reference Voltage Outputs PDN, V BIM 38. Output voltage on PDN V ref all 1.15 1.25 1.35 V 1 – 39. Battery image voltage V BIM CONV, PD 40. BB, RING Two-wire Input V 2W 41. Input currentI2W all – 30 – 30 µA– – 3 . 2 V < V2W <3 . 2V 42. Input capacitance Current Outputs IT, IL V 2W =–0 . 5V 43. IT output current |IT|P D , CONV ––1 5 µA2 Ia = Ib =0 44. PD, CONV 380 420 µA Ia = Ib =2 0m A1) 45. CONV 0.95 1.05 mA Ia = Ib = 50mA 1) 46. RING 20 µA Ia = Ib =0 47. IL output current |IL|P D , CONV ––3 0 µA2 Ia = Ib =0 48. PD, CONV 30 µA Ia = Ib =2 0m A1) 49. PD, CONV 65 135 µA Ia =1 5m A , Ib =2 5m A 50. CONV 180 320 µA Ia =3 7 . 5m A , Ib =6 2 . 5m A Table 7 DC-Characteristics (cont’d) No. Parameter Symbol Mode Limit Values Unit Test Fig. Test Condition min. PEB/ PEF typ. max. PEB/ PEF
Semiconductor Group 17 1998-03-01 1) Polarity of Ia and Ib is reversed for measurement in reverse polarity mode Note: The listed characteristics are ensured over the operating range of the integrated circuit. Typical characteristics specify mean values expected over the production spread. If not otherwise specified, typical characteristics apply at TA =2 5°C and the given supply voltage. Control Inputs C1, C2 51. H-input voltage VIH all 2 –– V – – 52. Z-input voltage VIZ all – 0.8 – 0.8 V – – 53. L-input voltage 54. Input leakage current ILeak all – 5 – 5 µA – –5V< VC1(2) <+5V 55. Thermal overload current C1 Itherm all 500 550 – µA– VC1 =–3 . 2V 56. Switching Temperature (guaranteed by design) Tjoff Tjon all all 165 145 Table 7 DC-Characteristics (cont’d) No. Parameter Symbol Mode Limit Values Unit Test Fig. Test Condition min. PEB/ PEF typ. max. PEB/ PEF
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2.5 AC-Characteristics
(Normal and reverse polarity unless otherwise stated) Table 8 No. Parameter Symbol Mode Limit Values Unit Test Fig. Test Condition min. typ. max. PEB/ PEF Line Termination TIP, RING 57. Receive gain Gr CONV, BB 31.92 32.04 32.16 dB
4 V 2W,AC =5 0m V r m s
f= 1015 Hz Iab =2 0m A 58. CONV 31.88 32.04 32.2 dB Iab =5 0m A 59. Gain flatness (guaranteed by design) dGr CONV, BB – 0.05 – 0.05 dB – 300 Hz < f< 3400 Hz V 2W,AC =5 0m V r m s 60. Gain tracking (guaranteed by design) dGr CONV – 0.2 – 0.2 dB – 3 dBm0 > Vab > –2 0d B m 0 f= 1015 Hz 61. Total harmonic distortion V ab THD CONV – – 0.3 % 4 V 2W,AC =5 0m V r m s f= 1015 Hz Iab =2 0m A 62. Teletax distortion THDTTX CONV –– 3% 5 f=1 6k H z R L = 200Ω Iab =5 0m A V ab,AC =2V r m s 63. – – 3 % V ab,AC =5V r m s Iab =0m A , V ab =5 5V 64. – – 5 % V ab,AC =2V r m s 65. Psophometric noise N P, Vab CONV – – – 75 dBmp 4 Iab =3 0m A 66. Longitudinal to transversal rejection ratio V long/V ab LTRR CONV 61/58 – – dB 6 V long=3V r m s 300 Hz <f<3 . 4k H z Iab =3 0m A 67. Transversal to longitudinal rejection ratio V ab/Vlong TLRR CONV 50 – – dB 7 V 2W,AC = 150 mVrms 300 Hz <f<3 . 4k H z Iab =3 0m A
Semiconductor Group 19 1998-03-01 68. Power supply rejection ratio VBAT /V ab PSRR CONV, BB PD dB dB 4 300 Hz < f< 3.4 kHz V Supply,AC = 100 mVp Iab =3 0m A 69. VH /Vab BB 33/30 40 – dB 70. VDD /Vab CONV, BB 33 50 – dB 71. VSS /Vab CONV, BB 33 50 –d B dB 72. Ringing voltage VRING RING 67 – – Vrms, diff
8 R L =1k Ω
C L =1 µF f=6 6H z V 2W = 1.7 Vrms 73. Ringing voltage with extended V H 84 – – Vrms, diff
8 V H =8 0V
f=2 0H z V 2W = 2.2 Vrms 74. Ringing distortion THD RING – – 4 % 8 f=6 6H z V 2W = 1.7 Vrms Transversal Current Output IT 75. Transversal current ratio Git CONV, BB 33.89 33.98 34.07 dB
4 V 2W = 50 mVrms
f= 1015 Hz Iab =2 0m A 76. CONV 33.89 33.98 34.07 dB Iab =5 0m A 77. Gain flatness (guaranteed by design) dGit CONV, BB – 0.05 – 0.05 dB – 300 Hz < f< 3400 Hz V 2W,AC = 50 mVrms Iab =2 0m A 78. Gain tracking (guaranteed by design) dGit CONV – 0.2 – 0.2 dB – 3 dBm0 > V ab > –2 0d B m 0 f= 1015 Hz 79. Total harmonic distortion VIT THD, IT CONV – 0.01 0.3 % 4 V 2W,AC =5 0m V r m s f= 1015 Hz Iab =1 5m A Table 8 (cont’d) No. Parameter Symbol Mode Limit Values Unit Test Fig. Test Condition min. typ. max. PEB/ PEF
Semiconductor Group 20 1998-03-01 80. Psophometric noise N P, VIT CONV –– – 1 0 0 -97 dBmp 4 Iab =3 0m A , T > 00C -400C<T<0 0C 81. Frequency response V IT/V2W (guaranteed by design) Amplitude –C O N V – 0.5 1.7 1.95 dB f= 200 kHz V 2W,AC =5 0m V r m s ILine=2 0m A C s =0 . 2n F 82. Phase 100 – – deg 83. Longitudinal to transversal current output rejection ratio V long/V IT LITRR CONV 75 – – dB
6 V long=3V r m s
Iab =3 0m A 300 Hz < f< 3.4 kHz 84. 81 – – dB f= 1015 Hz 85. Power supply rejection ratio V BAT /V IT PSRR CONV, PD 50 60 – dB 4 300 Hz < f< 3.4 kHz V supply,AC= 100 mVp Iab =3 0m A 86. V H /V IT BB 50 60 – dB 87. V DD /V IT CONV 50 60 – dB 88. V SS /VIT CONV 50 60 – dB Table 8 (cont’d) No. Parameter Symbol Mode Limit Values Unit Test Fig. Test Condition min. typ. max. PEB/ PEF
Semiconductor Group 21 1998-03-01 Note: Exceeding the min./max. limits can cause stability problems! Table 9 External Elements in the Application Circuit (Figure 5) Typical values are used in the test circuits, unless otherwise specified. Ext. Part Function Typ. Value Tolerance Limit Values Comment min. max. R1 Biasing, current reference 25 kΩ –– 5 0 k Ω power dissipation increases with smaller R2, R3 IT, IL gain adjustment 1k Ω 0.1% (rel.) – – clipping for IT × R2 >3V or IL × R3 >3V RS Protection, isolation of capacitive load R5, R6 Protection 50 Ω 0.1% (rel.) – – – C 1 C for the internal supply voltage filter 22 µF f3dB ≈ 3H z ) 20% 10 nF – f3dB increases with smaller C 1, causing worse low frequency PSRR from V BAT C S Suppression of voltage spikes, frequency compensation 15 nF 5% (rel.) 200 pF 20 nF – C 2, C 3 VDD , VSS supply voltage blocking 1 µF 20% 10 nF – C 2, C 3 >1 µF and C 4 ≈ C 5 allows arbitrary switching sequence of all supply voltages incl. C 4 VH blocking 100 nF – – – C 5 VBAT blocking 100 nF 20% 100 nF – ground
Semiconductor Group 22 1998-03-01 Figure 5 Application Circuit ITS10506 TIPC1 PEB 4065 DDV SSV BATV C 2 1 µ F Fµ1 C 4 100 nF 100 nF
5 V -5 V 60 V -70 V
7 19 5 1, 10, 11, 20 + 1C F/10 Vµ22 1 k R IL ΩΩ ITR 1 k BGND AGND 17 18 6 13 16 9 24.9 k R 1 Ω V2W PDN SR R 6 Ω 5130 R S Ω Ω30 51 Ω C S 15 nF 15 nF SC Subscriber Line SLICOFI PEB 3065 RING b a Careful symmetrical board layout with respect to a and b Connect close to pin 16 5 V VH BIMVΙTT Ι
Semiconductor Group 23 1998-03-01 Test Figure 1 DC Characteristics and Power Dissipation ITS10507 TIP PEB 4065 BIMV SSV BATV V2W PDN AGND V DD ILR R IT VH VSS DD VV BAT H V VBIM BIMC SSΙΙ HBATΙΙDD RING BGND PDNR VREF V DD PDN See Testcond. LΙΙ T
Semiconductor Group 24 1998-03-01 Test Figure 2 DC Line Voltage and Currents ITS10508 RING PEB 4065 BIMV SSV BATV V2W PDN AGND V DD VH VSS DD VV BAT H V BIMC TIP BGND See Testcond. 25 kΩ abV Ιa bΙ TΙΙL LΙΙ T
Semiconductor Group 25 1998-03-01 Test Figure 3 Output Current Limit Test Figure 4 Receive Gain, Transversal Current Ratio, THD, Noise and Power Supply Rejection ITS10509 RING PEB 4065 BIMV SSV BATV V2W PDN AGND V DD VH VSS DD VV BAT H V BIMC TIP BGND See Testcond. 25 kΩ aVΙa, max b, maxΙ ILRR IT Vb TΙΙL aVV b, : BGND / BATV in PDN, CONV BGND in BB, RING ITS10510 TIP PEB 4065 BIMV SSV BATV V2W PDN AGND V DD VH VSS DD VV BAT H V BIMC RING BGND See Testcond. 25 kΩ ILRR IT DC and AC 2W, DCV V2W, AC VIT, AC SR R S LR Vab, AC rG = ab, ACV V2W, AC IT, ACV Vab, AC=G IT 1000 660 TΙΙL
Semiconductor Group 26 1998-03-01 Test Figure 5 Teletax Distortion Test Figure 6 Longitudinal to Transversal Rejection Ratio ITS10511 TIP PEB 4065 BIMV SSV BATV V2W PDN AGND V DD VH VSS DD VV BAT H V BIMC RING BGND See Testcond. 25 kΩ ILRR IT 2W, DCV V2W, AC SR R S LR Vab, AC2 µF TΙΙL ITS10512 TIP PEB 4065 BIMV SSV BATV V2W PDN AGND V DD VH VSS DD VV BAT H V BIMC RING BGND See Testcond. 25 kΩ ILRR IT 2W, DCV V IT SR R S Vab, AC R L/2 L/2R ~~ LongV TΙΙL
Semiconductor Group 27 1998-03-01 Test Figure 7 Transversal to Longitudinal Rejection Ratio Test Figure 8 Ringing ITS10513 TIP PEB 4065 BIMV SSV BATV V2W PDN AGND V DD VH VSS DD VV BAT H V BIMC RING BGND See Testcond. 25 kΩ ILRR IT 2W, DCV SR R S Vab, AC R L/2 L/2R Long, ACV V2W, AC TΙΙL ITS10514 TIP PEB 4065 BIMV SSV BATV V2W PDN AGND V DD VH VSS DD VV BAT H V BIMC RING BGND See Testcond. 25 kΩ ILRR IT 2WV SR R S VRING LR C L TΙΙL
Semiconductor Group 28 1998-03-01 Test Figure 9 Output Resistance in PDNR Mode Test Figure 10 TIP, RING Overvoltage Pulses ITS10515 TIP PEB 4065 BIMV SSV BATV V2W PDN AGND V DD ILR R IT VH VSS DD VV BAT H V BIMC SSΙΙ HBATΙΙDD RING BGND PDNR V DD PDN See Testcond. TIPV RINGV VBAT Ιb aΙ V BAT TΙΙL ITS10516 TIP PEB 4065 BIMV SSV BATV V2W PDN AGND V DD ILR R IT VH VSS DD VV BAT H V VBIM BIMC SSΙΙ HBATΙΙDD RING BGND PDNR VREF V DD PDN 30 Ω Ω30 HV +10 V / 1 ms +20 V / 1 sVH BATV -10 V / 1 ms -20 V / 1 sVBAT µ TΙΙL µ
Semiconductor Group 29 1998-03-01
3 Package Outlines
(Plastic Dual Small Outline Package) GPS05755 Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. Dimensions in mmSMD = Surface Mounted Device