PEB3465

PEB4165 SIEMENS | Alldatasheet

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SIEMENS PEB 3465, PEB 31665, PEB 4165 Introduction

1 Introduction

The MuUSLIC, a chipset of three highly sophisticated ICs, bridges the gap between the analog and the digital signal transmission in modern telecommunication systems. This highly integrated chip set supports to realize an extremely compact Analog Subscriber Line Interface Module. Only a few external components are required and there is no trimming or adjustment necessary to meet worldwide recommendations. Each device is made of the best fitting technology (CMOS, BiCMOS and Smart Power Technology) and the standard SMD-packages P-MQFP and P-DSO are used. The chipset consists of the following three ICs: + PEB 31665 (MuPP Multichannel Processor for POTS) + PEB 3465 (QAP. Quad Analog POTS) + PEB 4165 (AHV-SLIC — Advanced High Voltage Subscriber Line Circuit) Semiconductor Group 6 04.97

Multichannel Subscriber Line Interface Concept PEB 3465 MuSLIC PEB 31665 PEB 4165 Version 1.0 CMOS

11 Features

• Chip set of three well fitted chips optimized for a

16 POTS-base system

• Including all low and high voltage SLIC functions Le * Only a few external components are required lm ee + No trimming or adjustments are required ~ * Specification according to relevant ITU-T, LSSGR and DTAG recommendations P-MQEFP-80-1 * Digital signal processing technique + Advanced low power CMOS and BiCMOS" and Smart Power technology + PCM encoded digital voice transmission (A-Law or u-Law) _ + Two serial IOM-2 (GCI) Interfaces with together 6 pins ge * 12 Pin, 8 bits parallel microcontroller interface + High performance AD and DA Conversion + Programmable digital filters for P-MQFP-44-2 — Impedance matching — Transhybrid balancing — Frequency response — Gain + Advanced test capabilities — Integrated line and circuit tests EA — Two programmable tone generators Sis P-DSO-20 ‘) Abbreviations see chapter 10.3 Type Ordering Code Package PEB4i6sVi0ssonrequest = CCP SOPOC Semiconductor Group 7 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Introduction + Fully digital programmable DC-Characteristic — Programmable Constant Current from 0 to 50 mA — Programmable Resistive Values from 0 to 2 x 500 2 —- Programmable Constant Voltage + Programmable Integrated Teletax Injection and Filtering during Active in Onhook and Offhook — Programmable up to 10 Vrms at Ring/Tip-wire of the AHV-SLIC — Programmable frequency (12/16 kHz) + Polarity reversal (programmable soft or hard) * Integrated (balanced) Ringing Generation with zero crossing injection — Programmable frequency between 16.6 and 70 Hz — Programmable amplitude up to 85 Vrms at Ring/Tip-wire of the AHV-SLIC + Three operating modes: Power Down, Active and Ringing * Offhook detection with programmable thresholds for all operating modes « Integrated Ring Trip Detection with zero crossing turn off function * Ground Start and Loop Start possible + Integrated checksum calculation for CRAM (AC and DC separated) + Linecard Identification + Sensing of transversal and longitudinal line current + Boosted battery mode with up to 150 V supply for long telephone lines and up to

85 Vrms balanced ringing

+ Reliable 170 V Smart Power Technology + Standard SMD packages: P-MQFP-44 and P-MQFP-80 for the low voltage parts and small power package P-DSO-20 for the high voltage device Semiconductor Group 8 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Introduction

1.2 Logic Symbol (PEB 3465)

74 ITA VO1-A 4

channel A 72 ITACA WA 6 channel A

73 VR-A oA >

75 DCP-A

. V0-Pins opeeeive 76 DONA K—> channel B rannel A 77 ACP-A

78 ACN-A

74 ILA k= channel c

K— channel D supply 4 VDD-A channel A 3 GND-A ADU 54 transmit ADD 5, Interface — AFSC 52} 16,384 MHZ channel B PEB 3465 Ape. 5 : receive Vem channel B Supervision 4» QAP ADR 4g<— Select QAP channel B RESET 4: Reset supply channel B => vbDI 5G digital transmit GNDI 4g supply channel 9 receive A channel C Supervision “—» VA 0 channel C ve 5 analog supply inputs channel C VBIM 8 transmit A channel D recelve > VDDZ 11 channel D GNoz 12) central Supervision “—» analog ie D vss 13) supply channel D RREF 14 Figure 1 Semiconductor Group 9 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Introduction

1.2.1 Pin Configuration (PEB 3465)

aaigif <6 $a feazaa tizazaq qd aa >on a 2a 2900 SogesSasFeeeSsgaeess 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 VDD-A - 8 VDD-D O1-A y 8 01-D GND-A eo lan 8 GND-D VOt-A . C) 5 vo1-D VO2-A a 8 vo2-D 11-A o 8 n-D Nc ~ 3 ADU vBIM ° 8 ADD VB © PEB 3465 g AFSC VA 3 & ADCL vppz 2 P-MQFP-80-1 3 vob! GNDZ 8 g GNDI vss 3 3 ADR RREF = ba RESET n-B a ¢ ike) v02-B a ¢ vo2-c v01-B Ey Bs V01-C GND-B ® g GND-C 01-B o g o1-¢ VDD-B 8 = VDD-c 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 a a a a a a a a NrZzazasS Gh ORE @adcdzazrn o°2288 7 FE #7 88ee°° Figure 2 Semiconductor Group 10 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Introduction

1.2.2 Pin Definition and Functions (PEB 3465)

The following tables group the pins according to their functions. They include pin number, pin name, type, a brief description of the function, and cross-references referring to the sections in which the pin functions are discussed. Table 1.‘ Pin Definition and Functions (PEB 3465) Power Supply Pins

1 VDD-A_|- [+5 V Analog Supply Voltage (channel A)

20 VDD-B |- _|+5V Analog Supply Voltage (channel B)

41 VDD-C |- | +5 V Analog Supply Voltage (channel C)

60 VDD-D |- | +5 V Analog Supply Voltage (channel D)

3 GND-A l- | Analog Ground (channel A)

18 GND-B |- | Analog Ground (channel B)

43 GND-C |- [Analog Ground (channel C)

58 GND-D |= [Analog Ground (channel D)

11 VDDZ |- | +5 V Analog Supply Voltage (bias)

12 GNDZ [- [Analog Ground (bias)

13 [vss [= _| -5 V Analog Supply Voltage 50 vpDI [- _|+5V Digital Supply Voltage

49 GnDI |- [Digital Ground

Interface Pins to MuPP (PEB 31665) 54 [ADU [© _ [Analog Data Upstream 53 laDD [l| Analog Data Downstream 51 ADCL |! [Analog Data-Clock 52 AFSC | Analog Frame-Sync. 48 [ADR [I _| Select odd or even port nr. 47 RESET |! _[Interface-Reset Semiconductor Group 11 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Introduction Table 1 Pin Definition and Functions (PEB 3465) (cont'd) Interface to AHV-SLIC (PEB 4165) 71___[WA [1 | Traneversal Current input (ACO), chan] 72 |ITAG-A |__| Transversal Curent input (AO), chan. A | 73 \\VRA_[I__[Reference input chan.A | 74 [ILA —_|1__[Longfuinal Current input chan. A | 77__|AOP-A_|O | Two Wire Output Votage (AGP), chan. A _| 7 |ACN-A_|O [Two Wire Output Votage (ACN), chan. A | 75__|DOP-A © | Two Wire Output otage (OCP), chan. A _| 76 [DGN-A [0 | Two Wire Output Votage (DCN), chan. A _| 80 [2A 0 | Digtalinteace to HV-SLIC, chan. A__| 30___|IT-B [I __[ Transversal Curent input (AC+DO), chan. B| 29___|ITAC-B [I __| Transversal Curent nput(AO). chan. 8 _| 28 |VRB |! [Reference mput,chanB | 27 [IB __[I__|Longfudinal Current Input chan B | 24 [AGP [0 __| Two Wie Output Votage (AGP), chan. B _| 29. [ACN-B 0 _|Two Wire Output Votage (ACN), chan. B _| 26 |DOP-B [O | Two Wire Output Votage (DOP), chan. B _| 25 |DONB [0 [Two Wire Output Votage (OCN), chan. B_| 21 [c268 [0 | Digtalintetace to HV-SLIC, chan. 8 | 3117-0 __[I__[ Transversal Curent input (ACD), chan. O| 32___|ITAC-O [I __| Transversal Curent input (AO). chan. © _| 39 VRC |! [Reference put, chanC | 34 [ILC [I [Longitudinal Curent input chan. © | 37 |AOP-6 [0 | Two Wire Output Votage (ACP), chan. | 38 [|AON-G [0 | Two Wire Output Votage (AGN), chan. O _| 35 [DOC [O | Two Wire Output Votage (DOP), chan. © _| 36 [D0N-c [0 | Two Wire Output Votage (DON), chan. C_| Semiconductor Group 12 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Introduction Table 1 Pin Definition and Functions (PEB 3465) (cont'd) Interface to AHV-SLIC (PEB 4165) (cont'd) 39 Digital Interface to HV-SLIC, chan. C 40 [c2-C [© _|Digital interface to HV-SLIC, chan. C 70 Li Transversal Current Input (AC+DC), chan. D 69 ITAC-D [ih | Transversal Current Input (AC), chan. D 68 lvRD [I | Reference Input, chan. D 67 [uo fr Longitudinal Current Input, chan. D 64 ACP-D |O [Two Wire Output Voltage (ACP), chan. D 63 ACN-D |O [Two Wire Output Voltage (ACN), chan. D 66 DCP-D |O _| Two Wire Output Voltage (DCP), chan. D 65 DCN-D |O _ | Two Wire Output Voltage (DCN), chan. D 62 Digital Interface to HV-SLIC, chan. D 61 [c2-D [0 | Digital interface to HV-SLIC, chan. D Semiconductor Group 13 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Introduction Table 1 Pin Definition and Functions (PEB 3465) (cont'd)

10 Pins

4 101-A User-Programmable I/O Pin, chan. A 5 102-A User-Programmable I/O Pin, chan. A 6 HWA fl | Fixed Input Pin, chan. A 2 fora [O | Fixed Output Pin, chan. A 17 (101-8 [vO | User-Programmable I/O Pin, chan. B 16 102-B User-Programmable I/O Pin, chan. B 15 Wwe fl | Fixed Input Pin, chan. B 19 o1B [oO | Fixed Output Pin, chan. B 44 101-C User-Programmable I/O Pin, chan. C 45 102-C User-Programmable I/O Pin, chan. C 46 (4-C [|__| Fixed Input Pin, chan. C 42 foc [Oo | Fixed Output Pin, chan. C 57 101-D User-Programmable I/O Pin, chan. D 56 102-D User-Programmable I/O Pin, chan. D 55 (H-D [1 [Fixed Input Pin, chan. D 59 (01-0 [0 | Fixed Output Pin, chan. D Miscellaneous Function Pins

14 RREF [h | External resistor to GNDZ

10 VA [ls Voltage sense a

9 ve [i | Voltage sense b

8 VBIM [th | Battery image sense input

7 [N.C. [= _| Not connected (not used) Semiconductor Group 14 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Introduction

1.2.3 Functional Block Diagram (PEB 3465)

o1 HY ve | a Sc 10 ao a ee OT eee Se cet net = VA vB vem vooz GNoz vss Figure 3 Semiconductor Group 15 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Introduction

1.3 Logic Symbol (PEB 31665)

csq 'p2 IDENTIFIKATION MICRO- WRQ ID3 CONTROLLER RDQ DIOO INTERFACE pice 101 Dio2 102 USER-PROGRAMMABLE Dios PEB 31665 (03 VO PINS 104 DIOS biog MuPP DIO7 abut 1sT1 TESTPIN ap ADD1 INTERFACE NOL pp1 ADU2 but ADD2 FSC, IoM 2 DcL INTERFACE RESET Boe Figure 4 Semiconductor Group 16 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Introduction

1.3.1 Pin Configuration (PEB 31665)

g£843898588 Csr e2oofaaaag yp 44 43 42 41 40 39 38 37 36 35 34 © FSC ~ 3 DIO4 DCL! Ny 8 DIO5 DD1 ie . m__._/pD106 DUu1. to $11 D107 vDD jo PEB 31665 11103 VSS[- To 0 a—!— VDD poz ~~ ~=©0 P-MQFP-44-2 3 a vss DU2\\ al TsT1 RESET © 1g 11102 loi Ts 3 VDD5 ADD1 1x QT ADD2 12 13 14 15 16 17 18 19 20 21 22 roradggneranrga 2negqgqgnkggaoga D a ===7F0 Figure 5 Semiconductor Group 17 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Introduction

1.3.2 Pin Definitions and Functions (PEB 31665)

The following tables group the pins according to their functions. They include pin number, pin name, type, a brief description of the function, and cross-references referring to the sections in which the pin functions are discussed. Table 2 _‘ Pin Definitions and Functions (PEB 31665) Power Supply Pins 6 [vss [= _ [Digital Ground 17 lvss |= __| Digital Ground 27 [vss [= _ [Digital Ground 38 vss |[- | Digital Ground 5 [vDD _|- _|+3.3 V Digital Supply Voltage 15 vDDP |= _[+3.3 V Digital Supply Voltage for PLL 16 [vDD —_|- _| +3.3 V Digital Supply Voltage 28 [voD |= _|+3.3 V Digital Supply Voltage 39 [voD f= + 3.3 V Digital Supply Voltage 24 vops |- [+5 V Digital Supply Voltage IOM®-2 Pins 4 [pur fo | 1’st IOM-2 Data Upstream (open drain) 3 [por ft 1’st IOM-2 Data Downstream 2 [pcL ft f1Om-2 Data-Clock 1 [Fsc ft IOM-2 Frame-Sync. 8 [pu2 fo | 2’nd |IOM-2 Data Upstream (open drain) 7 [poz ft 2’nd |OM-2 Data Downstream Semiconductor Group 18 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Introduction Table 2 ‘Pin Definitions and Functions (PEB 31665) (cont'd) MuPP/QAP Interface

11 ADD1 [O __[1’stQaP Data Downstream

12 ADU1 {I t’st QAP Data Upstream

13 AFSC |O [QAP Frame-Sync

14 ADCL |O [QAP Data-Clock

23 ADD2 lo | 2’nd QAP Data Downstream

22 Apu2|!_—_‘[2’nd QAP Data Upstream Microcontroller Interface 40 [cso ft uC Chip select 4 [ALE —|!_—_|wC Address latch enable 42 [RDQ |! __|wC Data-Clock read 43 [wRQ ft uC Data-Clock write 37 [pIc0jvo | uC Data / Address

36 DIO1 uC Data / Address

35 DIO2 uC Data / Address

34 DIO3 uC Data / Address

33 [DI04 «| VO wC Data / Address

32 DIOS uC Data / Address

31 [Dios [vO uC Data / Address

30 DIO7 uC Data / Address

10 User-Programmable I/O Pin

25 jio2jvo | User-Programmable I/O Pin

29 User-Programmable I/O Pin

44 [104 jv | User-Programmable I/O Pin Semiconductor Group 19 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Introduction Table 2 Pin Definitions and Functions (PEB 31665) (cont'd) Miscellaneous Function Pins 18 [ipo ft External Identification 19 fir ft External Identification 20 [i2 ft External Identification 21 [is ft External Identification

26 TST1 | Test Pin (must be connected to VSS)

Semiconductor Group 20 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Introduction

1.3.3 Functional Block Diagram (PEB 31665)

soot | QAP St 1OM2 poe | inter De. uz aM | face Wer DsP ue apee pe | CRAM [oc] Monitor (cost) ee a fe He ee a — FOO fn a Ea — ca Figure 6 Semiconductor Group 21 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Introduction

1.4 Logic Symbol (PEB 4165)

Semiconductor Group 22 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Introduction

1.4.1 Pin Configuration (PEB 4165)

VBAT |_| 20 1 VBAT wl 19 2 |] RING ir | 18 3.) tp “ss " bepaies | om AGND |_| 16 5 | va ACN || 15 6 _| vob P-DSO20-5 ACP LJ 14 7 C1 pen |_| 13 8 | oe pep | 12 9 | supFi veat | 11 10] vpat Figure 8 Semiconductor Group 23 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Introduction

1.4.2 Pin Definitions and Functions (PEB 4165)

Pin No. | Symbol Description 1,10,11, | VBAT Supply | Negative battery supply voltage (— 24 ... - 80 V), 20 referred to BGND

2 RING lo | Subscriber loop connection RING

3 imP fo Subscriber loop connection TIP

4 BGND Supply | Battery ground: TIP, RING, VBAT and VH refer to this

5 VH Supply | Auxiliary positive battery supply voltage (+ 5 ... + 85 V) used in ringing mode

9 SUPFI External capacitance for supply voltage filtering (internal

resistance of about 30 kQ)

6 Supply | Positive supply voltage (+ 5 V), referred to AGND

7 C1 vO Ternary logic input, controlling the operation mode; in

case of thermal overload this pin sinks a current of typ. 150 pA 8 cot Ternary logic input, controlling the operation mode 12,13 DCP,DCN Differential two wire DC-input voltage; multiplied by — 25 and related to (VH — VBAT) / 2, DCN appears at TIP and DCP at RING output, respectively 14,15 ACP,ACN Differential two wire AC-input voltage; multiplied by — 3.125, ACN appears at TIP and ACP at RING output, respectively

16 AGND Supply | Analog ground: VDD, VSS and all signal and control

pins with the exception of TIP and RING refer to AGND

17 Supply | Negative supply voltage (— 5 V), referred to AGND

18 IT Current output representing the transversal current

scaled down by a factor of 50.

19 IL Current output: longitudinal line current scaled down by

a factor of 50. Semiconductor Group 24 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Introduction

1.4.3 Functional Block Diagram (PEB 4165)

, Va ap | sensor [8 T song Ve TON ly Se 16 ko TIP ©) <1 | | = < DCN SUPR O E = O | pcp Ya a acs RING © [<1] = ACP rs Poo He AGND Vpp Ves 17809756 Figure 9 Semiconductor Group 25 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Introduction

1.5 System Integration

J— _ oe PEB 3465 |= Be a — ~ tie PEB 465 | Be ~ Nie ‘1 PEB 31656 1OM®-2 uC a = = [FPS PEB 3465 |< os PEB 4165 pp [ee Pe S| eases | ot — 3465 KS E-—— co i P-DSO-20-5 P-MQFP-80-1 P-MQFP-44-2 ay 11809757 Figure 10 Block Figure of an Analog Linecard for 16 Subscribers Using MuSLIC Semiconductor Group 26 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Introduction 1] tr ° [—_—_1 i "52 = — pep aces [Avie ° | PEB 4165 [2 >} QAP °s AHV-SLIC P.DSO-20-5 P-MQFP-80 : : PEB 31665 Jour PEB 2055. Lo» poy —— . ; 16] tr ° [ _—— "5 o-t}{ T+] Pes ates 6 ° | PEB 4165 [>| QAP. m ° AHV-SLIC P.DSO-20-5 P-MQFP-80 P-MQFP-44 11$09758 Figure 11 Application Example of a Central Office Analog Linecard for

16 Subscribers

Semiconductor Group 27 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Introduction vn VBAT VA VB vBIM a | Apel & e———4 anni ne : ft ac } re ee E ° \\ np Io vr RESET : © o- RESET ‘owe ff g 1Channel 4Channels | 16Channels \\# AHV-SLIC o acp QAP. q MuPP ° ® RING ? pcp ADR F-° : p= 3 cn 4 @ ADD2 : / of PLL lor re ‘SUPFI q RREF q q Figure 12 Overview of the Connection of MuPP, QAP and AHV-SLIC for One Subscriber Semiconductor Group 28 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Functional Description

2 Functional Description

The Multichannel Signal Processing Subscriber Line Interface Codec Filter Chipset, MuSLIC, is a logic continuation of the well established family of the SIEMENS PCM-Codec-Filter-ICs with the integration of all DC-feeding, Supervision and Meterpulse Injection features on chip as well. Fabricated in advanced CMOS, BiCMOS and High Voltage Technology SPT170 the MuSLIC is tailored for very flexible solutions in analog/digital communication systems. The chip set consists of the digital signal processor for 16 channels (MuPP, multichannel processor for POTS), the analog/digital and digital/analog converter for 4 channels (QAP, quad analog POTS) and the high voltage interface chip for 1 channel (AHV-SLIC, advanced high voltage subscriber line interface circuit). The MuPP uses the benefits of a DSP not only for the voice channel but even for line feeding and supervision which leads to a very high flexibility without the need of external components. Based on an advanced digital filter concept, the PEB 31665 (MuPP) and the PEB 3465 (QAP) provides excellent transmission performance. The new filter concept leads to a maximum of independence between the different filter blocks. Each filter block can be seen as a one to one representative of the corresponding network element. Together with the software package MuSLICOS, filter optimizing to different applications can be done in a clear and straight forward procedure. The AC frequency behavior is mainly determined by the digital filters. Using the oversampling 1 bit xA-AD/DA converters, linearity is only limited by second order parasitic effects. The digital solution of line feeding offers free programmability of feeding current and voltage as well as very fast settling of the dc-operating point after transitions. A 0.3 Hz lowpass filter in the DC-loop is mainly responsible for the system stability. Additionally teletax generation and filtering is implemented as well as free programmable balanced ring generation with zero-crossing injection. Offhook detection with programmable thresholds is possible in all operating modes. To reduce overall power consumption of the linecard, the MuPP, the QAP and the AHV-SLIC provide a Power Down mode. To program the MuSLIC or to get status information about the chipset or the system 2user interfaces are available: the IOM-2 interface and a 8-bit-parallel simple microcontroller interface. The PEB 4165 (AHV-SLIC) provides battery feeding between — 24 V and — 80 V and ringing injection with a differential ring voltage up to 85 Vrms. In order to achieve these high amplitudes, an auxiliary positive battery voltage is used during ringing. This voltage can also be applied to drive very long telephone lines. The AHV-SLIC is designed for a voltage feeding - current sensing line interface concept and provides sensing of transversal and longitudinal currents on both wires. In Power Down mode the AHV-SLIC is switched off turning the line outputs to a high impedance state. Off-hook supervision is provided by activating a simple line current sensor. Semiconductor Group 29 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Functional Description

21 Principles

2.1.1 Signal Flow Graph: AC

———> Transmit Path DHPX ——o afi [a], BE] [nl i ro al Cm [=r "aos PEB 3465 PEB 31665 “DR <1 Receive Path (| User Programmable Block | Functional Block Ey Fixed Filter Block nsoerso Figure 13 Transmit Path The analog input signal has to be connected to pin ITAC of the PEB 3465 by an external capacitor (470 nF) for AC/DC separation. After passing a programmable gain stage (AGX = 0 or 6 dB) and a simple antialiasing prefilter the voice signal is converted to a 1-bit digital data stream in the XA-converter. The first down sampling steps are done in fast running digital hardware filters on the PEB 3465. This down sampled AC-signal (64 kHz sampling rate) is sent to the PEB 31665 via the MuPP/QAP-Interface in the ADU-channel. The following signal processing is done in the DSP-machine of the PEB 31665. The benefits of this are the programmability of frequency and gain behavior. At the end the fully processed signal is transferred to the IOM-2 Interface in a PCM-compressed (A-law / \\1-law) signal representation. Semiconductor Group 30 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Functional Description Receive Path The digital input signal is received via the |OM-2 Interface of the PEB 31665. Expansion, PCM-lowpass-filtering, gain correction and frequency response correction are the next steps which are done by the DSP-machine. This 64 kHz AC signal is sent from the QAP to the MuPP via the MuPP/QAP-Interface in the ADD-channel. The up sampling interpolation steps are processed by fast hardware structures in the PEB 3465 to reduce the DSP-workload. The 1-bit data stream is then converted to an analog equivalent. A subsequent programmable gain stage (AGR = 0 or 6 dB) and smoothing filter provides the AC output signal at the Pins ACP and ACN of the PEB 3465 for direct connection to the AHV-SLIC PEB 4165. Loops There are two different loops implemented: The Impedance Matching (IM) loop which is divided into 2 separate loops to guarantee very high flexibility to various impedances, and the Transhybrid Balancing (TH) loop. For test purposes it is possible to close a loop behind the LA-converter to check either the analog of the digital part of the PEB 3465 and the PEB 31665 respectively.

2.1.2 Signal Flow Graph: DC

Lore liinorm | T [epee re | @ eee a ste a B B a ry O- - O OC Figure 14 Semiconductor Group 31 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Functional Description DC Characteristic The incoming information (transmit direction) at pin IT (scaled transversal AC + DC-current, transferred to a voltage via an external 1.5 kQ resistor at IT) passes first an antialiasing filter and is then converted to a 1-bit digital data stream in the LA-converter. Down sampling is done in hardware filters of the PEB 3465. This DC-information (2 kHz sampling rate) is then fed to the PEB 31665 where it is first lowpass filtered (0.3 Hz corner frequency) for stability and noise reasons. The following DC-characteristic consists of three branches which represents different kinds of feeding behavior. In typical applications it acts as a programmable constant current source (Rin > 30 kQ). If the desired value cannot be held feeding switches automatically and smoothly to the resistive branch (K;, programmable between 0 ... 1 kQ). The third branch is used for feeding long lines - the DC-characteristic switches to a constant voltage behavior. For superimposing voice as well as Teletax pulses the necessary drop at the line can be calculated and taken into account as well. The outgoing bit stream (2 kHz sampling rate), representing the DC-feeding value is then sent back to the PEB 3465 where a 1-bit 2A-converter and a following smoothing filter (using an external 33 nF capacitor) establish the desired values at the Pins DCP and DCN, respectively. Depending on the operating mode (Active, Ringing, Active with Boosted Battery) a gain of 0 or 4 dB is inserted. For test purposes it is possible to close a loop to test either the analog part or the digital part of the DC path. Supervision The HOOK-information is the most important one and is provided via the IOM-2 Interface (CIDU-4: HOOK; see chapter 4.2), in all operating modes: + Power Down: _In this state the transversal line current is sensed by the PEB 4165 and fed to the PEB 3465 via Pin IT. Offhook is detected if the voltage at IT exceeds a programmed value. + Active: Offhook is detected if the incoming voltage at IT exceeds a programmed value. To avoid instable information, lowpass filtering and a hysteresis is provided. + Ringing: Offhook is detected if the DC-value at IT exceeds the programmed Ring Trip threshold. The AC-value is filtered automatically. Ring Trip detection is reported within 2 cycles of the ring period and then the internal ring generator is switched off within 2 cycles at zero crossing of the ring voltage. For Ground Key information the PEB 4165 provides the longitudinal current information at the Pin IL. The PEB 3465 uses a LA-converter - similar to the DC-transmit path - to convert this signal to its digital representation. The accuracy is + 10% compared to + 5% of the DC-path. The 1-bit digital data stream is also down sampled and sent to the Semiconductor Group 32 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Functional Description PEB 31665 via the ADU-channel of the MuPP/QAP-Interface. Generation of the Ground Key bit is done in the PEB 31665 (CIDU-3: GNK; see chapter 4.2) Additional Features The PEB 3465 provides three general purpose input Pins (VA, VB, VBIM) for measuring. Via the MuPP/QAP-Interface it is possible to select one of these inputs for the measurement. The DC-signal at the selected input is converted to digital using the same xA-converter as for Ground Key information (accuracy of + 10%) and sent to the also possible to measure the internal VDDZ-voltage of the PEB 3465.

2.1.3 AHV-SLIC

The Advanced High Voltage Subscriber Line IC (AHV-SLIC) PEB 4165 is a reliable interface between the telephone line and the PEB 3465/PEB 31665. The PEB 4165 supports AC and DC control loops based on feeding a voltage Vp; to the line and sensing the transversal line current /p; (figure 15). DC- and AC-voltages are handled separately with different gain on the AHV-SLIC. Both are applied differentially via pins DCP, DCN, and ACP, ACN, respectively. The line voltages Vp and V; are the amplified input voltages, related to the mean supply voltage, V, = VTIP = (VH' — VBAT) / 2 — 25 x VDCN — 50/16 x VACN Va = VRING = (VH’ — VBAT) / 2 — 25 x VDCP — 50/16 x VACP. Depending on the operation mode, VH’ is switched either to VH or to BGND via the supply switch. The transversal line voltage Vat = Va — V+ is simply related to the input voltages Vat = 25 x (VDCP — VDCN) + 50/16 x (VACP — VACN) = 50 x VDCP + 6.25 x VACP A reversed polarity of Vp; is easily obtained by changing the sign of (VDCP — VDCN). The transversal and longitudinal currents are measured in the buffers and scaled images are provided at the IT and IL pin, respectively: IT= (Ip + Lyp)/100 = Ip7/50 IL = = (Ig — Iyip)/100= — I ong/50 Semiconductor Group 33 04.97

Table 3. Programming of Operating Modes off the RING buffer. In the mode HIRT both buffers show high impedance. Active (ACT): This is the regular transmit and receive mode for voiceband and teletax. The line driving section is operated between VBAT and BGND.

SIEMENS PEB 3465, PEB 31665, PEB 4165 Functional Description The Power Down (PDN) state is intended to reduce power consumption of the linecard to a minimum: the PEB 4165 is switched off completely, no operation is available. With respect to the output impedance of TIP and RING two PDN-modes have to be distinguished: A resistive one (PDNR) provides a connection of 10 kQ each from TIP to BGND and RING to VBAT, respectively, while the outputs of the buffers show high impedance (figure 16). The current through these resistors is sensed and transferred to the IT pin to allow offhook supervision. The other mode (PDNH) offers high impedance at TIP and RING. f FO ) eae . Rig LJ om FRG Feel] 10 FO 4 aR vest Figure 16 TIP and RING Impedance in Power Down

2.1.4 Test Features

There are two different kinds of test features: Internal test loops for circuit testing and defined test loops to perform board and line tests. There are loops for testing AC and DC path. As a special feature it is possible to switch signals to and from the DC-path via the IOM-2 Interface. Additionally there is the possibility to cut off the AC-receive and transmit path (the different kinds of testmodes are described in chapter 8). Semiconductor Group 35 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Interfaces

3 Interfaces

3.1 1OM®-2 Interface The IOM-2 Interface consists of two data lines and two clock lines. DU (data upstream) carries data from the MuSLIC to a master device. DD (data downstream) carries data from the master device to the MuSLIC. A frame synchronization clock signal (8 kHz, FSC) as well as a data clock signal (4096 kHz, DCL) has to be supplied to the MuSLIC. The MuSLIC handles data as described in the IOM-2 specification for analog devices (see chapter 10.1). 125 ps FSC DCL 4096 kHz - - bu | Detala_! DetallA - ACL CN BC . TrT09760 Figure 17 1OM®-2 Interface Timing for 8 Voice Channels (per 8 kHz frame) Semiconductor Group 36 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Interfaces 125 us ae FSC DCL 4096 kHz +t . | Detail | Detail B Woe. FSC ‘ DCL | | 11109761 Figure 18 IOM®-2 Interface Timing (DCL = 4096 kHz, per 8 kHz frame) Semiconductor Group 37 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Interfaces 1OM®-2 Time Slot Assignment An assignment of 16 time slots is given by the two IOM-2 interfaces of the MuPP. Each of them assigns 8 time slots synchronized with the FSC. This 8 slot structure is carried on from the MuPP to the QAP. In the QAP the assignment is partly done by pin-strapping (see figure 19). Channel SLOTO A +N) + suot2 : ADR . 2G INTERFACE SLOT 4 : QAP << |} SLOT6 P| | ADU1 > ADD1 DUI, SLOT 1 A —I 4 a SLOT3 ADR SLOTS : QAP «<—— SLOT7 D 1 ABSC FSC Channel ADCL MuPP pet SLOTS A — SLOT 10 ADR f SLOT 12 : QAP <— SLOT 14 bd 7 ADU2 + « ADD2 SLOTS A — uz, SLOT 11 . AOR , — 4 4 Dr. SLOT 13 : QAP << (sinc) SLOT 15 Dé i Time slot assignment Figure 19 Time Slot Assignment Semiconductor Group 38 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Interfaces 3.2 uC Interface The parallel C-Interface is used to communicate with an external master device and consists of four control lines (ALE, CSQ, RDQ, WRQ) and 8 bidirectional data lines (DIOO ... DIO7) and provides fast parallel data transfer to a microcontroller device as an alternative to the IOM-2 monitor channel data transfer. Only one method of transfer can be used at a time, with the C-Interface having a higher priority than the |OM-2 Interface. Thus, data transfer via the «C-Interface interrupts a communication via the IOM-2 monitor channel. During a data transfer cycle via the «C-Interface, |OM-2 monitor channel data will be ignored. The C/l-channel information is still transferred via the C/l-channel of the IOM-2 interface and is not affected by the ,C-Interface communication. The C-Interface of the MuPP has a multiplexed 8-bit address/data bus and allows direct connection to a microcontroller of the 8051- and the Siemens C16X-family without additional components. With every falling edge of ALE-line the MuPP latches the bus data on the 8 data lines DIOO ... DIO7 and stores it as address information. CSQ combined with RDQ or WRQ starts the data transfer cycle via the parallel 1sC-Interface. The data on DIOO ... DIO7 are valid on the rising edge of WRQ/RDQ (if CSQ is low). Depending on the previously latched address information, these data have a different meaning; e.g. the 8 bit of a command/data byte is preceeded by the address 00000001 or the subscriber/slot address for a subsequent data byte of a e.g. SOP-, TOP-, or COPI-command has the address information 00000000 (see table 4). A data transfer cycle to address 00000000 and 11111111 is already finished after the transfer of the first data byte; transfer cycles to addresses 00000001 and 00000010 consists of more transfers, depending on the length information in the first byte. As soon as the data transfer cycle via the \\1C-Interface has been completed, control information via the IOM-2 monitor channel will be accepted again (synchronized with the next FSC), until the next data transfer cycle starts with CSQ and RDQ/WRQ. cq =~ LJ LLL LT

10 OO — Ss OH

ADR DATA ADR_ DATA ADR DATA Figure 20 Example for a Read Access, with One Data Byte Transferred via DIO Semiconductor Group 39 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Interfaces cao SCL CL OL LT a ee ee os ee ADR DATA ADR DATA ADR DATA ADR DATA Figure 21 Example for a Write Access, With One Data Byte Transferred Table 4 Possible Address Information to Identify the Following Data Nibbles Address Command 00000000 address 00000001 data 00000010 status wee reserved 11111111 reset 1C Interface Data transfer to and from the MuSLIC is asynchron and the data will be transferred in bytes. Basically there is no difference to the IOM-2 commands, accept those which requires a slot specific address information. Semiconductor Group 40 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Interfaces

3.3 MuPP/QAP Interface

The MuPP/QAP-Interface, the link between the MuPP and the QAP, is a serial interface based on the 6 signals AFSC (analog frame sync), ADCL (analog data clock), ADU1/ADU2 (analog data upstream) and ADD1/ADD2 (analog data downstream). ADU1 and ADD1 are common to the first group of 8 time slots (channels) and ADU2 and ADD2 to the second 8 time slots (channels). AFSC and ADCL are common to both groups of time slots (timing diagram see chapter 7.2.6). 500 us (2 kHz) a | AFSC — SE SSSSSSSSSSSSSSSSSSSSSSSSSSsS]F ADDUADUL PEEL Po (Slot group 1) u fo — au SS ADD2/ADU2 ppp ee (Slot group 2) of — aE fcordscorf i —eonifrong a =S (EEL AC Woive, day PPT __ DG Commo 61 ns (16.384MHz) MuPP/QAP Interface: Frame, Bit Structure Figure 22 MuPP/QAP Interface: Frame, Bit Structure Semiconductor Group 41 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Interfaces

3.4 QAP/AHV-SLIC Interface

Output Voltage AC (ACP, ACN) The output voltage at the pins ACP and ACN represents the AC-information together with Teletax info at the receive path. The AC-information is received via the MuPP/QAP-Interface in the ADD channel. The 64-kHz Bitstream is converted to analog, passes a programmable gain stage of 0 / —6 dB and is buffered to drive a load of R, > 15 kQ and C_ < 10 pF, which is the input impedance of the AHV-SLIC. Output Voltage DC (DCP, DCN) The output voltage at the pins DCP and DCN represents the DC-information together with the Ring Burst at the receive path. The DC-information is received via the MuPP/QAP-Interface in the ADD channel. The 2-kHz Bitstream is converted to analog and buffered to drive an external smoothing capacitor of 33 nF. The pins are directly connected to the AHV-SLIC. Transversal Current Sense AC - Input (ITAC) The pin ITAC is the input voltage pin for the AC transversal current information from the AHV-SLIC in the transmit path. AC/DC separation is done by an external highpass filter (ext. capacitor = 470 nF). The input resistance is larger than 20 kQ. Current/voltage conversion is done via an external resistor of 1.5 kQ (same for pin IT). The signal passes a programmable gain stage 0 or 6 dB, is converted to digital and sent to the PEB 31665 via the MuPP/QAP-Interface in the ADU channel (64-kHz Bitstream). Transversal Current Sense DC - Input (IT) The pin IT is the input voltage pin for the DC transversal current information from the AHV-SLIC in the transmit path. The input resistance is larger than 500 kQ. Current/voltage conversion is done via an external resistor of 1.5 kQ (same for pin ITAC). The voltage at Pin IT is lowpass filtered and converted to digital. The bitstream (2 kHz) is sent to the PEB 31665 via the MuPP/QAP- Interface for further signal processing. Longitudinal Current Sense - Input (IL) The scaled longitudinal current information transferred from the AHV-SLIC - the current/voltage conversion is done by an external resistor of 1.5 kQ - is converted into digital and sent to the PEB 31665 via the MuPP/QAP-Interface in the ADU channel. In the PEB 31665 the IL-information is lowpass filtered (time programmable using DUPGNK-counter) and reported via the Data Upstream C/I-channel (CIDU-3) of the |OM-2 interface if the measured value exceeds a programmed limit. In Power Down, the GNK-bit is set to “O” and the setting of the Interrupt bit (CIDU-3) caused by GNK is prohibited. Semiconductor Group 42 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Interfaces Ternary Interface (C1, C2) In order to set the AHV-SLIC to the different operating modes, the information of the board-controller is passed through from the IOM-2-channel via the MuPP/ QAP- Interface to the ternary AHV-SLIC-Interface pins C1 and C2. Table 5 HIR PNDH~ - Power Down High Impedance PDNR~ - Power Down Resistive ACT - Active Mode ACT2 - Active Mode 2 (power save for SLIC, for future use) ACT3 - Active Mode 3 (power save for SLIC, for future use) BB - Boosted Battery HIR - Ring wire set to high impedance HIT - Tip wire set to high impedance HIRT - Ring and Tip wires set to high impedance For signalling “Over temperature” the AHV-SLIC drains a current (IOT) from pin C1. This current is sensed by the PEB 3465 and transferred in the ADU channel to the PEB 31665. The PEB 31665 sends the overtemperature message via the C/I-channel (CIDU-2: SLCX and TCRO-5) of the IOM-2 Interface. This is possible in any operating states of the AHV-Interface except for Power Down. Semiconductor Group 43 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Programming the MuSLIC

4 Programming the MuSLIC

With the appropriate commands, the MuSLIC can be programmed and verified very flexible via the |OM-2 Interface Monitor channel, and the Microcontroller Interface respectively. Transfer via the |OM®-2 Interface Data transfer to the MuSLIC starts with a MuSLIC-specific address byte (81,,). With the second byte one of 5 different types of commands (SOP, TOP, XOP, COP or COPI) is selected. Due to the extended MuSLIC feature control facilities these commands contain additional information (e.g. number of subsequent bytes) for programming (write) and verifying (read) the MuSLIC status. A write command is followed by up to 8 bytes of data. The MuSLIC responds to a read command with its IOM-2 specific address and the requested information, that is up to 15 bytes of data. Attention: Each byte of the monitor channel has to be transferred twice at least according to the IOM-2 Monitor handshake procedure. (For more information on IOM-2 specific Monitor Channel Data Structure see chapter 3.1 and chapter 10). Transfer via the Microcontroller Interface Data transfer to and from the MuSLIC is asynchron and the data will be transferred in bytes. Basically there is no difference to the IOM-2 commands. (For more information, about the LC Interface see chapter 3.2). 41 Types of Monitor / .C Interface Bytes The 8-bit Monitor / uC Interface bytes have to be interpreted as either commands or status information stored in Configuration Registers or the Coefficient RAMs. There are 5 different types of MuSLIC commands which are selected by bit 4 and 5 (partly bit 2 and 3) as shown below. SOP STATUS OPERATION: MUSLIC status setting/monitoring Bit 7 6 5 4 3 2 1 0 [6 | mw | o | 4 | atm | tset2| tsett | tseto XOP EXTENDED OPERATION: General settings Bit 7 6 5 4 3 2 1 0 Semiconductor Group 44 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Programming the MuSLIC TOP TRANSFER OPERATION: Read Certain Status / Options only Bit 7 6 5 4 3 2 1 0 COP COEFFICIENT OPERATION: Filter coefficient setting/monitoring Bit 7 6 5 4 3 2 1 0 COPI COEFFICIENT OPERATION INITIALIZE: Coefficient set assignment Bit 7 6 5 4 3 2 1 0 Table 6 Storage of Programming Information 6 status configuration registers: SCRO, ... SCR5 accessed by SOP command (for each channel) 2 test registers: STCRO, STCR1 accessed by SOP command (for each channel) 9 extended configuration registers: XRO ... XR8 accessed by XOP command 18 extended test registers: XTRO ... XTR17 accessed by XOP command

2 Transfer configuration registers: TCRO, TCR1 accessed by TOP command

(for each channel) AC- and DC-Coefficient RAMs: CRAMs accessed by COP command 2 coefficient set assignment registers: | CARO, CAR1 accessed by COPI command (for each channel) Semiconductor Group 45 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Programming the MuSLIC Overview of commands and registers via the IOM-2/uC Interface: SOP Command Bit 7 6 5 4 3 2 1 0 SOP for RW 1 ATR | LSEL2 | LSEL1 | LSELO SCR/STCR SOP Configuration Registers Bit 7 6 5 4 3 2 1 0 SCRI TTXNO NOSL | SOREV | ACTS aiozp | aici | SCR4 LOW Byte of DC-Offset Compensation SCR5 HIGH Byte of DC-Offset Compensation STCRI Rsvs | RSv4 | RSV3 Rsvi | RSvo | RSvU1 | RSVUO XOP Command Bit 7 6 5 4 3 2 1 0 XOP for Rw 1 ATR | LSEL2 | LSEL1 | LSELO XR/XTR Semiconductor Group 46 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Programming the MuSLIC XOP Configuration Registers Bit 7 6 5 4 3 2 1 0) Semiconductor Group 47 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Programming the MuSLIC XOP Test Register Bit 7 6 5 4 3 2 1 0 Semiconductor Group 48 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Programming the MuSLIC TOP Command Bit 7 6 5 4 3 2 1 0 TOP Configuration Registers Bit 7 6 5 4 3 2 1 0 TCRI NMVB/2 | NMICON [NMTEMP] NMFAIL | NMMVA|NMLSUP | RLM1 COP Command Bit 7 6 5 4 3 2 1 0 [icraw | Aw [0] 0] 0 | 1 Woraw] wRav] sev copes | copes | cope2 | cope1 | CODEO COPI Command Bit 7 6 5 4 3 2 1 0 CAR Coefficient set Assignment Registers Bit 7 6 5 4 3 2 1 0 Semiconductor Group 49 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Programming the MuSLIC

4.1.1 SOP Command

To modify or evaluate the MuSLIC status, individually for each channel, the contents of up to 6 configuration registers SCRO, ... SCR5 may be transferred to or from the MuSLIC. This is done by a SOP Command (status operation command). With ATR = 1 and LSELO = 0/1 and LSEL1 = LSEL2 = 0 the registers STCRO, STCR1 can be set/read. Bit 7 6 5 4 3 2 1 0 [se [pw | © | + | atm | tse | cee | 1set0 | B Broadcast B=0 Only one channel (time slot) is programmed B=1 All channels (up to 16) are programmed with the same information RW Read/Write Information: Enables reading from the MuSLIC or writing information to the MuSLIC RW =0 Write to the MuSLIC RW =1 Read from the MuSLIC ATR Access Test Register ATR=0 SCRO ... SCR5 Registers are available ATR=1 STCRO, STCR1 Registers are read/writeable LSEL Length select information This field identifies the number of SOP Register ATR LSEL 2 LSEL 1 LSEL 0 0 0 0 0 SCRO 0 0 0 1 SCR1 0 0 1 0 SCR2 0 0 1 1 SCR3 0 1 0 0 SCR4 0 1 0 1 SCR5 0 1 1 1 SCRO to SCR5 1 0 0 0 STCRO 1 0 0 1 STCR1 Semiconductor Group 50 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Programming the MuSLIC SCRO Configuration Register 0 Configuration register SCRO defines the basic feeding modes of the MuSLIC and enables/disables test features: Bit 7 6 5 4 3 2 1 0 [Pounn [ wee | us | ere | erat | eNO | ENTE | COR | Reset value: 00,, POLNR _ Normal or Reverse Polarity (see chapter 5.4) POLNR=0 _ sets the MuSLIC to Normal Polarity feeding POLNR=1___ sets the MuSLIC to Reverse Polarity feeding N/BB MuSLIC is in normal or Boosted Battery mode (see chapter 5.4). N/BB =0 Normal feeding N/BB = 1 Changes ternary interface to AHV-SLIC which sets the AHV-SLIC to Boosted Battery mode LB Handling of Loop Back functions for testing PCM loops LB=0 normal function LB=1 the desired Loop Back function is enabled ETG2 Enables programmable Test Tone Generator 2 ETG2=0 Test Tone Generator 2 is disabled ETG2 =1 Test Tone Generator 2 is enabled ETG1 Enables programmable Test Tone Generator 1 ETG1 =0 Test Tone Generator 1 is disabled ETG1 =1 Test Tone Generator 1 is enabled ENO Enables Offset compensation ENO =0 no DC offset compensation ENO =1 DC offset compensation ENTE Enables Test ENTE =0 normal operation ENTE =1 enables the test selected by the test registers (see chapter 8) COR Cut Off Receive Path for test reasons (see chapter 8) COR = 0 Receive Path transmission is available COR = 1 Receive Path is disabled Semiconductor Group 51 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Programming the MuSLIC SCR1 Configuration Register 1 Configuration register SCR1 defines the meterpulse settings and the soft/hard reversal, linear mode and IO settings. Bit 7 6 5 4 3 2 1 0 [Two [Tx | Nost | sonev | acts | acT2 | aia | aot | Reset value: 00,, TTXNO Meterpulses are represented by teletax (TTX) with 12 or 16 kHz or with Reverse Polarity TTXNO=0 ~~ Meterpulses are represented with 12 kHz or 16 kHz TTXNO = 1 Meterpulses are represented with Reverse Polarity TTX12 Teletax-signal with 12 kHz or 16 kHz TTX12 =0 16 kHz teletax-signal TTX12 =1 12 kHz teletax-signal NOSL No slope: means that the ramping of teletax (TTX) signal is switched off NOSL = 0 Slope of TTX-Signal is smooth NOSL = 1 Hard switch of TTX-Signal SOREV _ Soft Reversal Meterpulses SOREV =0 hard reversal SOREV=1 _ soft reversal ACT3 Active Mode with power save status of HV-SLIC (for future use) ACT3 = 0 normal mode ACT3 = 1 C1, C2 indicates the power save mode for the HV-SLIC ACT2 Active Mode with power save status of HV-SLIC (for future use) ACT2 =0 normal mode ACT2 = 1 C1, C2 indicates the power save mode for the HV-SLIC qio1D Direction for programmable IO - Pin of the QAP 101 QIO1D =0 sets the pin 101 as an input QIO1D = 1 sets the pin 101 as an output qlo2D Direction for programmable IO - Pin of the QAP 102 QIO2D = 0 sets the pin 102 as an input QlO2D = 1 sets the pin 102 as an output Semiconductor Group 52 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Programming the MuSLIC SCR2 Configuration Register 2 Configuration register SCR2 is the Mask register. Each bit of TCRO (Signalling register) can be masked (except the RES bit); that means changes of such a 'masked bit' are not causing a change of the SLCX - bit (Data Upstream C/I-channel byte). Bit 7 6 5 4 3 2 1 0 (vezw | iconm | Tewem | Faum | wvam | tsupm| i | 1 | Reset value: FF,, VB/2M Mask bit for half battery information VB/2M = 0 each change of the VB/2 bit leads to an interrupt (SLCX-bit) VB/2M = 1 changes of VB/2 bit are neglected ICONM Mask bit for constant current information ICONM=0 _ eachchange of the ICON bit leads to an interrupt (SLCX-bit) ICONM=1 changes of ICON bit are neglected TEMPN _ Mask bit for over temperature information TEMPM =0 _ eachchange of the TEMP bit leads to an interrupt (SLCX-bit) TEMPM=1__ changes of TEMP bit are neglected FAILM Mask bit for clock fail information FAILM = 0 each change of the FAIL bit leads to an interrupt (SLCX-bit) FAILM = 1 changes of FAIL bit are neglected MVAM Mask bit for internal measurement results MVAM = 0 each change of the MVA bit leads to an interrupt (SLCX-bit) MVAM = 1 changes of the MVA bit are neglected LSUPM Mask bit for line supervision LSUPM=0 _— each change of the LSUP bit leads to an interrupt (SLCX-bit) LSUPM=1 changes of the LSUP bit are neglected Information about changing half battery- and constant current- information will be neglected on both of the Power Down and the Ringing state. Semiconductor Group 53 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Programming the MuSLIC SCR3 Configuration Register Bit 7 6 5 4 3 2 1 0 [acsos| uN | taw | coms] 0 | 0 | 0 | 0 | Reset value: 00, AG6DB Fixed gain in the transmit path. AG6DB=0 OdBgain AG6DB = 1 +6 dB gain LIN Linear mode selection (16 bit linear information in voice channel A (upper byte) and B (lower byte) LIN=0 PCM-mode is selected LIN =1 linear mode is selected LAW PCM-law selection LAW =0 A-Law is selected LAW = 1 u-Law is selected (11255 PCM) COR8 Cut off receive (voice only) COR8 = 0 normal operation COR8 = 1 cut off receive is enabled SCR4 and SCR5 Configuration Register These two registers content the DC offset bytes. They can be used one by one. Activation is controlled by the ENO bit (SCRO-2) SCR4 Bit 7 6 5 4 3 2 1 0 Reset value: 00, SCR5 Bit 7 6 5 4 3 2 1 0 Reset value: 00, Semiconductor Group 54 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Programming the MuSLIC STCRO Test Configuration Register 0 The Test Configuration register STCRO is used for fuse operation and test only. Bit 7 6 5 4 3 2 1 0 [Fuses | Fuse2 | Fuser | Fuseo[ oo [| o | oo | o | Reset value: 00,, FUSEO to FUSE3 Information for fuse operation STCR1 Test Configuration Register 1 The Test Configuration register STCR1 is used for reserved operations of the PEB 3465 (QAP). Bit 7 6 5 4 3 2 1 0 Reset value: 00, RSVO to RSV5 from PEB 31665 to PEB 3465 RSVUO to RSVU1 from PEB 3465 to PEB 31665 Semiconductor Group 55 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Programming the MuSLIC

4.1.2 XOP Command

To modify or evaluate test configurations, to select special functions, to control the coefficient RAMs, to get information for fusing and ECIC and other common functions up to 15 Bytes maybe transferred to or from the MuSLIC, using the XOP Command (extended operation command). Bit 7 6 5 4 3 2 1 0 [o | ww | 4 | 0 | arm | toe | coer | tseto | RW Read/Write Information: Enables reading from the MuSLIC or writing information to the MuSLIC. RW =0 Write to the MuSLIC. RW =1 Read from the MuSLIC LSEL Length select information. This field identifies the subsequent data bytes. ATR LSEL2 LSEL1 LSELO 0 0 0 0 XRO 0 0 0 1 XR1 0 0 1 0 XR2 0 0 1 1 AC-RAM + DC-RAM Checksum 0 1 0 0 AC-RAM Checksum 0 1 0 1 DC-RAM Checksum 0 1 1 0 ECIC1 (0 to 14) 0 1 1 1 ECIC2 (15 to 29) 1 0 0 0 XTRO 1 0 0 1 XTR1 and XTR2 1 0 1 0 XTRO to XTR8 1 0 1 1 Fuse register 0 to Fuse register 1 1 1 0 0 Blocktest 1 to Blocktest 3 1 1 0 1 XTR14 to XTR17 1 1 1 0 RESERVED 1 1 1 1 RESERVED Semiconductor Group 56 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Programming the MuSLIC XRO Extended Operation Register 0 Extended Operation Register 0 defines the four |O-pins of the MuPP. Bit 7 6 5 4 3 2 1 0 Reset value: 00,, MIOiD Direction for programmable IO - Pins of the MuPP 101 to 104 MIOID = 0 sets the pin IOi as an input MIOID = 1 sets the pin IOi as an output MIOi Value of programmable IO - Pins of the MuPP 101 to 104 MIOi = 0 sets the pin IOi to LOW or if itis read it is LOW MIOi = 1 sets the pin IOi to HIGH or if it is read it is HIGH If the bit REXTEN (XR2-7) is set to 1 (Unbalanced Ringing) the MIO1 pin is switched to the ring pulse control function. Thus a zero-crossing signal connected to the MIO1 (combined with the Ringing Mode, burst on/off) generates a correct switching signal for the ringer relay sent on QIO1 of the selected subscriber line (see chapter 4.2 and chapter 5.5). If the bit EX-MCLK (XR2-2) and TST1 pin (No.26) are set to 1 and the MIO2 pin is set as an input the MuPP is ready for external clocking (32 MHz) (the internal PLL is shut down). If the TST1 pin (No.26) and the bit EX-MCLK (XR-2) is set to 1 and the MIO2 pin is set as an output the 32 MHz clock (output of the internal PLL) is on the MIO2 pin. Semiconductor Group 57 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Programming the MuSLIC XR1 Extended Operation Register 1 Extended Operation Register 1 defines the Data Upstream Persistency Counters. Bit 7 6 5 4 3 2 1 0 Reset value: 5A, DUPGNK To restrict the rate of upstream C/I-bit changes, deglitching (persistence checking) of the status information from the MuSLIC may be applied. New status information will be transmitted upstream, after it has been stable for N milliseconds. N is binary programmable in the range of 4 to 60 ms in steps of 4 ms, with DUPGNK = 0, the deglitching is disabled. Reset value is 20 ms. The HOOK bit (for external indication) and the GNK bit are influenced. (Detailed info see chapter 4.2, and figure 23.) DUP To restrict the rate of upstream C/I-bit changes, deglitching (persistence checking) of the status information from the MuSLIC may be applied. New status information will be transmitted upstream, after it has been stable for N milliseconds. N is binary programmable in the range of 1 to 15 ms in steps of 1 ms; with DUP = 0h the deglitching is disabled. Reset value is 10 ms. The HOOK, SLCX and the Ql1-bits are influenced (different counters but same programming). (Detailed info see chapter 4.2, and figure 23.) Semiconductor Group 58 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Programming the MuSLIC XR2 Extended Operation Register 2 Extended Operation Register 2 defines basic operations for all channels. Bit 7 6 5 4 3 2 1 0 [Rexten 0 [0 | Fixc | wn [exwok] 0 | 0 | Reset value: 10, REXTEN External Ringing Mode Enabled (see chapter 5.5) REXTEN = 0 use internal ringing mode REXTEN =1 use external ringing mode FIXC. The MuSLIC uses either fixed coefficients or the programmed ones. FIXC =0 programmed coefficients used FIXC =1 fixed coefficients used IDR Initializes Data RAM IDR =0 normal operation is selected IDR =1 content of Data RAM is set to 0 (for test purposes) EX-MCLK Possibility to provide the MuSLIC with an external clock (see XRO) EX-MCLK = 0 normal operation is selected EX-MCLK = 1 internal PLL is shut down or internal clock is connected to the pin MIO2, respectively (see XRO) Semiconductor Group 59 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Programming the MuSLIC XR3 TO XR6 Extended Operation Registers 3 to 6 XR3 to XR6 are the checksums of all the Coefficient bytes written into the Coefficient RAM (CRAM) of the MuPP by the COP-Command. Reading these bytes starts the sum generation. There are two identical blocks of CRAMs (time slot 0 to 7 and 8 to 15). Each reading alternates the block access. XR3 Bit 7 6 5 4 3 2 1 0 XR4 Bit 7 6 5 4 3 2 1 0 XR5 Bit 7 6 5 4 3 2 1 0 XR6 Bit 7 6 5 4 3 2 1 0 (Algorithm of defining the checksum: x'® + x'° + x” + x + 1) (With that algorithm you can reach a fault coverage of: 1-27'5) Semiconductor Group 60 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Programming the MuSLIC Sum generation is done in the following manner (see chapter 4.1.4) AC-CRAM-Checksum The sequence of the coefficients is: 13 , set 13 » sett Tat Sear TGCSF IM1 IM2 IM3 TH1 TH2 TH3 set FRX FRR AX AR TSTAC ACCSF IM1 seti ACCSF IM1 . set7 ACCSF Semiconductor Group 61 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Programming the MuSLIC DC-RAM-Checksum The sequence of the coefficients is: TSTTX TTX AGC DC rune setO HOOKL RAMP. TSTDC DCCSF TSTTX . set! DCCSF TSTTX set2 DCCSE TSTTX set3 DCCSF Using the “checksum fill” Bytes (TGCSF, ACCSF, DCCSF) it is possible to create a fixed set-checksum independent of changed coefficients. Semiconductor Group 62 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Programming the MuSLIC XR7 and XR8 Extended Operation Register 7 to 8 Each of these two registers feasibles to read 15 bytes of design/status information generated by an external ASIC. More details about the extended IOM-2 Channel Identification see chapter 10. XR7 Bit 7 6 5 4 3 2 1 0 XR8 Bit 7 6 5 4 3 2 1 0 XR7 and XR8 shows the data stream of the input pin IDO. If the input pins ID1, ID2 and ID3 = 1, IDO works as a serial input controlled by FSC and DCL (see chapter 10). Reading XR7 or XR8 15 bytes each will be transferred from IDO to IOM-2 Interface Monitor channel. XTRO Extended Operation Test Register 0 Extended Operation Test Register XTRO defines testing features. Bit 7 6 5 4 3 2 1 0 [wr [ wk [etm | SoFToN | opimem | oLP0s | oLPS | DISPOF! | Reset value: 00, HIT for AHV-SLIC test functions HIT =0 normal operation HIT = 1 changes HV-interface (C1,C2) which set the TIP wire to high impedance HIR for AHV-SLIC test functions HIR=0 normal operation HIR= 1 changes HV-interface (C1,C2) which set the RING wire to high impedance Semiconductor Group 63 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Programming the MuSLIC ELM Enable level meter ELM =0 normal operation if LM2PCM = 1 the input to the Levelmeter is switched to PCM Voice-Channel ELM = 1 level meter function is enabled if LM2PCM = 1 the output of the Levelmeter is switched to PCM Voice-Channel SOFTON SW-fuses are activated in the PEB 3465 SOFTON=0 HW-fuses are activated SOFTON=1 SW-fuses are activated OPIM8M Open fast digital Impedance Matching Loop (IM8M) OPIM8M = 0 normal operation OPIM8M = 1 opens fast digital IM-Loop (Himgm = 0) DLP03 Disable LP03-lowpass DLPO3 = 0 normal operation DLPO3 = 1 disables programmable lowpass (H,p93 = 1) DLP5 Disable LP5-lowpass DLP5 =0 normal operation DLP5 = 1 disables programmable lowpass (H,ps = 1) DISPOFI Disable Postfilter (DC path) DISPOFI =0 normal operation DISPOFI=1 disables postfilter Semiconductor Group 64 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Programming the MuSLIC XTR1 Extended Operation Test Register 1 XTR1 controls the level meter functions Bit 7 6 5 4 3 2 1 0 Reset value: 00,, CAL Enable level meter result register CAL = 0 normal operation (offset register - SCR4/SCR5 - is read) CAL = 1 levelmeter result register is read LMSEL selects Levelmeter and Thresholdpairs LMSEL1 LMSELO 0 0 DC-Levelmeter Thresholdpair 0 0 1 DC-Levelmeter Thresholdpair 1 1 0 AC-Levelmeter 1 1 TTX-Levelmeter LMNOTCH Bandpass or Notchfilter Function for Levelmetering AC LMNOTCH = 0 Bandpass Function LMNOTCH = 1 Notchfilter Function LMBP Activates the Bandpass or Notchfilter in the AC Transmit Path LMBP = 0 normal operation LMBP = 1 Bandpass/Notchfilter enabled LM2PCM Switches the selected Levelmeter Signal to the PCM Voice-Channel LM2PCM = 0 normal operation LM2PCM = 1 switches the selected Levelmetersignal to the PCM Voice-Channel PCM2DC switches the Receive PCM Voice-Channel to DC-Output PCM2DC = 0 normal operation PCM2DC = 1 switches the Receive PCM Voice-Channel to DC-Output ITIME Integration time of AC and TTX Levelmeter ITIME = 0 16 ms Integrationtime ITIME = 1 256 ms Integrationtime Semiconductor Group 65 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Programming the MuSLIC XTR2 Extended Operation Test Register 2 Extended Operation Test Register XTR2 defines testing features (see chapter 8). Bit 7 6 5 4 3 2 1 0 [ING-on| pDce | DCADI6 | ERAWP | ERECT [aC-ADPD[AC-DACPO) AFE-OFF Reset value: 00,, RING-ON Interrupt DC-characteristic and enables the Ringing Offset RING-ON = 0 normal operation RING-ON = 1 Interrupts DC-loop (HDCC = 0) and enables the Ringing Offset DDCC Disable DC-characteristic DDCC =0 normal operation DDCC = 1 disables DC-loop (HDCC = 1) DCAD16 DC gain of 16 in AD direction DCAD16 = 0 normal operation DCAD16 = 1 gain of 16 ERAMP Enable Ramping generator ERAMP =0 ramping generator off ERAMP = 1 ramping generator on ERECT Enable rectifier in DC-levelmeter ERECT =0 normal operation (HRECT = 1) ERECT = 1 enables rectifier AC-ADCPD ADC is set to power down (transmit path is opened) AC-ADCPD =0 normal operation AC-ADCPD = 1 ___ transmit path is inactive AC-DACPD DAC is set to power down (receive path is opened) AC-DACPD =0 normal operation AC-DACPD =1 ___ receive path is inactive AFE-OFF Analog front end is activated or deactivated AFE-OFF = 0 normal operation AFE-OFF = 1 the analog front end is deactivated Semiconductor Group 66 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Programming the MuSLIC XTR3 Extended Operation Test Register 3 Extended Operation Test Register XTR3 defines the basic MuSLIC settings which enable / disable the programmable digital filters. Bit 7 6 5 4 3 2 1 0 [pnp-x | pnpR | oH | FRx | FAR | ax | an | om | Reset value: 00,, DHP-X Disable Transmit Highpass for test reasons DHP-X = 0 Transmit Highpass Filter is enabled DHP-X = 1 Transmit Highpass Filter is disabled DHP-R Disable Receive Highpass for test reasons DHP-R = 0 Receive Highpass Filter is enabled DHP-R = 1 Receive Highpass Filter is disabled TH Set Transhybrid Balancing Filter - together with the bit FIXC (XR2-4). For FIXC = 1: the TH-Filter is set to Hy, = for Zgap; For FIXC = 0: TH=0 TH-filter is disabled TH=1 TH-filter is enabled (use programmed values) FRX Enable FRX- (Frequency Response Transmit) Filter For FIXC = 0: FRX =0 FRX-filter is disabled (Hea = 1) FRX =1 FRX-filter is enabled (use programmed values) FRR Enable FRR- (Frequency Response Receive) Filter For FIXC = 0: FRR =0 FRR-filter is disabled (Hap = 1) FRR =1 FRR-filter is enabled (use programmed values) AX Set AX- (Amplification/Attenuation Transmit) Filter For FIXC = 0: AX =0 AX-filter is set to default value (Hy, = 10 dB) AX=1 AX-filter is enabled (use programmed values) AR Set AR- (Amplification/Attenuation Receive) Filter For FIXC = 0: AR =0 AR-filter is set to default value (Hap = —15.11 dB) AR=1 AR-filter is enabled (use programmed values) IM Activates or deactivates the 64 kHz filter IM=0 64 kHz filter is deactivated (Hiy = 0) IM=1 64 kHz filter is activated Semiconductor Group 67 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Programming the MuSLIC XTR4 Extended Operation Test Register 4 Extended Operation Test Register XTR4 defines testing features. Bit 7 6 5 4 3 2 1 0 Reset value: 00,, DLB-8M AC digital loop: 8 MHz in/output is short cut DLB-8M = 0 normal operation DLB-8M = 1 8 MHz in/output is short cut DLB-64K AC digital loop: 64 kHz in/output is short cut DLB-64K = 0 normal operation DLB-64K = 1 64 kHz in/output is short cut DLB-32K AC digital loop: 32 kHz in/output is short cut DLB-32K = 0 normal operation DLB-32K = 1 32 kHz in/output is short cut DLB-PCM AC digital loop: PCM in/output is short cut DLB-PCM =0 normal operation DLB-PCM = 1 PCM in/output is short cut ALB-8M AC analog loop: 8 MHz in/output is short cut ALB-8M = 0 normal operation ALB-8M = 1 8 MHz short cut ALB-64K AC analog loop: 64 kHz in/output is short cut ALB-64K = 0 normal operation ALB-64K = 1 64 kHz in/output is short cut ALB-8K — AC analog and digital loops: ALB-8K = 0 normal operation ALB-8K = 1 and ALB-8M=0 8 kHz loop in the AC DSP (AC digital loop) ALB-8K = 1 and ALB-8M=1 _ Pre-/Postfilter out/input is short cut (AC analog loop) DCHOLD Holds the current DC-Output DCHOLD = 0 normal operation DCHOLD = 1 DC-Output is held Semiconductor Group 68 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Programming the MuSLIC XTR5 Extended Operation Test Register 5 XTR85 defines testing functions Bit 7 6 5 4 3 2 1 0 Reset value: 00,, DC-DLB DC digital loop: 1 MHz in/output is short cut DC-DLB = 0 normal operation DC-DLB = 1 1 MHz in/output is short cut DC-ALB DC analog loop: DC-ALB = 0 normal operation DC-ALB = 1 short cut of in/output of DC-ADC and DC-DAC DC-ALBIT DC analog loop: IT is switched to DCP/DCN DC_ALBIT =0 normal operation DC_ALBIT = 1 IT is switched to DCP/DCN DC-ALBIL DC analog loop: IL is switched to DCP/DCN DC_ALBIL =0 normal operation DC_ALBIL = 1 IL is switched to DCP/DCN DC-ALBV DC analog loop: VA, VB, VBIM, VDDIM is switched to DCP/DCN DC_ALBV = 0 normal operation DC_ALBV = 1 VA, VB, VBIM, VDDIM is switched to DCP/DCN DCLMU Selects the signal switched to the DC-Levelmeter DCLMU2 DCLMU1 DCLMUO 0 0 0 IT 0 1 0 IL 1 0 0 VA 1 0 1 VB 1 1 0 VBIM 1 1 1 VDDIM Semiconductor Group 69 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Programming the MuSLIC XTR6 Extended Operation Test Register 6 XTR6 defines testing functions Bit 7 6 5 4 3 2 1 0 [tra [orm | noaae [iuirwux| corse | onrorr | axGo | ARGO | Reset value: 00,, TTXL Enables current measurement for TTX TTXL=0 normal operation TTXL = 1 and IM = 1 and OPIM8M=1 enables TTX current measurement DTTXL Analog testloop: input/output is shortcut DTTXL =0 normal operation DTTXL =1 input/output is shortcut t NOAGC _ disable automatic gain control for TTX NOAGC =0 normal operation NOAGC =1 disable automatic gain control ILITMUX IL changes to IT and vice versa ILITMUX = 0 normal operation ILITMUX=1 IL changes to IT and vice versa COT16 cut off transmit path COT16=0 normal operation COT16 =1 cut off transmit path DITOFF Disables the dither for noiseshapers DITOFF =0 normal operation DITOFF=1 Dither disabled AXGO 0 dB Gain for Transmit Path AXGO =0 normal operation AXGO = 1 0 dB Gain for Transmit Path ARGO 0 dB Gain for Receive Path ARGO = 0 normal operation ARGO = 1 0 dB Gain for Receive Path Semiconductor Group 70 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Programming the MuSLIC XTR7 Extended Operation Test Register 7 XTR7 informs how many PEB 3465 are connected to the PEB 31665 Bit 7 6 5 4 3 2 1 0 [averos | overes [aneraa[averar| 0 | 0 | ° | 0 | Reset value: 00,, QDETQ4 _ informs about PEB 3465 connection QDETQi = 0 there is no PEB 3465 connected to the i-th interface QDETQi = 1 there is a PEB 3465 connected to the i-th interface Note: This information is available after the first AFSC-pulse. Semiconductor Group 71 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Programming the MuSLIC XTR8 Extended Operation Test Register 8 XTR8 defines testing functions Bit 7 6 5 4 3 2 1 0 [FeaP-rins|roar-rine|raar-rini[raaPrino] © © [| ENASY | Reset value: 00,, TQAP-FIR3 Disables Noiseshaping Function for Channel 9, 11, 13, 15 TQAP-FIR3 =0 normal operation TQAP-FIR3 =1 Noiseshaping Function is disabled TQAP-FIR2 Disables Noiseshaping Function for Channel 8, 10, 12, 14 TQAP-FIR2 =0 normal operation TQAP-FIR2=1 Noiseshaping Function is disabled TQAP-FIR1 Disables Noiseshaping Function for Channel 1, 3, 5, 7 TQAP-FIR1 =0 normal operation TQAP-FIR1=1 Noiseshaping Function is disabled TQAP-FIRO Disables Noiseshaping Function for Channel 0, 2, 4, 6 TQAP-FIRO =0 normal operation TQAP-FIRO=1 Noiseshaping Function is disabled ENRSV Enables Reserved Registers (STCR1, XTR14 to XTR17) ENRSV = 0 normal operation ENRSV = 1 reserved registers are enabled XTR9 to XTR10 Extended Operation Test Register 9 and 10 These bytes are used for the fuse operation of the PEB 3465. XTRO Bit 7 6 5 4 3 2 1 0 Reset value: 00, Semiconductor Group 72 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Programming the MuSLIC XTR10 Bit 7 6 5 4 3 2 1 0 Reset value: 00, XTR11 to XTR13 Extended Operation Test Register 11 to 13 These 3 bytes show the result of the test of internal function blocks. XTR11 Bit 7 6 5 4 3 2 1 0 Reset value: 00,, XTR12 Bit 7 6 5 4 3 2 1 0 Reset value: 00,, XTR13 Bit 7 6 5 4 3 2 1 0 Reset value: 00, Note: Write XTR11 with bit 0 = 1 starts the blocktests. There are several types of tests. Selection is done by the bits 1 to 7 of XTR11 (see chapter 8). XTR14 to XTR16 Extended Operation Test Register 14 to 16 XTR14 to XTR16 are reserved for transfer of information from the PEB 31665 to the PEB 3465. Reset value: 00, Semiconductor Group 73 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Programming the MuSLIC XTR17 Extended Operation Test Register 17 XTR17 is reserved for transfer of information from the PEB 3465 to the PEB 31665. Reset value: 00,,

4.1.3 TOP Command

With the TOP Command the TCRO and TCR1 registers can be read. Each channel has its own registers addressed by the time slot or by address Bit 7 6 5 4 3 2 1 0 Lo fe ft fot foo Jo J tsetr | tseto | R Read Information: Enables reading from the MuSLIC. R=0 No operation R=1 Read from MuSLIC LSEL Length select information This field identifies the number of the TCR Register and the handling of interrupts too. LSEL 1 LSEL 0 0 0 TCRO (Reset of the interrupt) 0 1 TCR1 (Not masked interrupts are not affected) 1 1 TCRO and TCR1 (Reset of the interrupt) Semiconductor Group 74 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Programming the MuSLIC TCRO Configuration Register 0 TCRO is the Signalling register. It indicates status information of each channel. If there is any change of one or more bits it is indicated via the SCLX bit in the C/I-channel. Each bit, except the RES bit, can be masked by the SCR2 Register (see also figure 23). Bit 7 6 5 4 3 2 1 0 [vera [icon | tewe [rau [ wva | sup | res | 0 | Reset value: 02,, VB/2 Half battery voltage is detected interrupt masked in Power Denial and Ringing State VB/2 =0 line voltage smaller than half battery VB/2 =1 line voltage larger than half battery ICON Current limitation information interrupt masked in Power Denial and Ringing State ICON =0 Resistive Feeding ICON = 1 Constant Current Feeding TEMP Temperature alarm of the AHV-SLIC which is signalled through the HV-SLIC Interface (see chapter 3.4) TEMP = 0 normal temperature TEMP = 1 Temperature alarm from AHV-SLIC detected FAIL DCL or FSC Fail: Not the right count of clock cycles between two frame syncs FAIL =0 no clock fails are detected FAIL = 1 clock fails are detected The FAIL bit is not influenced by the DUP-counter (each failure is reported). MVA Internal measurement results shown in the TCR1-0 and TCR1-1 are valid or not valid (see chapter 8) MVA =0 the level metering results are not valid MVA = 1 the level metering results are valid LSUP Line Supervision (of broken line) LSUP =0 the transversal current is higher than the programmed level LSUP = 1 the transversal current is lower than the programmed level RES Reset status RES =0 no Reset has occurred RES =1 Reset has occurred via Reset-pin or via Power on Reset Semiconductor Group 75 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Programming the MuSLIC Any change of these bits (except the FAIL bit: only the positive going is reported) is signalled via the interrupt-bit (SLCX) in the C/I-DU-channel. There are two types of generating an interrupt: — Each toggling of a non-masked TCRO-bit combined with a DUP-counter — Toggling of the non-masked TEMP or MVA-bit and positive going FAIL bit (no filtering by the DUP-counter) The status information is stored in the TCRO-register and an interrupt is generated but only if there isn’t a not-handled interrupt. Reading the TCRO-register gives the frozen interrupt status, clears the interrupt and enables the signalling of a further interrupt but not until after at least two 8 kHz frames. Note: The HOOK and the GNK signalling are directly filtered by there own DUP(GNK)- counters and they are directly put into the C/l-DU-channel (see chapter 4.2). TCR1 Configuration Register 1 TCR1 indicates interrupt information and level meter results of one channel. Bit 7 6 5 4 3 2 1 0 Reset value: 00,, NMVB/2 to NMLSUP Not masked signalling information. (The meaning of each bit is the same as described above.) Reading this register won't affect any stored information. RLM1 and RLMO Result Level Metering RLM1 RLMO 0 0 below both levels x 1 above level 0 1 x above level 1 Semiconductor Group 76 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Programming the MuSLIC ve2 ICON TEMP FAIL MVA ——_LSUP Persistency not masked TCR1 NMVB/2 | NMICON | NMTEMP] NMFAIL | NMMVA | NMLSUP- signalling P| | tt ~ scr2 7 7 mask ve/2M |ICONM |TEMPM | FAILM | MVAM |LSUPM | tegister Ft | tl ~ register

102101 It HOOK GNK

Figure 23 Interrupt Logic (block structure) ‘) In Power Down and Ringing Mode changes of VB/2 and ICON are masked. 2) TCRO is locked if one of the signals changes and is enabled after reading. Each change of TCRO sets the interrupt bit SLCX to 1. Reading TCRO sets SLCX to 0 but not before two 8 kHz frames. A take over of the signal FAIL from TCR1 to TCRO cleares this signal in TCR1. 2) In Power Down Mode the persistency counter DUPGNK is used. Semiconductor Group 77 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Programming the MuSLIC

4.1.4 COP Command

With a COP Command coefficients for the programmable filters can be written to or read from the MuSLIC (write access is only allowed if FIXC = 1 or to an unused SET). (Filter optimizing to different applications is supported by the software package MuSLICOS.) The coefficients are gathered to 8 and 4 SETS respectively. So an optimum is reached between supplying each channel, handling and memory space. Figure 24 gives an overview of the Coefficient RAM structure. To assign a SET to a channel the COPI command is used. Bit 7 6 5 4 3 2 1 0 [ioraw [aw [© | © | © | 1 | WORANT | WCRANO Bit 7 6 5 4 3 2 1 0 [sere | sett | seve | coves | coves | cone? | covet | coved | ICRAM Initialize CRAM ICRAM = 0 Only one coefficient is programmed (destination is coded in the following byte) ICRAM = 1 the whole AC- or DC-CRAM is written with the information of the following byte RW Read/ Write RW =0 Subsequent data is written to the MuSLIC RW = 1 Read data from the MuSLIC WCRAM1 and__ Write to CRAM (only valid in combination with ICRAM=1) WCRAMO WCRAM1 WCRAMO 0 0 no write 0 1 AC-CRAM 1 0 DC-CRAM 1 1 AC-CRAM and DC-CRAM Semiconductor Group 78 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Programming the MuSLIC SET includes the number of coefficient set SET2 SET1 SETO 0 0 0 SETO 0 0 1 SET 1 0 1 0 SET 2 0 1 1 SET 3 1 0 0 SET 4 1 0 1 SET 5 1 1 0 SET6 1 1 1 SET7 SET Oto SET 7 for the 8 sets of AC-coefficients and the 8 sets of Tone Generator 1 and 2 SET Oto SET3 for the 4 sets of DC-coefficients Semiconductor Group 79 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Programming the MuSLIC CODE includes the number of following bytes and filter-addresses") CODE4 | CODES | CODE2 |CODE1 | CODEO 0 lo fo fo. — fo _—_—[ TH¥Fiter coefficients (part 1) _| (followed by 8 bytes of data) 0 fo fo fo if; | TH-Filter coefficients (part 2) _| (followed by 8 bytes of data) 0 lo fo ft fo TH Fitter coefficients (part 3) _| (followed by 8 bytes of data) 0 fo fo fa ft FRX+fiter coefficients (followed by 8 bytes of data) 0 fo fs fo fo FRR ‘filter coefficients (followed by 8 bytes of data) i) fo ft fot AX-filter coefficients (followed by 8 bytes of data) 0 lo ft ft fo [AR iter coefficients (followed by 8 bytes of data) 0 lo fs ft ft ret-iter coeticients (followed by 8 bytes of data) 0 [1 fo fo fo Taatiter coefficients (followed by 8 bytes of data) 0 1 fo fo ft | AC test coefficients (followed by 8 bytes of data) 0 [1 fo fa fo [tv-titer coefficients (part 3) _| (followed by 8 bytes of data) i) Ce CL | IM-filter coefficients (part 1) (followed by 8 bytes of data) 0 [7 ft fo fo IM-filter coefficients (part 2) (followed by 8 bytes of data) 0 [pfs fo ft | ta cS (checksum fitt) (followed by 8 bytes of data)

0 Ce Ce LC AC CSF (checksum fill) (followed by 8 bytes of data)

1 lo fo fo — fo [ TIX test coefficients (followed by 8 bytes of data) 1 fo fo fo if; | TTX coefficients (followed by 8 bytes of data)

1 CE Ce Ce Ce AGC coefficients (followed by 8 bytes of data)

1 fo fot ft LP iter coefficients (followed by 8 bytes of data) 1 lo fs fo fo Hook level coefficients (followed by 8 bytes of data) 1 fo fs fot DC test coefficients (followed by 8 bytes of data) 1 fo fs ft fo Ringing coefficients (followed by 8 bytes of data) 1 lo fs oft DC-characteristic coefficients _| (followed by 8 bytes of data) 1 1 Ramp generator, (followed by 8 bytes of data) Ringer delay coefficients 1 [) fo fo ft [DC SF (checksum fit (followed by 8 bytes of data) 1) For generating a correct checksum all not used bits must be set to 0. Semiconductor Group 80 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Programming the MuSLIC DC set 0 TSTTTX : TTX AGC Dc RING LPF HOOKL RAMP TSTDC AC set 0 IM FRX FRR AX AR TSTAC TG1 setO TG2 set 0 Figure 24 Overview of Sets of Coefficients Semiconductor Group 81 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Programming the MuSLIC

4.1.5 COPI Command

The COPI command allows to assign the sets of the Coefficient RAMs to a selected channel (given by the time slot or by address). Bit 7 6 5 4 3 2 1 0 ee B Broadcast B=0 Only one channel (time slot) is programmed B=1 All channels (up to 16) are programmed with the same information RW Read/ Write RW =0 Subsequent data is written to the MuSLIC RW =1 Set assignment is read LSEL Length select information. This field identifies the subsequent data bytes. LSEL1 LSELO 0 0 CARO 0 1 CAR1 1 1 CARO and CAR1 Semiconductor Group 82 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Programming the MuSLIC CARO Coefficient set Assignment Register 0 CARO indicates AC and DC coefficients set assignment. Bit 7 6 5 4 3 2 1 0 [wer [peo [ace [act [aco [0 [0 | HloaD | Reset value: 00,, Dc DC1 DCO 0 0 DC coefficient set 0 0 1 DC coefficient set 1 1 0 DC coefficient set 2 1 1 DC coefficient set 3 AC AC2 AC1 ACO 0 0 0 AC coefficient set 0 0 0 1 AC coefficient set 1 0 1 0 AC coefficient set 2 0 1 1 AC coefficient set 3 1 0 0 AC coefficient set 4 1 0 1 AC coefficient set 5 1 1 0 AC coefficient set 6 1 1 1 AC coefficient set 7 HLOAD Hook for Load HLOAD = 0 normal operation HLOAD = 1 load is activated (LP03 will be preset) Semiconductor Group 83 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Programming the MuSLIC CAR1 Coefficient set Assignment Register 1 CAR1 indicates Tone Generator coefficients set assignment. Bit 7 6 5 4 3 2 1 0 [_te1.2 | tera [| toro | te22 | taz1 | tozo | oo | 0 | Reset value: 00,, TG1 TG1.2 TG1.1 TG1.0 0 0 0 Tone Generator 1 set 0 0 0 1 Tone Generator 1 set 1 0 1 0 Tone Generator 1 set 2 0 1 1 Tone Generator 1 set 3 1 0 0 Tone Generator 1 set 4 1 0 1 Tone Generator 1 set 5 1 1 0 Tone Generator 1 set 6 1 1 1 Tone Generator 1 set 7 TG2 TG22 TG21 TG20 0 0 0 Tone Generator 2 set 0 0 0 1 Tone Generator 2 set 1 0 1 0 Tone Generator 2 set 2 0 1 1 Tone Generator 2 set 3 1 0 0 Tone Generator 2 set 4 1 0 1 Tone Generator 2 set 5 1 1 0 Tone Generator 2 set 6 1 1 1 Tone Generator 2 set 7 Semiconductor Group 84 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Programming the MuSLIC

4.2 IOM®-2 Interface Command / Indication Byte

The Command/Indication (C/I) channel is used to communicate real time status information and for fast controlling of the MuSLIC Data on the C/I channel are continuously transmitted in each frame until new data is sent. Data Downstream C/I - Channel Byte (receive) - CIDD This Byte is used for fast controlling of the MuSLIC. Each transfer to the MuSLIC has to last for at least 2 consecutive frames (FSC-cycles) so that it is accepted internally. Changes (spikes) of less than 2 FSC cycles are neglected. (Note that there is no address DD direction because there is only one MuPP.) Bit 7 6 5 4 3 2 MO, M1, M2 these bits define the actual status; see table below (for details see chapter 5) M2 ey | Description 0 0 0 Power-Down High Impedance (loop open, PDNH) 1 1 1 Power-Down Resistive (loop open, PDNR) 0 1 Active State 1 1 Active State with Meterpulses 1 0 Ground Start 0 1 Ringing State (ring pause) 1 1 Ringing State (ring burst on) Qo1 Value for the fixed Output Pin O1 of the QAP. QO1=0 The corresponding pin at the digital interface of the QAP is set to a logic 0. QO1 =1 The corresponding pin at the digital interface of the QAP is set to a logic 1. Note: The Output Pin O1 of the QAP is tristate after reset and will be enabled by the first SOP command. Semiconductor Group 85 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Programming the MuSLIC aio1 Value for the programmable Input/Output Pin 101 of the QAP if programmed as an output pin. If the bit REXTEN (XR2-7) is set to 1 (external ringing) the internally created Ring Burst On Signal (for an external relay driver) chapter 5.5) Qloi =0 The corresponding pin at the digital interface of the QAP is set to a logic 0. Qlo1 = 1 The corresponding pin at the digital interface of the QAP is set to a logic 1. alo2 Value for the programmable Input/Output Pin 102 of the QAP if programmed as an output pin. Qlo2 =0 The corresponding pin at the digital interface of the QAP is set to a logic 0. QlO2 = 1 The corresponding pin at the digital interface of the QAP is set to a logic 1. Data Upstream C/I - Channel Byte (transmit) - CIDU This Byte is used for fast transfer of the most important and time critical informations from the MuSLIC. Each transfer from the MuSLIC lasts for at least 2 consecutive frames. (Note that there is no address in DU direction too.) Bit 7 6 5 4 3 2 [_aioz [aor [aT HooK | nk | scx | SLCX Interrupt bit: Summary output of the whole signalling register (TCRO). SLCX = 0 No unmasked bit in the signalling register has toggled. SLCX = 1 Any unmasked bit in the signalling register has toggled. GNK Indication if a ground connection is detected (filtered via the DUPGNK- counter). The function is disabled in Power Down State (GNK is set to 0). GNK =0 No ground connection was detected. GNK = 1 Ground connection was detected. HOOK Indication of the loop condition (filtered via the DUP-counter or the DUPGNK-counter in Power Down State). HOOK = 0 Subscriber is Onhook. HOOK = 1 Subscriber is Offhook. qn Logical state of the Input Pin 11 of the QAP. Qh =0 The corresponding pin at the digital interface of the QAP is receiving a logic 0. Qli=1 The corresponding pin at the digital interface of the QAP is receiving a logic 1. Semiconductor Group 86 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Programming the MuSLIC Qlo1 Logical state of the programmable Input/Output Pin 101 of the QAP - even if not programmed as an input pin. " Qlo1 =0 The corresponding pin at the digital interface of the QAP is receiving a logic 0. QloO1 =1 The corresponding pin at the digital interface of the QAP is receiving a logic 1. Qlo2 Logical state of the programmable Input/Output Pin 102 of the QAP - even if not programmed as an input pin. QIO2 = 0 The corresponding pin at the digital interface of the QAP is receiving a logic 0. QIO2 = 1 The corresponding pin at the digital interface of the QAP is receiving a logic 1. 1) If the Input/Output Pin is programmed as an output the corresponding bit in the CIDU is “1”. The DUP- (DUPGNK-)counters filter the status-information and the input I1. The counters count down and generate enable signals for the registers if they are zero. Then they start counting again at the programmed value. If a status information or the input signal changes the proper counter is set and continues counting down. There are DUP-counters for HOOK, VB/2, ICON, LSUP generating SLCX and the input pin 11 and one DUPGNK-counter for HOOK in Power Down mode or for GNK in all other modes. Changing the mode freezes the actual status of HOOK and sets the actual HOOk-counter. Semiconductor Group 87 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Operating Modes

5 Operating Modes

The MuSLIC supports 3 different Operating Modes: Power Down (PDown), Active and Ringing which are controlled via the lower 3 bits of the Data Downstream C/I Channel Byte (CIDD). Table 7 M2 M1 Mo Description (CIDD-4) |(CIDD-3) | (CIDD-2) 0 0 0 Power-Down High Impedance (PDNH) 1 1 1 Power-Down Resistive (PDNR) 0 1 Active State 1 1 Active State with Meterpulses 1 0 Active State with Ground Start 0 1 Ringing State (ring pause) 1 1 Ringing State (ring burst on) Semiconductor Group 88 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Operating Modes Power Down {PDNA) Rev. Pal. wi e/ / C3 TTXNO=1 Ring Burat Co ee wo [oot] Power Down {PDNH) M2, M1, MO bits f0.9. 160) POWERON- HW-Reset Reset Figure 25 Semiconductor Group 89 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Operating Modes se es Ss < ga S we SB /S3l, 2 12316 |sl5 Je Ee c = Ea ee z lo z= le gfe { [| pp. [. f | fT | S x x x x ef] f~ [f.[ ff. | fy | S x|x<_| x a S x| x x g gS x |x|x |x x iJ flilgi-[-[> 77] | | i. | goes eh & s 7 F > «= x rx > i G 2 2 e ® & = Be bat = 5 2 Ea! 2s P6/e 5/5 lelesi@ |Pee/fee/fee = < 2g|2s\\2 S|s9 S23) a23| ofs t= & [fF /&e/ 2/22 (25leletla ESS [ESS ESS = > a yx o 8 [-% geo ° a fay «© 2° iJ = a] | led al Selo l- lel- Ie lel- lo--le- Joe lor Semiconductor Group 90 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Operating Modes

5.1 Reset Behavior

The MuSLIC has 2 different reset sources that are internally connected. The Reset pins, which work totally asynchronously to the external clocks. Power On Reset. If internal VDD gets above typ. 2.33 V the MuPP is reset by Power On Reset. Both sources set the MuSLIC to the basic setting modes (see below). After a reset caused by any of the sources mentioned above, the reset bit (TCRO-1 = RES) is set to one and the SLCX-interrupt (CIDU-2) is set. Reading the TCRO register clears the interrupt and the RES-bit. The Reset pin (RESET) of the MuPP and the QAP has a Schmitt-Trigger input to reduce the sensitivity for spikes. In addition the pin RESET has a spike rejection. All spikes smaller than typ. 70 ns are neglected. The pin RESET can be set to 1 for an unlimited time but at least 2 1s is recommended; during that, the DU pin is set to high impedance. The 11C-IO pins are set as inputs. In the MuPP a reset activates the reset routine - but only if the DCL is present - which lasts at least two 2 kHz frame (AFSC) periods for setting the default values. After this time and if an external reset is not active (RESET = 0) the MuPP starts the normal (default) operation at the beginning of the next 8 kHz frame (FSC). In the QAP a reset works totally asynchronously and no reset routine is necessary. The normal (default) operation of the QAP starts at the beginning of a 2 kHz frame (ASFC) if the external reset (RESET = 0) is released.

5.2 Basic Setting Modes

After RESET, the MuSLIC is switched automatically to its basic settings in which internal default values for all filters and settings (AC and DC) are used. The whole module works in a kind of “emergency mode” and can be handled by the C/I-Interface commands only. This means that for an (un-)determined reset (e.g. Power On Reset) the MuSLIC is reset, but can be switched to or return automatically into any operating mode presented by the C/l-channel after 2 AFSC + 2 FSC cycles. In all modes the outputs (QO,) become tristate up to the first SOP Command, the I/Os (MIO;, QIO;) become inputs, supervision and DC-feeding are still working and conversation can go on in a proper way until all filters and settings have been reloaded by SOP, XOP and COP Commands. Actions initialized by a reset: — All configuration registers are set to their default values (note that the Coefficient RAM is not reset) — The RES-bit (TCRO-1) is set to 1 to indicate that a reset has taken place — The IOM-2 and the 1C-interface is reset. Running communication is stopped — DUis in high impedance state — AC- and DC-loop use the default values and not the programmed ones (see below) Semiconductor Group 91 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Operating Modes Table 9 pc Const | Limit for Constant Current Const V Limit for Constant Voltage Vdrop Overall voltage drop BoostGain 13 | | Additional gain in Boosted Battery Mode RFS Feeding Resistance (excluding the external Fuse resistors) fring Ring Frequency Aring Ring rms-value at Ring/Tip wire DC Offsetiring Ring offset fringe Corner Frequency of Ring-Lowpass OffhookPD Power-Down Current for Offhook Detection OffhookAct [s|ma_| Offhook Detection in Active with 2 mA hysteresis OffhookRing DC-Current for Offhook Detection in Ringing Mode LineSup [5 |ma_ | Current for Line-Supervision Levelmetert [8 [mA _ | First levelmeter threshold Levelmeter2 Second levelmeter threshold Levelmeter3 Third levelmeter threshold Levelmeter4 Fourth levelmeter threshold GKD1 First threshold-current for Ground-Key-Detection GKD2 Second threshold-current for Ground-Key-Detection RingTip Threshold at Ring/Tip wire DC-Lowpass [0.320 |Hz _| DC- Lowpass set to 0.3 and 20 Hz respectively ConstRamp Slope of the ramp while testing delaying [0 _|ms __ | Delay of Ring Burst SRend1 el Silent-Reversal threshold 1 (referred to the input of the rampgenerator) SRend2 ee Silent-Reversal threshold 2 (referred to the input of the rampgenerator) SRduration [ca. 80 |ms | Duration of a Silent-Reversal-sequence DUP [10 |ms_| Data Upstream Persistency Counter is set to 10 ms DUPGNK [20 |ms_ | Data Upstream Persistency Counter for GNK is set to 20 ms + Boosted Battery is reset to normal feeding + Reverse Polarity is reset to Normal Polarity + All bits of the Signalling Register are masked and reset to 0 without the RES bit Semiconductor Group 92 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Operating Modes + The Data Upstream C/I channel bits are set to 0 except SLCX, it is set to 1 (the IO's are set to Input pins) + Outputs are set tristate until the first SOP command * C1 and C2 are set to PDNH + A-Law is chosen Table 10 AC IM-Filter [900 [2 _| Approximately 900 @ Real Input Impedance TH-Filter [THero | | Approximately BRD-Impedance for Balanced Network AX On ee Attenuation Transmit (this means about 0 dB) AR -15.11 |dB Attenuation Receive (this means about — 7 dB) ATIX 4 Vrms | Teletax Generator Amplitude at Ring / Tip wire at AHV-SLIC frrx Teletax Generator frequency; TG1 1008 Hz Tone Generator 1 and AC -levelmeter Bandpass (—14 dBmo) TG2 [2000 [Hz | Tone Generator 2 (+ 2 dB compared to TG1)

5.3 Power Down (PDown)

After a Reset (including the Power On Reset) or programming the CIDD-Byte the MuSLIC is set to Power Down State. In Power Down all functions which are not necessary are disabled to minimize power consumption. This can be done for all the channels or only for the not active ones. While the interface is fully working - including programmability of the registers with SOP or XOP commands and the Coefficient RAM (COP commands) - the rest of the MuSLIC is turned off except the supervision of the line. The change of the line state is reported via the HOOK-bit in the IOM-2 Data Upstream channel. To avoid spurious Offhook informations caused by longitudinal induction the HOOK-bit is low pass filtered (programmable with the DUPGNk-counter in PDown state only). The voice channel Data Downstream is directly fed into the voice channel Data Upstream. The HOOK-indication in PDown is optimized for longitudinal suppression up to 65 Vrms for the Offhook transition. In Power Down Mode the AHV-SLIC can be set into two different modes: 1. PDNR, the resistive mode which provides a connection of 10 kQ from TIP and RING to BGND and VBAT, respectively 2. PDNH, offers high impedance at TIP and RING Semiconductor Group 93 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Operating Modes

5.4 Active Mode (Act)

In Active Mode (“Conversation State”) both AC-and DC-Loop are fully working. The output voltage at the DC pins is controlled via the IT input pin in such way, that it behaves like a constant current source which turns automatically into a programmable resistive feeding source due to the DC-Characteristic values. The ternary AHV-SLIC-interface is set to one of the active modes. Polarity The MuSLIC supports either normal or reverse Polarity which is set by the POLNR-bit (SCRO-7). A 180 degrees phase shift of the AC- and DC-Loop is done. The performance and the functionality is not influenced by that. Boosted Battery To feed subscriber lines with enhanced loop resistance the MuSLIC supports the Boosted Battery mode. The AHV-SLIC-Interface pins (C1, C2) are set to Boosted Battery (BB) mode and the maximum DC output voltage is extended to 140 V. Meterpulses The MuSLIC supports two different kinds of meterpulses: Meterpulses with 12/16 kHz (Teletax Metering) and with polarity reversal. The decision between these two types is made by the bit TTXNO (SCR1-7). If the bit TTXNO is set to 1 then the meterpulse is reversal. If the bit TTXNO is set to 0, Teletax Metering is used. Metering with Polarity Reversal As long as the M1 and the M2 bit of the C/I-channel (CIDD-4) is set to 1, the MuSLIC performs an immediate 180 degrees phase shift of the AC- and DC-Loop. Teletax Metering Injection For countries with Teletax Metering the MuSLIC provides either a 12 or a 16 kHz Signal (switchable with the bit TTX12 (SCR1-6))") which amplitude is free programmable up to 10 Vrms at the Ring/Tip wire. The MuSLIC filters the Teletax pulses in transmit direction, too. The slope of the pulses are internally shaped so that the noise during switching and transmission is less than 50 x 6.25 uV at AC pins and 1 mV at the IOM-2 interface (psophometrically weighted). With the bit NOSL (SCR1-5) the slope can be switched off. In that case the switching noise is not defined (for signalling only). 1) Note, that the right Teletax Coefficient Set (via COP-command) must be provided, too. Semiconductor Group 94 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Operating Modes

5.5 Ringing Mode

The MuSLIC generally supports balanced and unbalanced ringing. If the MuSLIC is set to Ringing Mode, the AC-loop is turned off and the DC-loop is automatically opened. The voice channel Data Downstream is directly fed into the voice channel Data Upstream. Balanced Ringing The sine wave of the ringing is generated in the MuSLIC. The frequency and the amplitude are free programmable between 16 and 70 Hz and up to 85 Vrms at the Ring/ Tip wire, respectively. The DC offset voltage is programmable between 0 V and 30 V. If the Ring Burst On command is sent to the MuSLIC via the C/I-channel (MO and M2 = 1) the begin (M2 = 1) and the end (M2 = 0) of the ring burst is automatically synchronized at the voltage zero crossing. If the DC-current at the IT-pin exceeds the programmed value, Offhook is detected within 2 periods of the ringing frequency and the Ring Burst is neglected. If Offhook is detected the MuSLIC changes automatically to the active mode. Unbalanced Ringing The ringing voltage is generated by an external ring generator. To connect this generator to the Ring/Tip wires relays are used. To control the relays the MuSLIC offers following functions: If the REXTEN bit (XR2-7) is set to 1 the MIO1 is an input for the zero crossing signal. QIO1 is switched to the CIDD-4 (M2 bit) and offers the zero crossed ring burst on/off control signal.

5.6 Ground Start

Changing into the Ground Start mode by programming the CIDD Byte (M2 = 1, M1 and MO =0) the active mode is chosen and the Ternary SLIC-interface is set to high impedance of the Tip output (HIT: C1 = VOM, C2 = VOH).

5.7 Changing Modes

Offhook detection is low pass filtered with the time of 2 x DUP counter if any change of the modes or if one of the following crossovers occurs: ring burst <---> ring pause reverse <----> normal polarity boosted <----> normal battery ground start on <---> Off PDNR on <---> Off FIXC, LOAD, RESET on <----> off Semiconductor Group 95 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Transmission Characteristics

6 Transmission Characteristics

The target figures in this specification are based on the subscriber-line board requirements. The proper adjustment of the programmable filters (transhybrid balancing, impedance matching, frequency-response correction) needs a complete knowledge of MuSLIC analog environment. Unless otherwise stated, the transmission characteristics are guaranteed within the test conditions. Test Conditions Ty = 0 to 70 °C; Vooi = Vooa = Voos = Vooc = Voon = 5 V 5%; Veg = — 5 V 5%} Vpp = 3.3 V + 5% GNDI = GNDA = GNDB = GNDC = GNDD = 0 V Hims Hru, Herx» Herr: AR, AX will be defined to meet the 0 dBm0 specification. f= 1004 Hz; 0 dBm0; A-Law; A 0dBm0 AC signal in Transmit direction is equivalent to 2 x 0.775 Vrms and in Receive direction equivalent to 0.775 Vrms (referred to 600 ©). Pa oO TIP. N a Mw 6000 0) £ — hy Mm 2 [2"0.775 V.., OP Noe O RING BS B BS eh BESCHAL1.DSF, 5.7.96} Figure 26 OdBMO|Musuic =O dBMO|g99Q = 0.775 Vrms for receive direction. OdBM0|yustic =O AdBMO|g99 = 2% 0.775 Vrms for transmit direction. Semiconductor Group 96 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Transmission Characteristics

6.1 Transmission Values

Parameter Sameer jue Test Condition Pre ae eee Interface Requirements 2-wire port | ft f2 x 100 2, inal. Out of band signalling Metering signal Vab 45 4.85|5.2 |Vrms_ | 12/16 kHz @ 2002 Ringing injection Vab 60 63 |66 |Vrms_ | 16 Hz to 50 Hz Longitudinal current capability AC In loo | | bene per line active Transmission performance Overload level ees || mw, 300 Hz to 4 kHz Return loss (2-wire) R, 14 18 dB 300 Hz to 500 Hz RL 18 dB 500 Hz to 2 kHz RL 14 18 |dB 2 kHz to 3.4 kHz Insertion loss Transmit V gain G, -0.3 0.3 |dB 0 dBm0O, 1 kHz Receive V gain G, -0.3 0.3 |dB 0 dBm0O, 1 kHz Insertion loss versus frequency relative to 1 kHz Transmit V gain G, see chapter 6.2 0 dBm0O, 0.3 to 3.4 kHz Receive V gain G, see chapter 6.2 0 dBm0O, 0.3 to 3.4 kHz Gain/Loss programmability Transmit absolute Tx 0.5 |dB voice band, in steps of +3dBr Receive absolute Ry 0.5 |dB voice band, in steps of 0...-12 dBr Semiconductor Group 97 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Transmission Characteristics

6.1 Transmission Values (cont'd)

min. [typ. |max.| Gain linearity relative to 1 kHz, -10dBm0 Transmit V gain G, see chapter 6.3 — 55 dBm0 to +3 dBm0 Receive V gain G, see chapter 6.3 — 55 dBm0 to +3 dBm0 Balance return loss | f2eo | | fw 500 Hz to 2.5 KHz Absolute group delay see chapter 6.4 distortion Overload compression | OC see chapter 6.5 AIA Longitudinal balance Longitudinal to L-T 52 dB 300 Hz to 3.4 kHz transversal world market requirement US market requirement | L-T 58 65 dB at 1020 Hz Transversal to T-L 46 dB 300 Hz to 4 kHz longitudinal Longitudinal signal T-L 46 dB 300 Hz to 4 kHz generation Semiconductor Group 98 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Transmission Characteristics Parameter a Test Condition [min. |typ. | max. Out-of-band Noise Pot | ft | single frequency inband - 25 dBmO Transversal Vab -—50 |dBm 12 kHz to 200 kHz Longitudinal fm || Pee | 12 kHz to 200 kHz Metering injection Impulse noise during Vab 1 mV psophometrically switching At 2-, 4-wire interface | V,, 1 mV weighted Harmonic distortion 5 % Ringing injection Superimposed d.c. Vide 20 22 (24 |V R,_=10kQ voltage Harmonic distortion THD 5 % Z.=1kQ || 6 uF Ring trip function Detection time and 12ms periods delay after The ringing to off hook periods status Cut off the ringing Semiconductor Group 99 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Transmission Characteristics min. [typ. |max.| Interface Requirements 2-wire port and PCM side Total harmonic distortion 2- to 4-wire Tad -46 |dB -7 dBm0, 0.3 to 3.4 kHz 4- to 2-wire Tao -46 |dB -7 dBm0, 0.3 to 3.4 kHz 2-wire port (receive) Vab -70 |dBmp | psophometric (idle A-Law code 0) p-Law Vab 20 |dBrnc | C-massage (idle code +0) PCM side (transmit) A-Law Nyp -67 |dBmp | psophometric (Vi = 0) p-Law Nyc 20 |dBrnc |C - massage (Vi = 0) Signal to total distortion ratio Input connection: s/D see chapter 6.6 - 45 dBm0 to 0 dBm0 L,=0dBr Output connection: s/D see chapter 6.6 — 45 dBm0 to 0 dBm0 L,=-7 dBr Semiconductor Group 100 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Transmission Characteristics Parameter Pm neers foe Test Condition fin. typ. max Battery Feeding Pot | ft | Veat = — 68 V, Vy=+52V Power Down Mode (PDNR) Loop resistance eles te toe be | Active Mode without calibration Loop current (without | /, 19 mA R,=1.8kQ TTX) Toop Accuracy I, 23 25 |27) |mA Tinke = 25 MA Toop accuracy I, 27 30 =|33 mA Tinkg = 830 MA Troop accuracy I 4 45 |49 mA Tinka = 45 MA 1, negative wire Iw 90 120 |mA wire to ground Transition time Tot 0.5 1.5 |ms On to Offhook Boost Battery Mode Loop current same as active state Output voltage Vab 78 Vv Tine = 20 MA Indication thresholds ee ee ee ee Offhook indication Offhook current Leet 7 9 1 mA Hysteresis 2 mA Ground Key indication Ground Key current Tet 10 17 |24 |mA Ring trip indication Current threshold 1 Toet 6 7 8 mA short line + bat. charging Current threshold 2 I ge 2.5 3.5 145 |mA long line Power supply rejection Fo | | | of Viippte = 100 mVpp ratio VCC referred to AGND |PSRR_ |30 dB 50 Hz to 4 kHz -objective 40 dB 50 Hz to 4 kHz 4 kHz to 128 kHz Semiconductor Group 101 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Transmission Characteristics fin. [typ. |max.| VBAT referred to AGND|PSRR_= |30 dB 50 Hz to 4 kHz -objective 40 dB 50 Hz to 4 kHz t.b.d 4 kHz to 128 kHz BGND referred to PSRR_ |40 dB 50 Hz to 4 kHz AGND -objective 40 dB 50 Hz to 4 kHz t.b.d 4 kHz to 128 kHz Semiconductor Group 102 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Transmission Characteristics

6.2 Frequency Response

a Cc 1! gs I g 09 +---4 0.7 +---4- ' 0.3 +---4-L- H fl hyo 1 ' ' tt ' t 1 03 ! 1 i i i ! i io i H 1 H t 4 1 ' H fo 0 234 6 1.0 20 24 30 34 36 fr_respt.dst Figure 27 Transmit: reference frequency 1 kHz, signal level — 10 dBm0, Hrrx = 1 ao « 14 s ' 3 ' $ 09 4---1 | 07 fo ' 2 os i j { tt 04 |) Fie ee ee | :

03 F--- sort ; 1

9 1 f t t ' -0.3 ‘ . . , . ——> Frequency kHz fr_respr.dst Figure 28 Receive: reference frequency 1 kHz, signal level — 10 dBm0, Hear = 1 Semiconductor Group 103 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Transmission Characteristics

6.3 Gain Tracking (receive or transmit)

The gain deviations stay within the limits in the figures below. measured with sine wave f= 1004 Hz reference level is — 10 dBm0. m +2 7 416 ----- o + 4 : <j ‘ +406 5---.---4 \\ 40.3 . o - : : : x : 03 : ; ; f : 0.6 - ' : ' : 16 2 : : : : -2 - ‘ - 55 -50 -40 -30 -20 -10 O +3 > fh & 3) GT_TRAN1.DSF Figure 29 Semiconductor Group 104 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Transmission Characteristics

6.4 Group Delay

Maximum delays when the PEB3465 and the PEB 31665 are operating with Hyy=Hiq=0 and Hegg=Hepx= 1 including delay through A/D- and D/A converters. Specific filter programming may cause additional group delays. Group Delay deviations stay within the limits in the figures below. Group Delay absolute values: Signal level — 10 dBm0 Table 11 Parameter Symbol Limit Values Test Condition min. |typ.__[max. a 3 300 c Bo} So a o 150. a Qa 5 6 1.0 26 28 ———> Frequency kHz gr_del.dst Figure 30 Group Delay Distortion receive and transmit: Signal level — 10 dBm0, frost? Tomin Semiconductor Group 105 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Transmission Characteristics

6.5 Overload Compression

, 5 Fundarrental c 4 Ollbut

4 Power

_ 2 | ; ; ! 0.25 ere ee ee ee pe eee ee eee oO i : -0.25 a 4 3.4 0 1 2 3 4 5 6 7 8 9 Fundamental Inout Power (dBm0) OL1_COM.DRW, 26.4.94 Figure 31 Transmit: measured with sine wave f = 1004 Hz Semiconductor Group 106 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Transmission Characteristics

6.6 Total Distortion

The signal to distortion ratio exceeds the limits in the following figure: Receive: measured with sine wave f= 1004 Hz. (C-message weighted for 1-law, pso- phometrically weighted for A-law). The mean relative level is — 7 dBr. 4 : : : o : : DO Bt lll lL LLL lee Ad 309 Oo p : : L Oo » : : : : 0 45 ~40 0 2 -10 0 - A sd_rdst Figure 32 AR = 7 dBr Table 12 Parameter Symbol Limit Values Test Condition [min. [typ _ | max. | Signal to distortion at | SDaia -13 Signal S = - 40 dB full attenuation AR = + 30 dB Semiconductor Group 107 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Transmission Characteristics Transmit: measured with sine wave f = 1004 Hz. (C-message weighted for ,1-law, pso- phometrically weighted for A-law). The mean relative level is 0 dBr. 40) : : : a : : : DO BSL----:2:2::25: tittle : : HB! : ‘ Z % : : : 285 : : : a as! eee mee ot. - ° @ 0 ' 50 45 40 0 20 -10 0 > i a sd_tdst Figure 33 AX = 0 dBr Table 13 Parameter Symbol Limit Values Test Condition [min |typ. | max. | Signal to distortion | SDoy7 -17 Signal S = — 40 dB at full gain AX =- 30 dB Semiconductor Group 108 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Transmission Characteristics

6.7 Out-of-Band Signals at Analog Output (receive)

With a 0 dBm0 sine wave with frequency f (300 Hz to 3.4 kHz) applied to the digital input, the level of any resulting out-of-band signal at the analog output will stay at least X dB below a 0 dBm0, 1 kHz sine wave reference signal at the analog output. 45 17D09762 |__| Fe | so os Ul ee i 0 0.06 0.1 34 4 46 6 10 18 kHz 200 —+f “xX = i 4000-f) Figure 34 Semiconductor Group 109 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Transmission Characteristics Out-of-Band Signals at Analog Input (transmit) With a 0 dBm0 out-of-band sine wave signal with frequency f (< 100 Hz or 3.4 kHz to 100 kHz) applied to the analog input, the level of any resulting frequency component at the digital output will stay at least X dB below a 0 dBm0, 1 kHz sine wave reference signal at the analog input. ?) 40 . 11009763 | s poppet | 990.06 0.4 34-4 46 «6 10 18 kHz 100 —+f . F 4000 — ) 7 ) Figure 35 Poles at 12 kHz + 150 Hz respectively 16 kHz + 150 Hz and harmonics will be provided Semiconductor Group 110 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Transmission Characteristics

6.8 Transhybrid Loss

The quality of Transhybrid-Balancing is very sensitive to deviations in gain and group delay — deviations inherent to the MuSLIC A/D- and D/A-converters as well as to all external components used on a line card. Measurement of MuSLIC Transhybrid-Loss: A 0dBm0 sine wave signal with a frequency in the range between 300 — 3400 Hz is applied to the digital input. The resulting analog output signal at the differential outputs ACP and ACN is connected to the pin ITAC. The programmable filters FRR, AR, FRX, AX and IM are disabled, the balancing filter TH is enabled with coefficients optimized for this configuration (ACP-ACN = ITAC). The resulting echo measured at the digital output is at least X dB below the level of the digital input signal as shown in the table below. Table 14 [COP-write | Coefficients TH-Filter Part 1 tb.d. TH-Filter Part 2 t.b.d. TH-Filter Part 3 t.b.d. Table 15 Parameter Symbol emacs in Test Condition Transhybrid Loss at500Hz |THL.. | [50 |[aB_ | Transhybrid Loss at 2500Hz|THloco | [44 [dB | Transhybrid Loss at 3000 Hz [THLin | [42 [aB | Semiconductor Group 111 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165

Electrical Characteristics

7 Electrical Characteristics

7A PEB 3465 (QAP)

7.11 Absolute Maximum Ratings

Parameter Symbol | Limit Values Yr Test Condition VDDA-VDDD referred to -0.3 |5.5 |V GNDA-GNDD VDDI referred to GNDI | —s[-o3 [55 |v | VSS referred to all GND pins | si f[-s5 jos fv | GNDA-GNDD to GNDI [Fos fos [v_| Analog input and output voltages referred to -10.3/0.3 |V VDD = 5 V; (VSS = -5 V) referred to -0.3 |10.3 |V VSS = - 5 V; (VDD = 5 V) All digital input voltages referred to GNDI = 0 V; (VDDI = 5 V) -0.3 |5.3 |V referred to VDDI = 5 V; (GNDI = 0 V) -5.3 ]0.3 |V DC input and output current at any 100 |mA input or output pin (free from latch-up) Ambient temperature under bias 7, _[-10 |8o [ec | Note: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Functional operation under these conditions is not implied. Exposure to conditions beyond those indicated in the recommended operational conditions of this specification may effect device reliability. Semiconductor Group 112 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165

7.1.2 Operating Range

T= 0 to 70 °C; all Von's = 5 V 45%; Veg = - 5 V 5%; all GND’s =O V Parameter Pen Values ver | Test Condition [min. typ. [max. | Vpp supply current’? Power down IDDepown 24 mA all channels PDown Active IDDact 67 mA all channels active Vgg supply current’) Power down ISSppown mA all channels PDown Active ISSact mA all channels active Power supply PSRR ripple: 1 kHz, rejection-ratio 100 mVrms Receive VDD t.b.d. Receive VSS t.b.d. Transmit VDD 40 dB at IOM-2 Transmit VSS 40 dB at IOM-2 Power dissipation" Power down Poepown 120 mW [all channels PDown Active Pact 180 mW |1 channel active Active Pact 360 mW _ [all channels active ) Power dissipation and supply currents are target values Note: In the operating range the functions given in the circuit description are fulfilled. Semiconductor Group 113 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165

7.1.3 V/O-Pins

Ty = 0 to 70 °C; all Vop’s = 5 V 5%; Veg = -— 5 V+ 5%; all GND’s = 0 V Parameter Symbol | Limit Values a Test Condition For all input pins: Low-input pos.-going Vay -0.3 13.15 |V see figure 36 Low-input neg.-going Vr. 1.35 |VDD |V see figure 36 +0.3 Low-input Hysteresis Va 0.5 Vv Va = Vz,- Vy. Input leakage current i f-1 ft [na | — 0.3 <= Vi, <= Vpp Spike rejection for RESET [7 (50 [200 |ns | For 1/01 and O1: Low-output voltage Vor Vv Ig=-50 mA High-output voltage Vou 3.5 Vv Ip=2mA For 1/02: Low-output voltage Vor 0.5 Vv Ig=-2mA High-output voltage Vou 3.5 Vv Ig=2mA Vout ye Vy Vin HYST.DR Figure 36 Semiconductor Group 114 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165

7.1.4 DC-Feeding

Ty= 0 to 70 °C; all Vop's = 5 V 5%; Vsg = - 5 V + 5%; all GND’s = 0 V Parameter Limit Values Test Condition min. [typ-[max. | “Line Current” Measurement: Transmit Vir ottset |— 25 25 |mV__ |direct/reverse polarity” Vir gain | 0.95 1.05 f< 50 Hz, direct/reverse polarity Virtup | 40 dB direct/reverse polarity “Line Voltage” Feeding: Receive Voc ottset | - 25 25 mV __ {normal battery, f= 300 Hz Voc gain | 0.94 1.06 normal battery, f= 300 Hz Voctupn | 40 50 dB normal battery Receive Boosted Voc otset_ | - 40 40 mV __ | boosted battery, f= 300 Hz Voc gain | 1-5 1.6 1.7 boosted battery, f= 300 Hz VoctHp | 40 50 dB boosted battery 1) Reverse polarity is an internal state of the PEB 31665; the polarity of the voltage at PIN IT is positive. Semiconductor Group 115 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165

7.1.5 AHV-SLIC Interface and Supervision Functions

Ty = 0 to 70 °C; all Vop’s = 5 V 5%; Veg = - 5 V + 5%; all GND’s = OV Parameter Symbol Limit Values Test Condition/ [min [typ __[max.| _| Result Longitudinal Vit gain 1 1.4 f<50 Hz Current Input (IL) Vin=—2.4...4+24V Auxiliary Inputs Vy gain 1 14 f< 50 Hz; Output voltage: AHV-SLIC-Interface C1, C2 High level Vonuv 0.8 x VDD Vi | Toap < 10 pA Mid level Vomuy 0.51 x VDD Vi Top < 10 pA Low level Vou 0.22 x VDD Vv Tout < 10 pA Current drained lotto pA |TEMPA=0" from pin C1 in all Tot 120 HA | TEMPA=1 3 states ’ TEMPA is reported via the MuPP/QAP-Interface to the PEB 31665 Semiconductor Group 116 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165

7.2 PEB 31665 (MuPP)

7.2.1 Absolute Maximum Ratings

Parameter Symoet mt natags| nt Remarks Vop referred to GND -0.3 |3.6 Vv Vops referred to GND -0.3 |5.5 Vv All digital input voltages (Vpp5 = 5 V) referred to GND = 0 V; (Vpp = 3.3 V) -0.3 {5.3 |V referred to Vpp = 3.3 V; (GND = 0 V) -5.3 |0.3 Vv DC input and output current at any input 100 |mA or output pin (free from latch-up) Ambient temperature under bias 7, |-10 [go [ec | Package power dissipation Ce a ee ee Note: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Functional operation under these conditions is not implied. Exposure to conditions beyond those indicated in the recommended operational conditions of this specification may effect device reliability.

7.2.2 Operating Range

Tn = 0 to 70 °C; Vpn = 3.3 V+ 5%; GND = 0 V Parameter Symbol Limit Values Test Condition ‘min typ. max. Power dissipation (all t.b.d. mW | Vp) =3.3V channels active Power dissipation (only tb.d. mW |Vpp =3.3 V 1 channel active) Power dissipation (no tb.d. mW |Vpp =3.3V channel active) Note: In the operating range the functions given in the circuit description are fulfilled. Semiconductor Group 117 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165

7.2.3 Characteristics

Ty = 0 to 70 °C; Vpp = 3.3 V+ 5%; GND =0V Parameter Symbol | Limit Values on Remarks For all input pins Input low-voltage Vit TTL Level Input high-voltage Vin Input leakage current - 0.3 <= V,, <= VDD5 For all output pins Set-up time t, typ. 30|ns_ | Load capacitance 30 pF Output low-voltage Vor 0.45 |V Io, = - 3.2 mA” Output high-voltage Vou 0.7 VDD Vi Ion = 2mA ) DU: Io, =-7MA Note: The listed characteristics are ensured over the operating range of the integrated circuit. Typical characteristics specify mean values expected over the production spread. If not otherwise specified, typical characteristics apply at T, = 25°C and the given supply voltage. Semiconductor Group 118 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 7.2.4 1OM®-2 Switching Characteristics t toct ‘DCLA DCL gy U | t trsc_s tel me FSC \\ tos tooy DD yy WV ye feou| DU ee a 11109764 Figure 37 Table 16 Switching Characteristics Parameter Limit Values Unit min. typ. [max. | Period DOL Ce 1) With a pull-up resistor of 1 kQ and a capacity of 50 pF. Semiconductor Group 119 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 90% Command OUT [sd Old Command Valid (XXY New Command Valid moves |

0 XK OGREXT

? Frame | Later | Loz Command High Imp. Out |) All Outputs t "dCA Command High Imp. All Outputs ? Frame Later DU (| Kegan” First indication Bit OUT tins finn Ind. IN i 1 All Inputs 117109765 Figure 38 IOM®-2 Command/Indication Interface Timing Semiconductor Group 120 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Table 17 Switching Characteristics min. |typ. max. | Command/Indication interface timing depends on time slot and for QIOs additionally on AFSC-period. 7.2.5 uC-Interface Switching Characteristics = lu tt ALE / \\ / \\ csq -=_ teswe _ twcosH WRQ \\ : / iw =< = rw e—_—_ tiaxs pe <— <_— com 5») DIO : \\ DATA OUT jy ~~ iw ore Se tticx Figure 39 Timing Specifications for a Write Access to the .C-Interface Semiconductor Group 121 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 tesAL <_ > trost Too ruby tiw.—a~ <— = taLRH _ oa a > <— trnoz [X ey, ~~ tw <= tataz Stix ——— tavov Figure 40 Timing Specifications for a Read Access to the .C-Interface Semiconductor Group 122 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 RD pulse width lium | [9s | | | [ns WR pulse width ltwwe | (9s |] ns Address hold after ALE Ite | (85 | | | [ns RD to valid data in leaov | «(35 | S| S| ns Data hold after RD ltawox | [ts | | | ns Data float after RD fanz | (40 | | | Ins ALE to valid data in lmov | (35 [| | | Ins Address to valid data in ltvov | {50 | | | Ins ALE to WR or RD liom | [90 | | | ns WRorRDhightoALE high Jiwun | [55 | | | _—i[{ns ALE high time Jim | [40 | [| [ns Address setup to ALE lin | [390 | | [Ins Data setup before WR own | [45 | ff ns Data hold after WR lenox | [35 | | | ns Address float after RD ltumz | (15 [| | | ns CS low to WR low licom | [20 | | | ns CS low to AD low licsm | [20 | | | Ins WR high to CS high ltwosh | [20 | | | [ns RD high to CS high ltacsh | [20 | =| | ns Semiconductor Group 123 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165

7.2.6 QAP-Interface Switching Characteristics

too 7] tooth ty FSC I tyrsc fil AFSC t DUS t DU_H I ADUT/2—OXX_ K_) Itaop ADD1/2 ( Figure 41 Table 19 Parameter Symbol Unit min. [typ max. | Period ADCL ltr =| st. 384MHz || Semiconductor Group 124 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 7.2.7 /O-Switching Characteristics (101 to 104, IDO to ID3) t.b.d concerned to IOM-2 and uC

7.3 PEB 4165 (AHV-SLIC)

7.3.1 Absolute Maximum Ratings

Parameter Symbol Limit Values a Condition Battery voltage Veat 0.5 Vv referred to BGND Auxiliary supply voltage Vu -0.5 Vv referred to BGND Total battery supply voltage, | V4y-Vgar 160 Vv continuously Total battery supply voltage, | V4-Vgar 170 Vv pulse < 1 ms VDD supply voltage Voo 5.5 Vv referred to AGND VSS supply voltage Vg -5.5 0.4 Vv referred to AGND Ground voltage difference |VBGND |-0.5 0.5 Vv -VAGND Input voltages VDCP/N Vv VACP/N |VSS-0.3 | Vp) + 0.3 VC1, VC2 |-0.3 Vop +0.3 Voltages on current outputs | VIT, VIL RING, TIP voltages, Va, Vr Veat-0.3 |Vyt+0.3 |V continuously RING,TIP voltages, Va, Vr Veat-10 |V4+10 Vv pulse < 1 ms RING, TIP voltages, Vas Vr Veatr-20 |Vyt+20 |V pulse < 1 ys ESD-voltage, all pins 1 kV Human body model Semiconductor Group 125 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165

7.3.2 Operating Range

Parameter pre Limit Value eo Condition Battery voltage Veat -24 Vv referred to BGND Auxiliary supply voltage | Vi, Vv referred to BGND Total battery supply Vu-Vear 150 Vv voltage VDD supply voltage Vop 4.75 5.25 Vv referred to AGND VSS supply voltage Vs - 5.25 -4.75 Vv referred to AGND Ground voltage -0.3 0.3 Vv difference Ambient temperature Tp 0 70 °C PEB 4165 -40 85 °c PEF 4165 Voltage compliance Vig Vie -3 3 Vv IT, IL Input range VDCP, VDC -3.2 +3.2 Vv VDCN Thermal Resistances Junction to ambient Rin ja K/W with heatsink, typ. Semiconductor Group 126 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165

7.3.3 Electrical Parameters

Min / max values are valid within the full operating range. If PEB- and PEF-specifications are different, both values can be found in the respective column. Testing is performed according to the test figures with external circuitry as depicted in fig. t.o.d. Unless otherwise stated, load impedance R, = 600 2, Vg,7=-70V and Vy =+ 60 V, Vop = +5 V, Vsg = — 5 V. Test temperatures are 25 °C and 70 °C for PEB, — 40 °C, 25 °C and 85 °C for PEF-type (without heatsink). Supply Currents and Power Dissipation (/, = Ip = 0 A; Vay = 0 V) No. | Parameter Limit Values | Unit |min. |typ. | max. | Power Down Mode 2. | Vsg current Isg PDNH 50 HA PDNR 150 HA 3. | Vgqy Current Teat PDNH 10 HA PDNR 50 HA 4. |V,, current Ty PDNH 1 10 pA HIRT, 1 10 HA Vy=+80V Active Mode 5. [Voocurent ‘(le [ACT | [83 | __|ma 8. |Vcurent | faCT. | [tT | [a 9. | Quiescent power dissipation [pa fact ——s| Sf | mw Semiconductor Group 127 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Supply Currents and Power Dissipation (/, = Jip = 0 A; Var = 0 V) " (cont'd) No. | Parameter Symbol Limit Values _| Unit [min. |typ. |max. | Boosted Battery Mode Ti [Vesourent ‘(iss ‘| (08 | [ma 13. [Vvcurent _|s [88 | |_| [ma 1) The total power dissipation consists of the quiescent power dissipation PQ given above, a Vpq dependent component PV and a component PI depending on the line curent /py: Ptot = PQ + PV + Pl with A Aetve fo | .08 ar Vea = Far Vo Boosted (Var / 100 k) x (Vy — Vga) 1.05 x Ipy x (Vy - Vgat) - lat X Var Semiconductor Group 128 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165

7.4 DC-Characteristics

° i ane al Toe a ve Line Termination TIP, RING 15. |DC line voltage | VTR,DC | ACT, BB te) Vv VDCP =— VDCN =0 V 16. VT,DC | ACT —35 Vv BB -5 v 17. VTR, DC | ACT 50 Vv VDCP =- VDCN =1V 18. -50 Vv VDCP =-— VDCN =-1V 19. | Max. DC line ACT 67 Vv VDCP =- VDCN = 1.5 V voltage Tgp = 20 MA 20. | Outputcurrent | |/;, max| mA |VR, VT limit | Fy, max| 21. | Loop open Rie PDNR |68 8 9.2 kQ | Typ =2mA, resistance TIP to Temp = 25 °C” BGND 22. | Loop open Rap PDNR |68 8 9.2 kQ |Ig=2mA, resistance RING Temp = 25 °C” to Vear 23. | Power denial ILeak,R |PDNH |-30 30 HA | Veat< VR < Vy output leakage current 24, ILeak,T -30 30 WA |Vpat<Vr< Vy 25. | High impedance | ILeak,R |HIR(T) |-30 HA | Veat<Va<Vy-3 output leakage current 26. ILeak,T | HI(R)T |-30 WA | Veat<Vr<Vy-3 Inputs DCP, DCN, ACP, ACN 27. | Input resistance | RDC 100 kQ DCP, DCN 28. | Input resistance | RAC 13 16 kQ ACP, ACN Semiconductor Group 129 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165

7.4 DC-Characteristics (cont'd)

No. Symbol | Limit Values er Test Condition Current Outputs IT, IL 29. | IT output current | /> ACT 15 WA |Ig==OmA 30. 380 420 WA |Iq=t,=20mA 34. | Offhook output uA | TIP/RING shorted current on I 35. | /_ output current | JL ACT 30 WA |ig=1,=20mA 36. 75 125 BA |Iq=15 mA, 1, =25mA 1, =37.5mA Control Inputs C1, C2 41. | Input leakage lLeak 5 HA |0<VC1(2)<+5V current 42. | Thermal Itherm 120 150 wA |VC1=1.25V overload current 43. | Switching Trott 165 °C temperature Tron 145 °C (guaranteed by design) ”) The systematic temperature dependence of these resistances is + 0.1% /°C Semiconductor Group 130 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165

7.5 AC-Characteristics

No. | Parameter Symbol Limit Values Test Condition min. typ. PEB/PEF Line Termination TIP, RING 44. | Receive gain Gr ACT, BB VACP =- VACN = 320 mVrms f=1015 Hz 9.78 10.02 Ipp = 25 MA 45. | Gain flatness dGr ACT, 0.05 300 Hz < f< 3400 Hz (guaranteed by BB design) 46. | Gain tracking dGr ACT 3 dBm0 > Var (guaranteed by >-20dBm0 design) 47. | Total harmonic THD ACT % VACP =~ VACN distortion Vay = 320 mVrms f= 1015 Hz, Tap = 25 MA 48. | Teletax distortion | THDTTX | ACT f= 16 kHz, R, = 2002 % Tg = 25 MA Var, AC = 5 Vrms 49. % Ipp =O mA, Var = 55 V Var, AC = 2 Vrms 50. | Psophometric Np,VRT | ACT -75 dBmp | /g7 = 25 MA noise 51. | Longitudinal to LTRR ACT 61/58 Vlong = 3 Vrms transversal 300 Hz < f< 3.4 kHz rejection ratio Tgp = 25 MA Viong/Var 52. | Transversal to TLRR ACT VACP =— VACN longitudinal = 960 mVrms rejection ratio Var 300 Hz < f< 3.4 kHz Nlong Tgp = 25 MA Power supply PSRR 300 Hz < f< 3.4 kHz rejection VSupply, ratio AC = 100 mVp 53. | VeaT/Var ACT, BB | 33 40 dB | far =25mA 54. | VilVar BB 33 40 dB 55. | Vpp/Var ACT, BB | 33 50 dB 56. | Vsg/Var ACT 33 50 dB Semiconductor Group 131 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165

7.5 AC-Characteristics (cont'd)

No. | Parameter Limit Values Test Condition min. typ. PEB/PEF 57. | Ringing distortion | THD BB 4 % RU=1K,C_=1 pF f= 66 Hz, VDCP =- VDCN = 0.4 V (DC) +1.3 Vrms (sine wave) Transversal Git VACP = — VACN current ratio = 320 mVrms 58. ACT, BB | 33.89 33.98 |34.07 |dB f= 1015 Hz ACT, BB | 33.89 33.98 |34.07 |dB Tar = 25 MA 59. Tgp = — 25 mA 60. | Gain flatness dGit ACT, BB 300 Hz</f (guaranteed by < 3400 Hz design) 61. | Gain tracking dGit ACT, BB | - 0.2 3 dBm0 > Var (guaranteed by >-—20 dBm0 design) Total harmonic THD,IT ACT VACP =-— VACN distortion VIT = 320 mVrms f= 1015 Hz 62. 0.01 % Int = 25 MA 63. tb.d. Ign = 0 mA 64. | Psophometric Np,VIT ACT -102 |dBmp] ig, =25mA noise Longitudinal to LITRR ACT Vlong = 3 Vrms transversal 300 Hz< f current output <3.4 kHz 65. | rejection ratio tb.d. dB Igp = 25 MA Viong/VIT 66. tb.d. dB | Igp=25mA Power supply PSRR 300 Hz < f< 3.4 kHz rejection ratio Vsupply, AC = 100 mVp 67. | Vear/Vir ACT 50 60 dB | Ig =25mA 68. | Vi/Vir BB 50 60 dB 69. | Vpp/Vir ACT 50 60 dB 70. | Vgg/Vit ACT 50 60 dB Semiconductor Group 132 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Test Features

8 Test Features

Table 20 Card Tests: (900 Q Testloop, Option: with relay) 1. Level PCM AC Loop | ITIME ENTE on | After programming the settings and release metering | MVA, LMBP ELM on with the ENTE the levelmetering will be AC RLMO/1 LMNOTCH started by ELM = 1. The end of measurement LM2PCM is shown by MVA, RLMO0/1 and the result can LMSELO/1 be sent to the CIDU-voice channel. ITIME ELM determines the Integration time either 16 ms or 256 ms. 2. Level PCM DC Loop | LPO3,LP5, | ENTE on | After programming the settings and release metering | MVA, DISPOFI, |ELMon with the ENTE the levelmetering will be DC RLMO/1 PCM2DC started by ELM = 1. The measurement time is DCAD16 programmable using the ring generator. The ERAMP end of measurement is shown by MVA, ERECT RLMO/1 and the result can be sent to the LM2PCM DU-voice channel. Includes measurement of LMSELO/1 Offset, and Ringer Capacitance. ELM frine 3. Level PCM DC Loop | ELM ENTE on | After programming the settings and release metering | MVA, TTXL ELM on with the ENTE the levelmetering will be TTX RLMO/1 LMSELO/1 started by ELM = 1. The measurement time is LM2PCM programmable by ITIME either 16ms or PCM2DC 256 ms. The end of measurement is shown by MVA, RLMO/1 and the result can be sent to the DU-voice channel. By setting TTXL and correct programming of the IM-Filters the TTX current is measured directly. Semiconductor Group 133 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Package Outlines

9 Package Outlines

9.1 PEB 3465 (QAP)

a. =sSsaesiie (Mastic Metric Quad Tat Package) 0.65 Le i 4 0,88 20.15 0.3 10.08 1285 {@[0.12_W/AB [DIC]80x hr [0.2 TAB1D]80x lh —=}—{5]0.2[ABIDIH)4x > (0) (EN | { | : =| E, FIN index Mating i as 1) Does not include plastic or metal protrusions of 0.25 max per side g a (o) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. ‘SMD = Surface Mounted Device Dimensions in mm Semiconductor Group 134 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Package Outlines

9.2 PEB 31665 (MuPP)

(Plastic Metric Quad Flat Package) ‘ia 4 Op] |_ | 0.882035 os i| os" | __ soz mABDIC 44x (82) —~|_ apa pcEDsax we (6]0.2/A-B/D]H) 4x { nogantanog 1 We ea | 447 /TUMMOOee { Index Marking 1 O.8x45 * 1) Doss not Include plastic or metal protrusioh of 0.25 max. per side BY a Gg Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. SMD = Surface Mounted Device Dimensions in mm Semiconductor Group 135 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Package Outlines

9.3 PEB 4165 (AHV-SLIC)

_.__sdisiwiaéicca gat] mes wo io Ett [ose +069) e104) 096°" 2-10) 20x ~l 103 #08 20 tt 12.8 02° Index Marking 1) Does not Include plastic or metal protrusion of 0.16 max. par skis

2 Does not Include dambar protrusion

a G Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. Semiconductor Group 136 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Appendix

10 Appendix

10.1 IOM®-2 Interface Monitor Transfer Protocol

The monitor channel is used for the transfer of maintenance information between two functional blocks. Using two monitor control bits (MR and MX) per direction, the data are transferred in a complete handshake procedure. The MR and Mx bits in the fourth octet (C/I channel) of the IOM-2 frame are used for the handshake procedure of the monitor channel The monitor channel transmission operates on a pseudo-asynchronous basis: — Data transfer (bits) on the bus is synchronized to Frame Sync FSC — Data flow (bytes) are asynchronously controlled by the handshake procedure. For example: Data is placed onto the DD-Monitor-Channel by the Monitor-transmitter of the master device (DD-MX-Bit is activated i.e. set to ‘0’). This data transfer will be repeated within each frame (125 us rate) until it is acknowledged by the MuPP Monitor-receiver by setting the DU-MR-bit to ‘0’, which is checked by the Monitor-transmitter of the master device. Thus, the data rate is not 8-kbytes/s. MX MX Trenemniter [e—_—_| | el Recetvo Transmitter Receiver MR MR DD DU MR MR Monitor- Monitor- Receiver Transmitter MX MX Master Device MuPP 1OM_MON.DRW, 04.11.92 Figure 42 Semiconductor Group 137 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Appendix Monitor handshake procedure The monitor channel works in 3 states — idle state: A pair of inactive (set to ‘1’) MR- and MX-bits during two or more consecutive frames: End of Message (EOM) — sending state: MX-bit is activated (set to ‘0’) by the Monitor-transmitter, together with data-bytes (can be changed) on the Monitor-channel — acknowledging: MR-bit is set to active (set to ‘0’) by the Monitor-receiver, together with a data-byte remaining in the Monitor-channel. A start of transmission is initiated by a Monitor-transmitter in sending out an active MxX-bit together with the first byte of data (the address of the receiver) to be transmitted in the Monitor-channel. This state remains until the addressed Monitor-Receiver acknowledges the received data by sending out an active MR-bit, which means that the data-transmission is repeated each 125 us frame (minimum is one repetition). During this time the Monitor-transmitter evaluates the MR-bit. Flow control, means in the form of transmission delay, can only take place when the transmitters MX and the receivers MR bit are in active state. Since the receiver is able to receive the monitor data at least twice (in two consecutive frames), it is able to check for data errors. If two different bytes are received the receiver will wait for the receipt of two identical successive bytes (last look function). A collision resolution mechanism (check if another device is trying to send data during the same time) is implemented in the transmitter. This is done by looking for the inactive (‘1’) phase of the MX-bit and making a per bit collision check on the transmitted monitor data (check if transmitted ‘1’s are on DU/DD-line; DU/DD-line are open-drain lines). Any abort leads to a reset of the MuPP command stack, the device is ready to receive new commands. To obtain a maximum speed data transfer, the transmitter anticipates the falling edge of the receivers acknowledgment. Due to the inherent programming structure, duplex operation is not possible. It is not allowed to send any data to the MuPP, while transmission is active. Semiconductor Group 138 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Appendix MR + MXR ’ ; \\ / . MXR initial ide |_| MR°MXR { wait | 7 abort) Sate MX=1 MxX=1 J) MR° MXR | MX-1 /s MR ° RQT MR an an (1 byte | MR ° RQT com \\MR \\ MXe0 MX=1 MR ° RQT ‘ nMoyte ack) MR Me MR MR ° RQT [ waittorack | MR ° RQT eco @ CLS/ABT . : any state IOM_TRAN.DRW, 04.11.92 Figure 43 State Diagram of the MuPP Monitor Transmitter MR ... MR - bit Received on DD - line MX ... MX - bit Calculated and expected on DU - line MXR... MX- bit Sampled on DU - line CLS ... Collision within the monitor data byte on DU - line RQT... Request for transmission from internal source ABT... Abort request/indication Semiconductor Group 139 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Appendix ‘idle ani wR rN \\ MX ° LL

1 MX Sate

byte rec. | MX abort | MRO an Y \\ \\ MX ABT MX Stato 1 MX brisvadd MX°LL ~ wart ) MX ° LL — ee > \\ MX x \\ = \\ MX ° LL 1 MX . _» ; Mx —_/new byte ° ( nM™oyte rec. MX° LL | waittor | MX \\ MBET pet / \\ MRC IOM_REC.DRW, 04.11.92 Figure 44 State Diagram of the MuPP Monitor Receiver MR ... MR - bit Calculated and transmitted on DU - line MX ... MX - bit Received data downstream (DD - line) LL... Last lock of monitor byte received on DD - line ABT... Abort indication to internal source Semiconductor Group 140 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Appendix Monitor Channel Data Structure The monitor channel is used for the transfer of maintenance information between two functional blocks. By use of two monitor control bits (MR and MX) per direction, the data are transferred in a complete handshake procedure. Address Byte Messages to and from the MuPP are started with the following byte: Bit 7 6 5 4 3 2 1 0 pt foe }oftototofots | Thus providing information for up to 16 analog lines, the MuPP is one device for up to 16 IOM-2 time slots. Monitor data for the analog channels is selected by the MuPP specific commands (SOP, XOP, TOP or COP) following.

10.2 Channel Identification Command (CIC)

In order to unambiguously identify different devices by software, a two Byte identification command is defined for analog lines IOM-2 devices. A device requesting the identification of the MuPP will send the following 2 byte code: Each device will then respond with its specific identification code. For the MuPP this two byte identification code is: Pr fofoftot}ofofoti| CONF an optional 4-bit code indicating the specific hardware environment. A typical application of the CONF code is the differentiation of various types of line circuits that use the same MuSLIC hardware within the same system. For the realization of the Channel Identification Commands on the line card, it needs of a shift register, to transfer special line card design informations up to 2 x 15 bytes into the monitor channel of the IOM-2 interface. Semiconductor Group 141 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Appendix There are two different solutions of the CIC for the MuPP to identify the version of the line card. Solution 1: (‘Normal’ Channel Identification Command) The input of the 4 pin interface (IDO ... |D3) is transferred to the 4 bit CONF information using the following truth-table (binary coded): Table 21 MuPP Ports CONF-inf. ov lov [sv jov__|oot0 ov Iv isv—isv ion av fev _fev fav [row 3V sv jov_jov_|t100 This is a 14 possible individual line card design information or an address pointer for the system to get more basic information. The information is read through the IOM-2 monitor channel with the CIC command. Semiconductor Group 142 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Appendix Solution 2 (Extended Channel Identification Command): The second realization step is that the combination of ports (ID1, ID2, ID3 = +3 V) changes the input port IDO to a shift register input. Table 22 MuPP Ports CONF-inf. An external shift register on the line card transmits up to 2 x 15 bytes of special HW + FW line card design information. The information is read through the |OM-2 monitor channel with the XOP Command for XR7 or XR8. The CONF code is ‘111x’ by this extended identification. The first schematic gives an overview of the different timings for the extended channel identification. Semiconductor Group 143 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Appendix spe Dota A ocx [fl HATTA : PO cn__ TTT TT TEEEETTTITUTITTED EET ET Po Ts vp Bx. Chane! Identtcaton Byte ecice RW DetailA DCL | f | f | | (4096kHz) ID CIBx ... Channel Identification Byte Figure 45 General Timing Semiconductor Group 144 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Appendix Expected Output of the ASIC Which Sends the Channel Identification: The MuPP sends the Extended Channel Identification in the Monitor Channel of that time slot in which the XOP Command was sent. If — for example — the MuPP uses the time slot 6, the Monitor Channel of TS6 looks like the following (for all other time slots equivalent). og__ PEPE EP PEPEEE-EEPPPEE EP PEPEEEe) —PEEEEE}--EPEEEE EE a a a Figure 46 Expected Input Timing and IOM-2 Interface Timing and Switching characteristic: To be defined Semiconductor Group 145 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Appendix

10.3 List of Abbreviations

ADC Analog Digital Converter AGDCR Attenuation DC Receive AGDCX Attenuation DC Transmit AGR Attenuation Receive AGX Attenuation Transmit AGTTX Attenuation Teletax AR Attenuation Receive AX Attenuation Transmit BB Boosted Battery BiCMOS Bipolar Complementary Metal Oxid Semiconductor BP Band Pass C/l-DD Channel Identification-Data Downstream C/Il-DU Channel Identification-Data Upstream C1,2 Digital Interface between QAP and AHV-SLIC CHOP Chopper (see SCR8_6) CMP Compander CODEC Coder Decoder COMP Comparator (Testloops, Levelmetering) COP Coefficient Operation CRAM Coefficient RAM DAC Digital Analog Converter DAC-HOLD DC DAC Hold (Testloop TVP) DTAG Deutsche Telecom AG DCCHAR DC Characteristic block DCL Data Clock DD Data Downstream DHP_R Disable Receive Highpass (SCR5_7) DHP_X Disable Transmit Highpass (SCR1_1) DSP Digital Signal Processor DU Data Upstream DUP Data Upstream Persistency Counter DUPGNK Data Upstream Persistency Counter for GNK EXP Expander Semiconductor Group 146 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Appendix FRR Frequency Response Receive Filter FRX Frequency Response Transmit Filter FSC Frame Sync. GNDIT Analog Ground GNK Ground Key AHV-SLIC Advanced High Voltage Subscriber Line Interface Circuit ih Fixed Input Pin ID External Identification IL Longitudinal Current Input IMI Impedance Matching Filter (programmable) IMFIX Impedance Matching Filter (fixed)

10 User Programmable I/O Pin

IOM 2-Interface ISDN Oriented Modular Interface ISDN Integrated Service Digital Network IT Transversal Current Input (for AC and DC) ITAC. Transversal Current Input (for AC) LPO3 Low Pass 0.3 Hz LPS Low Pass 5 Hz LSSGR Local area transport access Switching System Generic Requirements MEAN VAL. Mean Value (Testloops, Levelmetering) MR Monitor Receive MX Monitor Transmit MuPP Multi Channel Processor for POTS MuSLIC Multi Channel Subscriber Line Interface Circuit MuSLICOS MuSLIC Oriented Software O1 Fixed Output Pin PCM Pulse Code Modulation PDen Power Denial PDN Power Down PDN PDN Pin (Sets the HV SLIC to Power Denial) POFI Post Filter PREFI Antialiasing Pre Filter Semiconductor Group 147 04.97

SIEMENS PEB 3465, PEB 31665, PEB 4165 Appendix QAP Quad Analog POTS RB Ring Burst RECT Rectifier (Testloops, Levelmetering) RES Reset REXT External Ring Sync. Input RFIX Receive Filter (fixed) RNG Ring Generator RREF External Resistor to GNDA SCR Status Configuration Register SLIC Subscriber Line Interface Circuit SLMA Subscriber Loop Marging SLXC Summary Line Card Outputs SOP Status Operation STCR Status Test Configuration Register TCR Transfer Configuration Register TST1 Test Pin TG Tone Generator TH Transhybrid Balancing THFIX Transhybrid Balancing Filter (fixed) THRESH Threshold (Testloops, Levelmetering) TOP Transfer Operation TS Time Slot TS 0-2 Time Slot selection Pin TTX Teletax TTXFI Teletax Adaptation TTXGEN Teletax Generator VBIM Battery Image Input VB/2 Half Battery Voltage Input X Transmit Filter (programmable) XFIX Transmit Filter (fixed) Semiconductor Group 148 04.97