PEB3081

PEB3081 INFINEON | Alldatasheet

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Never stop thinking. Data Sheet, DS 1, Feb. 2003 Wired Communications SBCX-X S/T Bus Interface Circuit Extended PEB 3081, Version 1.4

Published by Infineon Technologies AG, St.-Martin-Strasse 53,

81669 München, Germany

© Infineon Technologies AG 2003. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (www.infineon.com). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. ABM®, ACE ®, AOP ®, ARCOFI ®, ASM ®, ASP ®, DigiTape ®, DuSLIC ®, EPIC ®, ELIC ®, FALC®, GEMINAX ®, IDEC ®, INCA ®, IOM ®, IPAT ®-2, ISAC ®, ITAC ®, IWE ®, IWORX ®, MUSAC®, MuSLIC ®, OCTAT ®, OptiPort ®, POTSWIRE ®, QUAT ®, QuadFALC ®, SCOUT®, SICAT®, SICOFI®, SIDEC ®, SLICOFI ®, SMINT ®, SOCRATES®, VINETIC ®, 10BaseV®, 10BaseVX ® are registered trademarks of Infineon Technologies AG. 10BaseS™, EasyPort™, VDSLite™ are trademarks of Infineon Technologies AG. Microsoft® is a registered trademark of Microsoft Corporation. Linux ® is a registered trademark of Linus Torvalds. The information in this document is subject to change without notice.

Revision History: 2003-02-04 DS 1 Previous Version: Data Sheet, DS1, V1.3, 2000-07-21 Page Subjects (major changes since last revision) Chapter 1 Comparison SBCX/SBCX-X Chapter 3.3.6.2 S- Transceiver Synchronization New Chapter 3.3.10 Test Functions extended Chapter 3.7.1.1 CDA Handler Description extended Chapter 3.7.5.1 TIC Bus Access Control: Note added Chapter 5.6 IOM-2 Interface Timing: Explanation added Chapter 5.9 S-Transceiver Chapter 5.10 Recommended Transformer Specification: Changed Chapter 5.11 Line Overload Protection added Chapter 5.12 EMC/ESD added

The S/T Bus Interface Circuit Extended (SBCX-X) implements the four-wire S/T interface used to link voice/data ISDN terminals, network terminators and PBX trunk lines to a central office. It is based on the SBCX PEB 2081, and provides enhanced features and functionality. The SBCX-X provides the electrical and functional link between the analog S/T interface (compliant to the ITU recommendation I.430) and the IOM-2 interface. It provides an S/T interface operating in TE, LT-T, LT-S, NT and intelligent NT modes, a serial control interface (SCI) for host programming, three general purpose I/O pins and one LED output which is capable to indicate the activation status of the S-interface automatically or can be programmed by the host. The SBCX-X is produced in advanced CMOS technology. Table 1 Comparison of the SBCX-X with the Previous Version SBCX SBCX-X PEB 3081 SBCX PEB 2081 Operating modes TE, LT-T, LT-S, NT, Int. NT TE, LT-T, LT-S, NT Supply voltage 3.3 V /g177 5% 5 V /g177 5% Technology CMOS CMOS Package P-MQFP-44 / P-TQFP-48 P-LCC-28 / P-DIP-28 Transceiver Transformer ratio for the transmitter receiver 1:1 1:1 2:1 2:1 Test Functions - Analog loop (LP_A - bit EXLP - bit, ARL) - Analog loop (ARL) Microcontroller Interface Serial interface (SCI) Not provided Host programming SCI or MON channel (MONITOR slave mode) MON channel (MONITOR slave mode) Command structure of the register access Header/address/data Address/data Crystal 7.68 MHz 7.68 MHz Buffered 7.68 MHz output Provided Not provided

All timeslots; various possibilities of data access Not provided Data control and manipulation Various possibilities of data control and data manipulation (enable/disable, shifting, looping, switching) Shifting B-channel to channel 0 and direction control Auxiliary Interface AUX0-2 (general purpose I/Os) MAI0-7 (general purpose I/Os and several mode dependent functions) IOM channel select (LT modes) Channel select pins multiplexed on AUX0-2 X0-2 LED pin ACL (host controlled or automatic indication of layer 1 activated state) Not provided Output pin for D-channel active indication Provided Not provided Control input pin for D-channel inhibit Provided Not provided Stop/Go bit output pin Provided Provided IOM-2 IOM-2 Interface Double clock (DCL), bit clock (BCL), serial data strobe 1 (SDS1) serial data strobe 2 (SDS2) Double clock (DCL), bit clock (BCL) Monitor channel programming Provided Provided (MON0 or 1) C/I channels CI0 (4 bit), CI1 (4/6 bit) CI0 (4 bit), CI1 (6 bit) Table 1 Comparison of the SBCX-X with the Previous Version SBCX (cont’d) SBCX-X PEB 3081 SBCX PEB 2081

Layer 1 state machine With changes for correspondence with the actual ITU specification Layer 1 state machine in software Possible Not possible Reset Signals RES input signal RSTO output signal RST input signal Reset Sources RES Input Watchdog C/I Code Change EAW Pin Software Reset RST Input C/I Code Change Interrupt Output Signals INT low active (open drain) by default, reprogrammable to high active (push-pull) Not provided Pin SCLK 1.536 MHz 512 kHz Table 1 Comparison of the SBCX-X with the Previous Version SBCX (cont’d) SBCX-X PEB 3081 SBCX PEB 2081

S/T Bus Interface Circuit Extended SBCX-X PEB 3081 Version 1.4 P-MQFP-44-2 P-MQFP-44 P-TQFP-48

1.1 Features

 Full duplex 2B + D S/T interface transceiver according to ITU-T I.430  Successor of SBCX PEB 2081 in 3.3 V technology  Conversion of the frame structure between the S/T-interface and IOM-2  IOM-2 interface supporting TE, LT-T, LT-S, NT and intelligent NT modes  Single and double clocks on IOM-2  Two serial data strobe signals  Serial control interface (SCI)  Microcontroller access to all IOM-2 timeslots  Monitor channel handler (master/slave)  IOM-2 MONITOR and C/I-channel protocol to control peripheral devices  Receive timing recovery  D-channel access control  Activation and deactivation procedures with automatic activation from power down state  Access to S and Q bits of S/T-interface  Adaptively switched receive thresholds  3 general purpose I/O pins multiplexed with channel select pins  Three pins for D-channel active indication, Stop/Go bit output and E-bit control on S  One programmable timer  Watchdog timer  Software Reset  One LED pin automatically indicating layer 1 activated state  Test loops  Sophisticated power management for restricted power mode

 Power supply 3.3 V  3.3 V output drivers, inputs are 5 V safe  Advanced CMOS technology

1.2 Logic Symbol

The logic symbol gives an overview of the SBCX-X functions. It must be noted that not all functions are available simultaneously, but depend on the selected mode. Pins which are marked with a “ * “ are multiplexed and not available in all modes. Figure 1 Logic Symbol of the SBCX-X CS RES INT DU SCL SDR SDX RSTO XTAL2 XTAL1

7.68 MHz output

7.68 MHz ± 100ppm

+3.3V 0V IOM-2 Interface Host Interface (SCI) 3081_17 TP SDS1/2 LED OutputIOM channel select General purpose I/O Auxiliary Interface MODE0 MODE1 / EAW Mode Setting DCI DCA SGO D-channel Active Indication D-channel Inhibit S/G Bit Output

1.3 Typical Applications

The SBCX-X is designed for the user area of the ISDN basic access. By programming the corresponding operating mode it may be used at both ends of these interfaces. Figure 2 illustrates the general application fields of the SBCX-X:  ISDN terminals (TE mode)  ISDN network termination (NT) for a link between the S/T interface and the U interface  ISDN subscriber line termination (LT-S)  ISDN trunk line termination (LT-T), i.e. PBX connection to central office Figure 2 Applications of the SBCX-X ITS04492 NT 2 1 NT NT 1(1)TE T SU LT-S LT-T NT NT TE(8) TE(8) TE(1) LT-S S Network Terminator (NT) = SBCX-X

2 Pin Configuration

Figure 3 Pin Configuration of the SBCX-X (P-MQFP-44) P-MQFP-44 SR2 SBCX-X PEB 3081 12345 6 789 1 0 1 1 33 32 31 30 29 28 27 26 25 24 23 SR1 VDDA VSSA SX2 SX1 VSS XTAL2 XTAL1 VSS DCA VDD INT n.c. CS TP RES RSTO VSS DU DD FSC DCL VSS VSS VDD MODE0 MODE1 / EAW ACL 3081_02.vsd VDD SCL SDR VDD VSS SDS2 C768 SGO DCI AUX1 AUX0 SDS1 SDX AUX2BCL / SCLK

Figure 4 Pin Configuration of the SBCX-X (P-TQFP-48) P-TQFP-48 SR2 SBCX-X PEB 3081 12345 6 789 1 0 1 1 1 2 36 35 34 33 32 31 30 29 28 27 26 25 SR1 VDDA VSSA SX2 SX1 n.c. VSS XTAL2 XTAL1 DCA VSS VDD INT n.c. CS TP RES RSTO VSS BCL / SCLK DU DD FSC DCL VSS VSS VDD MODE0 MODE1 / EAW ACL n.c. 3081_01.vsd VDD n.c. SCL SDR SDX n.c. VDD VSS SDS2 C768 SGO DCI AUX2 AUX1 AUX0 SDS1

Table 2 SBCX-X Pin Definitions and Functions Pin No. Symbol Input (I) Output (O) Open Drain (OD) Function MQFP- TQFP- Host Interface 91 0 S C L I SCL - Serial Clock Clock signal of the SCI interface if a serial interface is selected. 10 11 SDR I SDR - Serial Data Receive Receive data line of the SCI interface if a serial interface is selected. 11 12 SDX OD SDX - Serial Data Transmit Transmit data line of the SCI interface if a serial interface is selected.

33 C S I Chip Select

A low level indicates a microcontroller access to the SBCX-X. 1 1 INT O (OD) Interrupt Request INT becomes active (low) if the SBCX-X requests an interrupt (open drain characteristic). The polarity can be reprogrammed to high active with push-pull characteristic.

55 R E S I Reset

A LOW on this input forces the SBCX-X into a reset state. IOM-2 Interface 37 40 FSC I/O Frame Sync 8-kHz frame synchronization signal. 38 41 DCL I/O Data Clock IOM-2 interface clock signal (double clock, e.g. 1.536 MHz in TE mode).

TE-Mode: Bit clock output, identical to IOM-2 data rate (DCL/2). LT-T Mode:

1.536 MHz output synchronous to

S-interface. NT / LT-S Mode: Bit clock output derived from the DCL input clock divided by 2. 36 39 DD I/O (OD) Data Downstream IOM-2 data signal in downstream direction. 35 38 DU I/O (OD) Data Upstream IOM-2 data signal in upstream direction. 19 21 SDS1 O Serial Data Strobe 1 Programmable strobe signal for time slot and/or D-channel indication on IOM-2. 18 20 SDS2 O Serial Data Strobe 2 Programmable strobe signal for time slot and/or D-channel indication on IOM-2. Miscellaneous SX1 SX2 O O S-Bus Transmitter Output (positive) S-Bus Transmitter Output (negative) SR1 SR2 I I S-Bus Receiver Input S-Bus Receiver Input XTAL1 XTAL2 I O Crystal 1 Connection for a crystal or used as external clock input. 7.68 MHz clock or crystal required. Crystal 2 Connection for a crystal. Not connected if an external clock is supplied to XTAL1 Table 2 SBCX-X Pin Definitions and Functions (cont’d) Pin No. Symbol Input (I) Output (O) Open Drain (OD) Function MQFP- TQFP-

I/O (OD) I/O (OD) I/O (OD) TE-Mode: Auxiliary Port 0 - 2 (input/output) These pins are individually programmable as general input/output. The state of the pin can be read from (input) / written to (output) a register. LT-T/LT-S/NT Mode: CH0-2 - IOM-2 Channel Select (input) These pins select one of eight channels on the IOM-2 interface. 42 45 MODE0 I Mode 0 Select A LOW selects TE-mode and a HIGH selects LT-T / LT-S mode (see MODE1/ EAW 43 46 MODE1 EAW I I The pin function depends on the setting of MODE0. If MODE0=1: Mode 1 Select A LOW selects LT-T mode and a HIGH selects LT-S mode. If MODE0=0: External Awake If a falling edge on this input is detected, the SBCX-X generates an interrupt and, if enabled, a reset pulse.

66 R S T O O D Reset Output

Low active reset output, either from a watchdog timeout or programmed by the host. 17 19 C768 O Clock Output A 7.68 MHz clock is output to support other devices. This clock is not synchronous to the S interface. 14 16 DCA O DCA - D-Channel Active Indication This pin provides an output of the D-channel bits on the S-bus receive line. Table 2 SBCX-X Pin Definitions and Functions (cont’d) Pin No. Symbol Input (I) Output (O) Open Drain (OD) Function MQFP- TQFP-

15 17 DCI I DCI - D-Channel Inhibit If this bit is set to ’1’ the E-bits are inverted, i.e. the D-channel is blocked (only in NT/LT-S mode). This pin has the same function as the D-channel inhibit bit (see TR_MODE.DCH_INH). 16 18 SGO O SGO - Stop/Go Bit Output A S/G bit output with programmable polarity and length (TR_CONF2 register) is provided. 44 47 ACL O Activation LED This pin can either function as a programmable output or it can automatically indicate the activated state of the S interface by a logic ’0’. An LED with pre-resistance may directly be connected to ACL

44 T PI Test Pin

Must be connected to VSS. 2 2, 9, 15, 30, 48 n.c. Not Connected Power Supply 8, 13, 23, 8, 14, 25, 44 VDD – Digital Power Supply Voltage (3.3 V /g1775% ) 31 34 VDDA – Analog Power Supply Voltage (3.3 V /g1775% ) 7, 12, 24, 27, 39, 7, 13, 26, 29, 42, 43 VSS – Digital Ground (0 V) 30 33 VSSA – Analog Ground (0 V) Table 2 SBCX-X Pin Definitions and Functions (cont’d) Pin No. Symbol Input (I) Output (O) Open Drain (OD) Function MQFP- TQFP-

Description of Functional Blocks Data Sheet 23 2003-02-04

3 Description of Functional Blocks

3.1 General Functions a nd Device Architecture

Figure 5 shows the architecture of the SBCX-X containing the following functions:  S/T-interface transceiver supporting TE, LT-T, LT-S, NT and intelligent NT modes  Serial Control Interface (SCI)  IOM-2 interface for terminal, linecard and NT applications, with single/double clock  Two serial data strobe signals  IOM handler with controller data access regi sters (CDA) allows flexible access to IOM timeslots for reading/writing, looping and shifting data  Synchronous transfer interrupts (STI) allow controlled access to IOM timeslots  MONITOR channel handler on IOM-2 for master mode, slave mode or data exchange  C/I-Channel handler  D-channel access mechanism  3-pin auxiliary port for general purpose I/O pins or channel select pins  LED connected to pin ACL indicates S-interface activation status automatically or can be controlled by the host  Output for D-channel active indication (output of received D-bits on S)  Stop/Go bit output with programmable polarity and length  D-channel inhibit input pin to control inversion of E-bits on S to block other terminals  Level detect circuit on the S interface reduces power consumption in power down mode  Timer for periodic or single interrupts  Clock and timing generation  Digital PLL to synchronize the transceiver to the S/T interface  Buffered 7.68 MHz oscillator clock output allows connection of further devices and saves another crystal on the system board  Reset generation (watchdog timer)

Description of Functional Blocks Data Sheet 24 2003-02-04 Figure 5 Functional Block Diagram of the SBCX-X Reset Interrupt generation IOM-2 Interface IOM-2 Handler S Transceiver Serial Host Interface (SCI) OSC DPLL Host Peripheral Devices 3081_18 Auxiliary Interface General Purpose I/Os C/ITICMONITOR Handler

Description of Functional Blocks Data Sheet 25 2003-02-04

3.2 Microcontroller Interface

The SBCX-X supports a serial micrcontroller interface. For applications where no controller is connected to the SBCX-X programming is done via the IOM-2 MONITOR channel from a master device. In such applications the SBCX-X operates in the IOM-2 slave mode (refer to the corresponding chapter of the IOM-2 MONITOR handler). This mode is suitable for control functions (e.g. programming registers of the S/T transceiver), but the bandwidth is not sufficient to transfer B- and D-channel data. The interface selection is done by pinstrapping of the chip select signal CS (see Table 3). The selection pins are evaluated when the reset input RES is active. For the pin levels stated in the table the following is defined: ’High’: dynamic pin; value must be ’High’ only during reset VSS: static pin; pin must statically be strapped to ’Low’ level The interfaces contain all circuitry necessary for the access to programmable registers. The mapping of all these registers can be found in Chapter 4. The microcontroller interface also provides an interrupt request at pin INT which is low active by default but can be reprogrammed to high active, a reset input pin RES and a reset output pin RSTO. The interrupt request pin INT becomes active if the SBCX-X requests an interrupt and this can occur at any time. Table 3 Host Interface Selection CS Interface Mode ’High’ Serial Control Interface (SCI) V SS IOM-2 MONITOR Channel (Slave Mode)

Description of Functional Blocks Data Sheet 26 2003-02-04

3.2.1 Serial Control Interface (SCI)

The serial control interface (SCI) is compatible to the SPI interface of Motorola or Siemens C510 family of microcontrollers. The SCI consists of 4 lines: SCL, SDX, SDR and CS . Data is transferred via the lines SDR and SDX at the rate given by SCL. The falling edge of CS indicates the beginning of a serial access to the registers. The SBCX-X latches incoming data at the rising edge of SCL and shifts out at the falling edge of SCL. Each access must be terminated by a rising edge of CS . Data is transferred in groups of 8 bits with the MSB first. Figure 6 shows the timing of a one byte read/write access via the serial control interface. Figure 6 Serial Control Interface Timing 7 654321076543210 Header Address CS SCL SDR SDX 7 654321 CS SCL SDR SDX 76543210 Data Data '0' write Header Address 7 654321 0 7 654321 0 '1' read 21150_19 Write Access Read Access

Description of Functional Blocks Data Sheet 27 2003-02-04

3.2.2 Programming Sequences

The basic structure of a read/write access to the SBCX-X registers via the serial control interface is shown in Figure 7. Figure 7 Serial Control Interface Timing A new programming sequence starts with the transfer of a header byte. The header byte specifies different programming sequences allowing a flexible and optimized access to the individual functional blocks of the SBCX-X. The possible sequences for access to the complete address range 00H-7FH are listed in Table 4 and described after that. Note: In order to access the address range 00H-7FH bit 2 of the header byte must be set to ’0’ (header bytes 40H, 48H, 43H, 41H, 49H), and for the addresses 80H-FFH bit 2 must be set to ’1’ (header bytes 44H, 4CH, 47H, 45H, 4DH). Table 4 Header Byte Code Header Byte Sequence Sequence Type 40H/44H Adr-Data-Adr-Data Alternating Read/Write (non-interleaved) 48H/4CH Alternating Read/Write (interleaved) 43H/47H Adr-Data-Data-Data Read-only/Write-only (constant address) 41H/45H Read and following Write-only (non-interleaved) 49H/4DH Read and following Write-only (interleaved) SDR write sequence: read sequence: SDR 7 0 76 07 0 write data address read data write read 7 0 76 07 0 header byte 2 byte 3 header byte 2 byte 3 SDX address

Description of Functional Blocks Data Sheet 28 2003-02-04 Header 40H: Non-interleaved A-D-A-D Sequences The non-interleaved A-D-A-D sequence gives direct read/write access to the complete address range and can have any length. In this mode SDX and SDR can be connected together allowing data transmission on one line. Example for a read/write access with header 40H: Header 48H: Interleaved A-D-A-D Sequences The interleaved A-D-A-D sequence gives direct read/write access to the complete address range and can have any length. This mode allows a time optimized access to the registers by interleaving the data on SDX and SDR (SDR and SDX must not be connected together). Example for a read/write access with header 48 Header 43H: Read-/Write- only A-D-D-D Sequence (Constant Address) This mode can be used for a fast access to the HDLC FIFO data. Any address (rdadr, wradr) in the range 00 H-1FH and 6A H/7AH gives access to the current FIFO location selected by an internal pointer which is automatically incremented with every data byte following the first address byte. The sequence can have any length and is terminated by the rising edge of CS. Example for a write access with header 43H: Example for a read access with header 43H: SDR header wradr wrdata rdadr rdadr wradr wrdata SDX rddata rdata SDR header wradr wrdata rdadr rdadr wradr wrdata SDX rddata rddata SDR header wradr wrdata (wradr) wrdata (wradr) wrdata (wradr) wrdata (wradr) wrdata (wradr) wrdata (wradr) wrdata (wradr) SDX SDR header rdadr SDX rddata (rdadr) rddata (rdadr) rddata (rdadr) rddata (rdadr) rddata (rdadr) rddata (rdadr) rddata (rdadr)

Description of Functional Blocks Data Sheet 29 2003-02-04 Header 41H: Non-interleaved A-D-D-D Sequence This sequence allows in front of the A-D-D-D write access a non-interleaved A-D-A-D read access. This mode is useful for reading status information before writing to the HDLC XFIFO. The termination condition of the read access is the reception of the wradr. The sequence can have any length and is terminated by the rising edge of CS. Example for a read/write access with header 41H: Header 49H: Interleaved A-D-D-D Sequence This sequence allows in front of the A-D-D-D write access an interleaved A-D-A-D read access. This mode is useful for reading status information before writing to the HDLC XFIFO. The termination condition of the read access is the reception of the wradr. The sequence can have any length and is terminated by the rising edge of the CS line. Example for a read/write access with header 49H:

3.2.3 Interrupt Structure

Special events in the device are indicated by means of a single interrupt output, which requests the host to read status information from the device or transfer data from/to the device. Since only one interrupt request pin (INT) is provided, the cause of an interrupt must be determined by the host reading the interrupt status registers of the device. The structure of the interrupt status registers is shown in Figure 8. SDR header rdadr rdadr wradr wrdata (wradr) wrdata (wradr) wrdata (wradr) SDX rddata rddata SDR header rdadr rdadr wradr wrdata (wradr) wrdata (wradr) wrdata (wradr) SDX rddata rddata

Description of Functional Blocks Data Sheet 30 2003-02-04 Figure 8 Interrupt Status and Mask Registers All five interrupt bits in the ISTA register point at interrupt sources in the Monitor handler (MOS), C/I handler (CIC), the transceiver (TRAN), the synchronous transfer (ST) and the auxiliary interrupts (AUXI). All these interrupt sources are described in the corresponding chapters. After the device has requested an interrupt activating the interrupt pin (INT ), the host must read first the device interrupt status register (ISTA) in the associated interrupt service routine. The interrupt pin of the device remains active until all interrupt sources are cleared by reading the corresponding interrupt register. Therefore it is possible that the interrupt pin is still active when the interrupt service routine is finished. Each interrupt indication of the interrupt status registers can selectively be masked by setting the respective bit in the MASK register. For some interrupt controllers or hosts it might be necessary to generate a new edge on the interrupt line to recognize pending interrupts. This can be done by masking all interrupts at the end of the interrupt service routine (writing FFH into the MASK register) and write back the old mask to the MASK register. MOS TRAN AUX CIC ST MOS TRAN AUX CIC ST STI10 STI11 STI20 STI21 STOV10 STOV11 STOV20 STOV21 STI10 STI11 STI20 STI21 STOV10 STOV11 STOV20 STOV21 STI ACK10 ACK11 ACK20 ACK21 ASTIMSTI MIE MRE MAB MDA MER MDR SQW SQC RIC LD MASKTR ISTATR SQW SQC RIC LD MASK ISTA 3081_16.vsd Interrupt MOCR MOSR TIN WOV AUXM AUXI TIN WOV EAW EAW CI1E CIC1 CIC0 CIX1 CIR0

Description of Functional Blocks Data Sheet 31 2003-02-04

3.2.4 Reset Generation

Figure 9 shows the organization of the reset generation of the device. Figure 9 Reset Generation Reset Source Selection The internal reset sources C/I code change, EAW and Watchdog can be output at the low active reset pin RSTO . The selection of these reset sources can be done with the RSS2,1 bits in the MODE1 register according Table 5. The setting RSS2,1 = ’01’ is reserved for further use. In this case no reset except software reset (SRES.RSTO) is output on RSTO . The internal reset sources set the MODE1 register to its reset value. C/I Code Change (Exchange Awake) EAW (Subscriber Awake) Watchdog /g179 1 125µs /g163 t /g163 250µs 125µs /g163 t /g163 250µs Software Reset Register (SRES) Reset Functional Block Transceiver, C/I (22H-3FH) IOM-2 (40H-5BH) MON-channel (5CH-5FH) Reset MODE1 Register Internal Reset of all Registers /g179 1 RSS1 RSS2,1 '0' '1' '1x' '00' RSS2,1 '01' ' 01 ' Pin RSTO Pin RES 3081_21 (reserved) /g179 1 125µs /g163 t /g163 250µs 125µs /g163 t /g163 250µs General Config (60H-6FH)

Description of Functional Blocks Data Sheet 32 2003-02-04  C/I Code Change (Exchange Awake) A change in the downstream C/I channel (C/I0) generates an external reset pulse of 125 µs /g163 t /g163 250 µs.  EAW (Subscriber Awake) A low level on the EAW input starts the oscillator from the power down state and generates a reset pulse of 125 µs /g163 t /g163 250 µs.  Watchdog Timer After the selection of the watchdog timer (RSS = ’11’) an internal timer is reset and started. During every time period of 128 ms the microcontroller has to program the WTC1- and WTC2 bits in the following sequence to reset and restart the watchdog timer: If not, the timer expires and a WOV-interrupt (ISTA Register) together with a reset pulse of 125 µs is generated. Deactivation of the watchdog timer is only possible with a hardware reset. External Reset Input At the RES input an external reset can be applied forcing the device in the reset state. This external reset signal is additionally fed to the RSTO output. The length of the reset signal is specified in Chapter 5.8. After an external reset from the RES pin all registers of the device are set to its reset values (see register description in Chapter 4). Software Reset Register (SRES) Every main functional block of the device can be reset separately by software setting the corresponding bit in the SRES register. A reset to external devices can also be controlled in this way. The reset state is activated by setting the corresponding bit to ’1’ and onchip Table 5 Reset Source Selection RSS2 Bit 1 RSS1 Bit 0 C/I Code Change EAW Watchdog Timer 0 0 -- -- -- 0 1 reserved 10 x x - - 1 1 -- -- x WTC1 WTC2

Description of Functional Blocks Data Sheet 33 2003-02-04 logic resets this bit again automatically after 4 BCL clock cycles. The address range of the registers which will be reset at each SRES bit is listed in Figure 9.

3.2.5 Timer Modes

The SBCX-X provides one timer which can be used for various purposes. It provides two modes (Table 6), a count down timer interrupt, i.e. an interrupt is generated only once after expiration of the selected period, and a periodic timer interrupt, which means an interrupt is generated continuously after every expiration of that period. When the programmed period has expired an interrupt is generated and indicated in the auxiliary interrupt status ISTA.AUX. The source of the interrupt can be read from AUXI.TIN and masked in AUXM. Figure 10 Timer Interrupt Status Registers Table 6 SBCX-X Timer Address Register Modes Period 65H TIMR Periodic 1 ... 63 ms Count Down 1 ... 63 ms ST MOS TRAN AUX Interrupt ISTAMASK MOS TRAN AUX ST WOV TIN WOV TIN AUXM AUXI EAWEAW CIC CIC

Description of Functional Blocks Data Sheet 34 2003-02-04 The host starts and stops the timer in TIMR.CNT (Figure 11). If TIMR.TMD=0 the timer is operating in count down mode, for TIMR.TMD=1 a periodic interrupt AUXI.TIN is generated. The timer length (for count down timer) or the timer period (for periodic timer), respectively, can be configured to a value between 1 - 63 ms (TIMR.CNT). Figure 11 Timer Register 3081_14CNT 7 6 5 4 3 2 1 0 65H Timer Count 0 : Timer off Timer Mode 0 : Count Down Timer 1 : Periodic Timer TIMR TMD 0

Description of Functional Blocks Data Sheet 35 2003-02-04

3.2.6 Activation Indication via Pin ACL

The activated state of the S-interface is directly indicated via pin ACL (Activation LED). An LED with pre-resistance may directly be connected to this pin and a low level is driven on ACL as soon as the layer 1 state machine reaches the activated state (see Figure 12). Figure 12 ACL Indication of Activated Layer 1 on TE Side By default (ACFG2.ACL=0) the state of layer 1 is indicated at pin ACL . If the automatic indication of the activated layer 1 is not required, the state on pin ACL can also be controlled by the host (see Figure 13). If ACFG2.ACL=1 the LED on pin ACL can be switched on (ACFG2.LED=1) and off (ACFG2.LED=0) by the host. Figure 13 ACL Configuration 3086_15 Layer 1 ACFG2:LED 0 : off 1 : on ACFG2:ACL '1' '0' ACL +3.3V S Interface

Description of Functional Blocks Data Sheet 36 2003-02-04

3.3 S/T-Interface

The layer-1 functions for the S/T interface of the SBCX-X are: – line transceiver functions for the S/T interface according to the electrical specifications of ITU-T I.430; – conversion of the frame structure between IOM-2 and S/T interface; – conversion from/to binary to/from pseudo-ternary code; – level detection; – receive timing recovery for point-to-point, passive bus and extended passive bus configuration; – S/T timing generation using IOM-2 timing synchronous to system, or vice versa; – D-channel access control and priority handling; – D-channel echo bit generation by handling of the global echo bit; – activation/deactivation procedures, triggered by primitives received over the IOM-2 interface or by INFOs received from the line; – execution of test loops. The wiring configurations in user premises, in which the SBCX-X can be used, are illustrated in Figure 14.

Description of Functional Blocks Data Sheet 37 2003-02-04 Figure 14 Wiring Configurations in User Premises 3081_20 SBCX-X TR TE TR LT-S /g163 1000 m 1) TR LT-T TR NT /g163 1000 m 1) Point-to-Point Configurations TR TR NT / LT-S /g163 100 m TR TE1 TR NT / LT-S /g163 10 m Extended Passive Bus TE8 /g163 25 m /g163 500 m .... TE1 /g163 10 m TE8 .... Short Passive Bus TR: Terminating Resistor 1) The maximum line attenuation tolerated by the SBCX-X is 7 dB at 96 kHz. SBCX-X SBCX-X SBCX-X SBCX-X SBCX-XSBCX-X SBCX-X SBCX-XSBCX-X

Description of Functional Blocks Data Sheet 38 2003-02-04

3.3.1 S/T-Interface Coding

Transmission over the S/T-interface is performed at a rate of 192 kbit/s. 144 kbit/s are used for user data (B1+B2+D), 48 kbit/s are used for framing and maintenance information. Line Coding The following figure illustrates the line code. A binary ONE is represented by no line signal. Binary ZEROs are coded with alternating positive and negative pulses with two exceptions: For the required frame structure a code violation is indicated by two consecutive pulses of the same polarity. These two pulses can be adjacent or separated by binary ONEs. In bus configurations a binary ZERO always overwrites a binary ONE. Figure 15 S/T-Interface Line Code Frame Structure Each S/T frame consists of 48 bits at a nominal bit rate of 192 kbit/s. For user data (B1+B2+D) the frame structure applies to a data rate of 144 kbit/s (see Figure 16). In the direction TE /g174NT the frame is transmitted with a two bit offset. For details on the framing rules please refer to ITU I.430 section 6.3. The following figure illustrates the standard frame structure for both directions (NT /g174 TE and TE /g174 NT) with all framing and maintenance bits. 011 code violation

Description of Functional Blocks Data Sheet 39 2003-02-04 Figure 16 Frame Structure at Reference Points S and T (ITU I.430) Note: The ITU I.430 standard specifies S1 - S5 for optional use. – F Framing Bit F = (0b) /g174 identifies new frame (always positive pulse, always code violation) – L. D.C. Balancing Bit L. = (0b) /g174 number of binary ZEROs sent after the last L. bit was odd – D D-Channel Data Bit Signaling data specified by user – E D-Channel Echo Bit E = D /g174 received E-bit is equal to transmitted D-bit –F A Auxiliary Framing Bit See section 6.3 in ITU I.430 –N N = – B1 B1-Channel Data Bit User data – B2 B2-Channel Data Bit User data – A Activation Bit A = (0b) /g174 INFO 2 transmitted A = (1b) /g174 INFO 4 transmitted – S S-Channel Data Bit S 1 channel data (see note below) – M Multiframing Bit M = (1b) /g174 Start of new multiframe FA

Description of Functional Blocks Data Sheet 40 2003-02-04

3.3.2 S/T-Interface Multiframing

According to ITU recommendation I.430 a multiframe provides extra layer 1 capacity in the TE-to-NT direction by using an extra channel between the TE and NT (Q-channel). The Q bits are defined to be the bits in the F A bit position. In the NT-to-TE direction the S-channel bits are used for information transmission. One S channel (S1) out of five possible S-channels can be accessed by the SBCX-X. In the NT-to-TE direction the S-channel bits are used for information transmission. The S and Q channels are accessed via the µC interface or the IOM-2 MONITOR channel, respectively, by reading/writing the SQR or SQX bits in the S/Q channel registers (SQRRx, SQXRx). Table 7 shows the S and Q bit positions within the multiframe. Table 7 S/Q-Bit Position Identification and Multiframe Structure Frame Number NT-to-TE FA Bit Position NT-to-TE M Bit NT-to-TE S Bit TE-to-NT FA Bit Position ONE ZERO ZERO ZERO ZERO ONE ZERO ZERO ZERO ZERO S11 S21 S31 S41 S51 ZERO ZERO ZERO ZERO ONE ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO S12 S22 S32 S42 S52 ZERO ZERO ZERO ZERO ONE ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO S13 S23 S33 S43 S53 ZERO ZERO ZERO ZERO ONE ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO S14 S24 S34 S44 S54 ZERO ZERO ZERO ZERO ONE ZERO ONE ZERO S11 S21 ZERO

Description of Functional Blocks Data Sheet 41 2003-02-04 TE Mode After multiframe synchronization has been established, the Q data will be inserted at the upstream (TE /g174 NT) FA bit position in each 5th S/T frame (see Table 7). When synchronization is not achieved or lost, each received FA bit is mirrored to the next transmitted FA bit. Multiframe synchronization is achieved after two complete multiframes have been detected with reference to FA/N bit and M bit positions. Multiframe synchronization is lost if bit errors in F A/N bit or M bit positions have been detected in two consecutive multiframes. The synchronization state is indicated by the MSYN bit in the S/Q-channel receive register (SQRR1). The multiframe synchronization can be enabled or disabled by programming the MFEN bit in the S/Q-channel transmit register (SQXR1). NT Mode The transceiver in NT mode starts multiframing if SQXR1.MFEN is set. After multiframe synchronization has been established in the TE, the Q data will be inserted at the upstream (TE /g174 NT) FA bit position by the TE in each 5th S/T frame, the S data will be inserted at the downstream (NT /g174 TE) S bit position in each S/T frame (see Table 7). Interrupt Handling for Multiframing To trigger the microcontroller for a multiframe access an interrupt can be generated once per multiframe (SQW) or if the received S-channels (TE) or Q-channel (NT) have changed (SQC). In both cases the microcontroller has access to the multiframe within the duration of one multiframe (5 ms).

Description of Functional Blocks Data Sheet 42 2003-02-04

3.3.3 Data Transfer and Delay between IOM-2 and S/T

In the state F7 (Activated) or if the internal layer-1 statemachine is disabled and XINF of register TR_CMD is programmed to ’011’ the B1, B2, D and E bits are transferred transparently from the S/T to the IOM-2 interface. In all other states ’1’s are transmitted to the IOM-2 interface. To transfer data transparently to the S/T interface any activation request C/I command (AR8, AR10 or ARL) is additionally necessary or if the internal layer-1 statemachine is disabled, bit TDDIS of register TR_CMD has additionally to be programmed to ’0’. Figure 17 shows the data delay between the IOM-2 and the S/T interface and vice versa. For the D channel the delay from the IOM-2 to the S/T interface is only valid if S/G evaluation is disabled (TR_MODE2.DIM0=0). If S/G evaluation is enabled (TR_MODE2.DIM2-0=0x1) the delay depends on the selected priority and the relation between the echo bits on S and the D channel bits on the IOM-2, e.g. for priority 8 the timing relation between the 8th D-bit on S bus and the D-channel on IOM-2. Figure 17 Data Delay between IOM-2 and S/T Interface (TE mode only) line_iom_s.vsd NT -> TE DD DU FSC TE -> NT B1 B1 B2 B2F D DDD B1 B1 B2 B2F D DDD B1 B1 B2 B2F D DDDE EEE B1 B1 B2 B2F D DDDE EEE E E E E B2 DB1 B2 DB1 B2 DB1 B2 DB1 B2 DB1B2 DB1B2 DB1B2 DB1

Description of Functional Blocks Data Sheet 43 2003-02-04 Figure 18 Data Delay between IOM-2 and S/T Interface with S/G Bit Evaluation (TE mode only) LT-T mode In this mode the frame relation between S/T interface and IOM-2 is flexible. LT-S/NT mode In the state F7 (Activated) or if the internal layer-1 statemachine is disabled and XINF of register TR_CMD is programmed to ’011’ the B1, B2 and D bits are transferred transparently from the S/T to the IOM-2 interface. In all other states ’1’s are transmitted to the IOM-2 interface. Note: In intelligent NT the D-channel access can be blocked by the IOM-2 D-channel handler. line_iom_s_dch.vsd NT -> TE DD DU FSC TE -> NT B1 B1 B2 B2F D DDD B1 B1 B2 B2F D DDD B1 B1 B2 B2F D DDDE EEE B1 B1 B2 B2F D DDDE EEE E E E E B2 DB1 B2 DB1 B2 DB1 B2 DB1 B2 DB1B2 DB1B2 DB1B2 DB1 Mapping of B-Channel Timeslots 1. Possibility 2. Possibility Mapping of a 4-bit group of D-bits on S and IOM depends on prehistory (e.g. priority control):

Description of Functional Blocks Data Sheet 45 2003-02-04

3.3.4 Transmitter Characteristics

The full-bauded pseudo-ternary pulse shaping is achieved with the integrated transmitter which is realized as a symmetrical current limited voltage source (VSX1/SX2 = +/-1.05 V; Imax = 26 mA). The equivalent circuit of the transmitter is shown in Figure 21. The nominal pulse amplitude on the S-interface of 750 mV (zero-peak) is adjusted with external resistors (see Chapter 3.3.6.1). Figure 21 Equivalent Internal Circuit of the Transmitter Stage 21150_28 Level '+0' '-0' '1' '+0' '-0' '1' VCM+0.525V VCM-0.525V VCM VCM-0.525V VCM+0.525V VCM TR_CONF2.DIS_TX '+0' '1' '-0' V=1 VCM V=1 SX2 SX1

Description of Functional Blocks Data Sheet 46 2003-02-04

3.3.5 Receiver Characteristics

The receiver consists of a differential input stage, a peak detector and a set of comparators. Additional noise immunity is achieved by digital oversampling after the comparators. A simplified equivalent circuit of the receiver is shown in Figure 22. Figure 22 Equivalent Internal Circuit of the Receiver Stage The input stage works together with external 10 k/g87 resistors to match the input voltage to the internal thresholds. The data detection threshold Vref is continuously adapted between a maximal (Vrefmax) and a minimal (Vrefmin) reference level related to the line level. The peak detector requires maximum 2 /g109s to reach the peak value while storing the peak level for at least 250 /g109s (RC > 1 ms). The additional level detector for power up/down control works with a fixed threshold VrefLD. The level detector monitors the line input signals to detect whether an INFO is present. When closing an analog loop it is therefore possible to indicate an incoming signal during activated loop. 100 k/g87 Level detected VCM Vrefmin Vref+ Vref- SR110 k/g87 10 k/g87 40 k/g87 40 k/g87 VrefLD SR2 Peak Detector Negative detected reccirc Positive detected

Description of Functional Blocks Data Sheet 47 2003-02-04

3.3.6 S/T Interface Circuitry

For both, receive and transmit direction a 1:1 transformer is used to connect the SBCX- X transceiver to the 4 wire S/T interface. Typical transformer characteristics can be found in the chapter on electrical characteristics. The connections of the line transformers is shown in Figure 23. Figure 23 Connection of Line Transformers and Power Supply to the SBCX-X For the transmit direction an external transformer is required to provide isolation and pulse shape according to the ITU-T recommendations.

3.3.6.1 External Protection Circuitry

The ITU-T I.430 specification for both transmitter and receiver impedances in TEs results in a conflict with respect to external S-protection circuitry requirements: – To avoid destruction or malfunction of the S-device it is desirable to drain off even small overvoltages reliably. – To meet the 96 kHz impedance test specified for transmitters and receivers (for TEs dimensioned such that voltages below 1.2 V (ITU-T I.430 amplitude) x transformer ratio are not affected. This requirement results from the fact that this test is also to be performed with no supply voltage being connected to the TE. Therefore the second reference point for overvoltages V DD, is tied to GND. Then, if the amplitude of the 96 kHz test signal is greater than the combined forward voltages of the diodes, a current exceeding the specified one may pass the protection circuit. The following recommendations aim at achieving the highest possible device protection against overvoltages while still fulfilling the 96 kHz impedance tests. 21150_05 Protection Circuit Protection Circuit 1:1 1:1 Transmit Pair Receive Pair SX1 SX2 SR1 SR2GND VDD VSS 3.3 V 10 µF

Description of Functional Blocks Data Sheet 49 2003-02-04 Between each receive line and the transformer a 10 k /g87/g32resistor is used. This value is split into two resistors: one between transformer and protection diodes for current limiting during the 96 kHz test, and the second one between input pin and protection diodes to limit the maximum input current of the chip. With symmetrical receivers no difficulties regarding LCL measurements are observed; compensation networks thus are obsolete. In order to comply to the physical requirements of ITU-T recommendation I.430 and considering the national requirements concerning overvoltage protection and electromagnetic compatibility (EMC), the SBCX-X may need additional circuitry.

3.3.6.2 S-Transceiver Synchronization

Synchronization problems can occur on a S-Bus that is not terminated properly. Therefore, it is recommended to change the resistor values in the receive path. The sum of both resistors is increased from 10 k receiver line. This change is possible but not necessary for a S-Bus that is terminated properly. Figure 26 External Circuitry for Symmetrical Receivers Note: Lower or higher values than 34 k/g87 may be used as well, however for values above 34 k/g87 the additional delay must be compensated by setting TR_CONF2.PDS=1 (compensates 260 ns) so the allowed input phase delay is not violated. Note: Capacitors (up to 10 pF) are optional for noise reduction. 21150_33 1:1 S Bus SR2 SR1 GND V DD R1 R2 R1 R2

Description of Functional Blocks Data Sheet 50 2003-02-04

3.3.7 S/T Interface Delay Compensation (TE/LT-T Mode)

The S/T transmitter is shifted by two S/T bits minus 7 oscillator periods (plus analog delay plus delay of the external circuitry) with respect to the received frame. To compensate additional delay introduced into the receive and transmit path by the external circuit the delay of the transmit data can be reduced by another two oscillator periods (2 x 130 ns). Therefore PDS of the TR_CONF2 register must be programmed to ’1’. This delay compensation might be necessary in order to comply with the "total phase deviation input to output" requirement of ITU-T recommendation I.430 which specifies a phase deviation in the range of – 7% to + 15% of a bit period.

3.3.8 Level Detection Power Down

If MODE1.CFS is set to ’0’, the clocks are also provided in power down state, whereas if CFS is set to ’1’ only the analog level detector is active in power down state. All clocks, including the IOM-2 interface, are stopped (DD, DU are ’high’, DCL and BCL are ’low’). An activation initiated from the exchange side will have the consequence that a clock signal is provided automatically if TR_CONF0.LDD is set to ’0’. If TR_CONF0.LDD is set to ’1’ the microcontroller has to take care of an interrupt caused by the level detect circuit (ISTATR.LD) From the terminal side an activation must be started by setting and resetting the SPU-bit in the IOM_CR register and writing TIM to the CIX0 register or by resetting MODE1.CFS=0.

3.3.9 Transceiver Enable/Disable

The layer-1 part of the SBCX-X can be enabled/disabled by configuration (see Figure 27) with the two bits TR_CONF0.DIS_TR and TR_CONF2.DIS_TX . By default all layer-1 functions with the exception of the transmitter buffer is enabled (DIS_TR = ’0’, DIS_TX = ’1’). With several terminals connected to the S/T interface, another terminal may keep the interface activated although the SBCX-X does not establish a connection. The receiver will monitor for incoming calls in this configuration. If the transceiver is disabled (DIS_TR = ’1’) all layer-1 functions are disabled including the level detection circuit of the receiver. In this case the power consumption of the Layer-1 is reduced to a minimum. The DCL and FSC pins become input.

Description of Functional Blocks Data Sheet 51 2003-02-04 Figure 27 Disabling of S/T Transmitter

3.3.10 Test Functions

The SBCX-X provides test and diagnostic functions for the S/T interface: Note: For more details please refer to the application note “Test Function of new S- Transceiver family” – The internal local loop (internal Loop A) is activated by a C/I command ARL or by setting the bit LP_A (Loop Analog) in the TR_CMD register if the layer-1 statemachine is disabled. The transmit data of the transmitter is looped back internally to the receiver. The data of the IOM-2 input B- and D-channels are looped back to the output B- and D- channels. The S/T interface level detector is enabled, i.e. if a level is detected this will be reported by the Resynchronization Indication (RSY) but the loop function is not affected. Depending on the DIS_TX bit in the TR_CONF2 register the internal local loop can be transparent or non transparent to the S/T line. – The external local loop (external Loop A) is activated in the same way as the internal local loop described above. Additionally the EXLP bit in the TR_CONF0 register has to be programmed and the loop has to be closed externally as described in Figure 28. The S/T interface level detector is disabled. This allows complete system diagnostics. –I n remote line loop (RLP) received data is looped back to the S/T interface. The D- channel information received from the line card is transparently forwarded to the output IOM-2 D-channel. The output B-channel information on IOM-2 is fixed to ‘FF’ H while this test loop is active. The remote loop is programmable in TR_CONF2.RLP. TR_CONF2.DIS_TX ’1’ ’0’ TR_CONF0.DIS_TR

Description of Functional Blocks Data Sheet 52 2003-02-04 Figure 28 External Loop at the S/T-Interface – transmission of special test signals on the S/T interface according to the modified AMI code are initiated via a C/I command written in CIX0 register (see Chapter 3.5.4) Two kinds of test signals may be transmitted by the SBCX-X: – The single pulses are of alternating polarity. One pulse is transmitted in each frame resulting in a frequency of the fundamental mode of 2 kHz. The corresponding C/I command is SSP (Send Single Pulses). – The continuous pulses are of alternating polarity. 48 pulses are transmitted in each frame resulting in a frequency of the fundamental mode of 96 kHz. The corresponding C/I command is SCP (Send Continuous Pulses). SCOUT-S(X) SX1 SX2 SR1 SR2 100 /g87 100 /g87

Description of Functional Blocks Data Sheet 53 2003-02-04

3.4 Clock Generation

Figure 29 shows the clock system of the SBCX-X. The oscillator is used to generate a 7.68 MHz clock signal (f XTAL). In TE mode the DPLL generates the IOM-2 clocks FSC (8 kHz), DCL (1536 kHz) and BCL (768 kHz) synchronous to the received S/T frames. In LT modes these pins are input and in LT-T mode an 1536 kHz clock synchronous to S is output at SCLK which can be used for DCL input. The FSC signal is used to generate the pulse lengths of the different reset sources C/I Code, EAW pin and Watchdog (see Chapter 3.2.4). Figure 29 Clock System of the SBCX-X 3081_06 OSC XTAL

7.68 MHz

FSC (TE mode) DCL (TE mode) BCL (TE mode) SCLK (LT-T mode) 125 µs /g163 t /g163 250 µs 125 µs /g163 t /g163 250 µs 125 µs /g163 t /g163 250 µs Pin RSTO 125 µs /g163 t /g163 250 µs

Description of Functional Blocks Data Sheet 54 2003-02-04 Table 8 Clock Modes TE LT-T LT-S NT Int. NT Selected via pin: MODE0=0 pin:MODE1=0 MODE0=1 pin:MODE1=1 MODE0=1 bit:MODE2=0 MODE1=1 MODE0=0 bit:MODE2=1 MODE1=1 MODE0=1 or MODE0=0 *1) FSC o:8 kHz i:8 kHz i:8 kHz i:8 kHz i:8 kHz DCL o:1536 kHz i:1536 kHz (from SCLK) or 4096 kHz (from ext. PLL) i:512 kHz or 1536 kHz or 4096 kHz i:512 kHz or 1536 kHz or 4096 kHz i:1536 kHz BCL/SCLK o:768 kHz (BCL) o:1536 kHz (SCLK) *3) o:256 kHz or 768 kHz or 2048 kHz (derived from DCL/2) o:256 kHz or 768 kHz or 2048 kHz (derived from DCL/2) o:768 kHz (derived from DCL/2) DU *4) i i ooo D D o o iii AUX0-2 general purpose I/O pins CH0-2: strap pins for IOM channel select *2) CH0-2: strap pins for IOM channel select *2) CH0-2: strap pins for IOM channel select *2) general purpose I/O pins

Description of Functional Blocks Data Sheet 55 2003-02-04 Note: The IOM-2 interface is adaptive. This means in LT-S/NT and LT-T mode other frequencies for BCL and DCL are possible in the range of 512-4096 kHz (DCL) and 256-2048 kHz (BCL). For details please refer to the application note “Reconfigurable PBX”. Note: i = input; o = output; For all input clocks typical values are given although other clock frequencies may be used, too. 1) The modes TE, LT-T and LT-S can directly be selected by strapping the pins MODE1 and MODE0. The mode can be reprogrammed in TR_MODE.MODE2-0 where NT and intelligent NT can be selected additionally. In int. NT mode MODE0 selects between NT state machine (0) and LT-S state machine (1). 2) The number of IOM channels depends on the DCL clock, e.g. with DCL=1536 kHz 3 IOM channels and with DCL=4096 kHz 8 channels are available. 3) In LT-T mode the 1536 kHz output clock on SCLK is synchronous to the S interface and can be used as input for the DCL clock. 4) The direction input/output refers to the direction of the B- and D-channel data stream across the S-transceiver. Due to the capabilites of the IOM-2 handler the direction of some other timeslots may be different if this is programmed by the host (e.g. for data exchange between different devices connected to IOM-2).

Description of Functional Blocks Data Sheet 56 2003-02-04

3.4.1 Description of the Receive PLL (DPLL)

The receive PLL performs phase tracking between the F/L transition of the receive signal and the recovered clock. Phase adjustment is done by adding or subtracting 0.5 or 1 XTAL period to or from a 1.536-MHz clock cycle. The 1.536-MHz clock is than used to generate any other clock synchronized to the line. During (re)synchronization an internal reset condition may effect the 1.536-MHz clock to have high or low times as short as 130 ns. After the S/T interface frame has achieved the synchronized state (after three consecutive valid pairs of code violations) the FSC output in TE mode is set to a specific phase relationship, thus causing once an irregular FSC timing. The phase relationships of the clocks are shown in Figure 30. Figure 30 Phase Relationships of SBCX-X Clock Signals

3.4.2 Jitter

The timing extraction jitter of the SBCX-X conforms to ITU-T Recommendation I.430 (– 7% to + 7% of the S-interface bit period). ITD09664 1536 kHz * 768 kHz * Synchronous to receive S/T. Duty Ratio 1:1 Normally F-bit FSC

Description of Functional Blocks Data Sheet 57 2003-02-04

3.4.3 Oscillator Clock Output C768

The SBCX-X derives its system clocks from an external clock connected to XTAL1 (while XTAL2 is not connected) or from a 7.68 MHz crystal connected across XTAL1 and XTAL2. At pin C768 a buffered 7.68 MHz output clock is provided to drive further devices, which is suitable in multiline applications for example (see Figure 31). This clock is not synchronized to the S-interface. In power down mode the C768 output is disabled (low signal). Figure 31 Buffered Oscillator Clock Output 3086_12 XTAL1 XTAL2 C768XTAL1 XTAL2 C768XTAL1 XTAL2 C768 7.68 MHz

Description of Functional Blocks Data Sheet 58 2003-02-04

3.5 Control of Layer-1

The layer-1 activation / deactivation can be controlled by an internal state machine via the IOM-2 C/I0 channel or by software via the microcontroller interface directly. In the default state the internal layer-1 state machine of the SBCX-X is used. By setting the L1SW bit in the TR_CONF0 register the internal state machine can be disabled and the layer-1 commands, which are normally generated by the internal state machine are written directly in the TR_CMD register or indications read from the TR_STA register respectively.The SBCX-X layer-1 control flow is shown in Figure 32. Figure 32 Layer-1 Control In the following sections the layer-1 control by the SBCX-X state machine will be described. For the description of the IOM-2 C/I0 channel see also Chapter 3.7.4. The layer-1 functions are controlled by commands issued via the CIX0 register. These commands, sent over the IOM-2 C/I channel 0 to layer-1, trigger certain procedures, such as activation/deactivation, switching of test loops and transmission of special pulse patterns. These procedures are governed by layer-1 state diagrams. Responses from layer 1 are obtained by reading the CIR0 register after a CIC interrupt (ISTA). The state diagrams of the SBCX-X are shown in Figure 34 and Figure 35. The activation/deactivation implemented by the SBCX-X agrees with the requirements set forth in ITU recommendations. State identifiers F1-F8 are in accordance with ITU I.430.

Description of Functional Blocks Data Sheet 59 2003-02-04 State machines are the key to understanding the transceiver part of the SBCX-X. They include all information relevant to the user and enable him to understand and predict the behaviour of the SBCX-X. The state diagram notation is given in Figure 33. The informations contained in the state diagrams are: – state name (based on ITU I.430) – S/T signal received (INFO) – S/T signal transmitted (INFO) – C/I code received – C/I code transmitted – transition criteria The coding of the C/I commands and indications are described in detail in Chapter 3.5.4. Figure 33 State Diagram Notation The following example illustrates the use of a state diagram with an extract of the TE state diagram. The state explained is “F3 deactivated”. The state may be entered: – from the unconditional states (ARL, RES, TM) – from state “F3 pending deactivation”, “F3 power up”, “F4 pending activation” or “F5 unsynchronized” after the C/I command “DI” has been received. The following informations are transmitted: – INFO 0 (no signal) is sent on the S/T-interface. – C/I message “DC” is issued on the IOM-2 interface. ITD09657 Cmd.Ind. State ΙC / Unconditional Transition S / T Interface INFO OUT IPAC IN i x i r IPAC IOM-2 Interface SBCX-X

Description of Functional Blocks Data Sheet 60 2003-02-04 The state may be left by either of the following methods: – Leave for the state “F3 power up” in case C/I = “TIM” code is received. – Leave for state “F4 pending activation” in case C/I = AR8 or AR10 is received. – Leave for the state “F6 synchronized” after INFO 2 has been recognized on the S/T- interface. – Leave for the state “F7 activated” after INFO 4 has been recognized on the S/T- interface. – Leave for any unconditional state if any unconditional C/I command is received. As can be seen from the transition criteria, combinations of multiple conditions are possible as well. A “/g42” stands for a logical AND combination. And a “+” indicates a logical OR combination. The sections following the state diagram contain detailed information on all states and signals used.

3.5.1 State Machine TE and LT-T Mode

3.5.1.1 State Transition Diagram (TE, LT-T)

Figure 34 shows the state transition diagram of the SBCX-X state machine. Figure 35 shows this for the unconditional transitions (Reset, Loop, Test Mode i).

Description of Functional Blocks Data Sheet 61 2003-02-04 Figure 34 State Transition Diagram (TE, LT-T) X 1) DR for transition from F7 or F8 DR6 for transition from F6 2) AR stands for AR8 or AR10 3) AI stands for AI8 or AI10 4) X stands for commands initiating unconditional transitions (RES, ARL, SSP or SCP) TO1: 16 ms TO2: 0.5 ms statem_te_s.vsd Pending Deact. DR1) i0 i0 Deactivated DC DI i0 i0 AR i2 TIM i0*TO1 Power Up PU TIM i0 i0 DI TIM DI DI*TO2 TIM*TO2 Lost Framing RSY X i0*TO1 i0*TO1 AR DI Activated AI3) AR2) i3 i4 Synchronized AR i3 i2 X Unsynchronized RSY i0 ix Pending Act. PU AR2) i1 i0 X ix ix TIM TIM DI TIM X4) Uncond. State X DI

Description of Functional Blocks Data Sheet 62 2003-02-04 Figure 35 State Transition Diagram of Unconditional Transitions (TE, LT-T)

3.5.1.2 States (TE, LT-T)

State after deactivation from the S/T interface by INFO 0. Note that no activation from the terminal side is possible starting from this state. A ’DI’ command has to be issued to enter the state ’Deactivated State’. F3 Deactivated State The S/T interface is deactivated and the clocks are deactivated 500 µs after entering this state and receiving INFO 0 if the CFS bit of the SBCX-X Configuration Register is set to “0“. Activation is possible from the S/T interface and from the IOM-2 interface. The bit TR_CMD.PD is set and the analog part is powered down. F3 Power Up The S/T interface is deactivated (INFO 0 on the line) and the clocks are running. F4 Pending Activation The SBCX-X transmits INFO 1 towards the network, waiting for INFO 2. statem_te_aloop_s.vsd Loop A Activated AIL RSY ARL i3 * Loop A Closed ARL ARL i3 * DI TIM DI TIM ARL Reset RES RES i0 * DI TIM SSP SCP Test Mode i TMA SSP SCP iti * DI TIM i3i3 RES Any State RST

Description of Functional Blocks Data Sheet 63 2003-02-04 F5 Unsynchronized Any signal except INFO 2 or 4 detected on the S/T interface. F6 Synchronized The receiver has synchronized and detects INFO 2. INFO 3 is transmitted to synchronize the NT. F7 Activated The receiver has synchronized and detects INFO 4. All user channels are now conveyed transparently to the IOM-2 interface. To transfer user channels transparently to the S/T interface either the command AR8 or AR10 has to be issued and TR_STA.FSYN must be “1” (signal from remote side must be synchronous). F8 Lost Framing The receiver has lost synchronization in the states F6 or F7 respectively. Unconditional States Loop A Closed (internal or external) The SBCX-X loops back the transmitter to the receiver and activates by transmission of INFO 3. The receiver has not yet synchronized. For a non transparent internal loop the DIS_TX bit of register TR_CONF2 has to be set to ’1’. Loop A Activated (internal or external) The receiver has synchronized to INFO 3. Data may be sent. The indication “AIL” is output to indicate the activated state. If the loop is closed internally and the S/T line awake detector detects any signal on the S/T interface, this is indicated by “RSY”. Test Mode - SSP Single alternating pulses are transmitted to the S/T-interface resulting in a frequency of the fundamental mode of 2 kHz. Test Mode - SCP Continuous alternating pulses are transmitted to the S/T-interface resulting in a frequency of the fundamental mode of 96 kHz.

Description of Functional Blocks Data Sheet 64 2003-02-04

3.5.1.3 C/I Codes (TE, LT-T)

Note: In the activated states (AI8, AI10 or AIL indication) the 2B+D channels are only transferred transparently to the S/T interface if one of the three “Activation Request” commands is permanently issued. Command Abbr. Code Remark Activation Request with priority class 8 AR8 1000 Activation requested by the SBCX-X, D-channel priority set to 8 (see note) Activation Request with priority class 10 AR10 1001 Activation requested by the SBCX-X, D-channel priority set to 10 (see note) Activation Request Loop ARL 1010 Activation requested for the internal or external Loop A (see note). For a non transparent internal loop bit DIS_TX of register TR_CONF2 has to be set to ’1’ additionally. Deactivation Indication DI 1111 Deactivation Indication Reset RES 0001 Reset of the layer-1 statemachine Timing TIM 0000 Layer-2 device requires clocks to be activated Test mode SSP SSP 0010 One AMI-coded pulse transmitted in each frame, resulting in a frequency of the fundamental mode of 2 kHz Test mode SCP SCP 0011 AMI-coded pulses transmitted continuously, resulting in a frequency of the fundamental mode of 96 kHz

Description of Functional Blocks Data Sheet 65 2003-02-04 Indication Abbr. Code Remark Deactivation Request DR 0000 Deactivation request via S/T-interface if left from F7/F8 Reset RES 0001 Reset acknowledge Test Mode Acknowledge TMA 0010 Acknowledge for both SSP and SCP Slip Detected SLD 0011 Resynchronization during level detect RSY 0100 Signal received, receiver not synchronous Deactivation Request from F6 DR6 0101 Deactivation Request from state F6 Power up PU 0111 IOM-2 interface clocking is provided Activation request AR 1000 INFO 2 received Activation request loop ARL 1010 Internal or external loop A closed Illegal Code Violation CVR 1011 Illegal code violation received. This function has to be enabled by setting the EN_ICV bit of register TR_CONF0. Activation indication loop AIL 1110 Internal or external loop A activated Activation indication with priority class 8 AI8 1100 INFO 4 received, D-channel priority is 8 or 9. Activation indication with priority class 10 AI10 1101 INFO 4 received, D-channel priority is 10 or 11. Deactivation confirmation DC 1111 Clocks are disabled if CFS bit of register MODE1 is set to ’1’, quiescent state

Description of Functional Blocks Data Sheet 66 2003-02-04

3.5.1.4 Infos on S/T (TE, LT-T)

Receive Infos on S/T (Downstream) Transmit Infos on S/T (Upstream) Name Abbr. Description INFO 0 i0 No signal on S/T INFO 2 i2 4 kHz frame A=’0’ INFO 4 i4 4 kHz frame A=’1’ INFO X ix Any signal except INFO 2 or INFO 4 Name Abbr. Description INFO 0 i0 No signal on S/T INFO 1 i1 Continuous bit sequence of the form ’00111111’ INFO 3 i3 4 kHz frame Test INFO 1 it

1 SSP - Send Single Pulses

Test INFO 2 it 2 SCP - Send Continuous Pulses

Description of Functional Blocks Data Sheet 67 2003-02-04

3.5.2 State Machine LT-S Mode

3.5.2.1 State Transition Diagram (LT-S)

Figure 36 State Transition Diagram (LT-S) Note: State ’Test Mode’ can be entered from any state except from state ’Test Mode’ itself , i.e. C/I-code ’SSP/SCP’ must not be followed by C/I-code ’SCP/SSP’ directly. G3 Activated AI DC ARD i4 i3 Reset TIM RES i0 * G2 Pend. Act. AR DC ARD i2 i3 G2 Lost Framing S/T RSY DC ARD i2 i3 G1 Deactivated DI TIM 2) DC i0 i0 1) ARD = AR or ARL st at em_lt s_s. vsd G4 Pend. Deact. TIM DR i0 i0 Test Mode i TIM SSP SCP it * DRDR G4 Wait for DR DI DR i0 * (i0*16ms)+32ms DC DC SSP SCP Any State DR DC Any State RES ARD1) ARD1) DR DR DR RST (i0*8ms)+ARD1) 2) DI if i0 TIM if i0

Description of Functional Blocks Data Sheet 68 2003-02-04

3.5.2.2 States (LT-S)

The transceiver is not transmitting. There is no signal detected on the S/T interface, and no activation command is received in the C/I channel. The clocks are deactivated if MODE1.CFS is set to 1. Activation is possible from the S/T interface and from the IOM- 2 interface. G2 Pending Activation As a result of an INFO 0 detected on the S/T line or an ARD command, the transceiver begins transmitting INFO 2 and waits for reception of INFO 3. The timer to supervise reception of INFO 3 is to be implemented in software. In case of an ARL command, loop 2 is closed. G3 Activated Normal state where INFO 4 is transmitted to the S/T-interface. The transceiver remains in this state as long as neither a deactivation nor a test mode is requested, nor the receiver looses synchronism. When receiver synchronism is lost, INFO 2 is sent automatically. After reception of INFO 3, the transmitter keeps on sending INFO 4. G2 Lost Framing This state is reached when the transceiver has lost synchronism in the state G3 activated. G4 Pending Deactivation This state is triggered by a deactivation request DR. It is an unstable state: indication DI (state “G4 Wait for DR.”) is issued by the transceiver when: either INFO 0 is received for a duration of 16 ms, or an internal timer of 32 ms expires. G4 Wait for DR Final state after a deactivation request. The transceiver remains in this state until DC is issued. Unconditional States Test mode - SSP Single alternating pulses are sent on the S/T-interface.

Description of Functional Blocks Data Sheet 69 2003-02-04 Test mode - SCP Continuous alternating pulses are sent on the S/T-interface.

3.5.2.3 C/I Codes (LT-S)

Command Abbr. Code Remark Deactivation Request DR 0000 DR - Deactivation Request. Initiates a complete deactivation from the exchange side by transmitting INFO 0. Reset RES 0001 Reset of state machine. Transmission of INFO 0. No reaction to incoming infos. RES is an unconditional command. Send Single Pulses SSP 0010 Send Single Pulses. Send Continuous Pulses SCP 0011 Send Continuous Pulses. Activation Request AR 1000 Activation Request. This command is used to start an exchange initiated activation. Activation Request Loop ARL 1010 Activation request loop. The transceiver is requested to operate an analog loop-back close to the S/T-interface. Deactivation Confirmation DC 1111 Deactivation Confirmation. Transfers the transceiver into a deactivated state in which it can be activated from a terminal (detection of INFO 0 enabled). Indication Abbr. Code Remark Timing TIM 0000 Interim indication during activation procedure in G1. Receiver not Synchronous RSY 0100 Receiver is not synchronous Activation Request AR 1000 INFO 0 received from terminal. Activation proceeds. Illegal Code Violation CVR 1011 Illegal code violation received. This function has to be enabled in TR_CONF0.EN_ICV.

Description of Functional Blocks Data Sheet 70 2003-02-04

3.5.2.4 Infos on S/T (LT-S)

Receive Infos on S/T (Downstream) I0 INFO 0 detected I0 Level detected (signal different to I0) I3 INFO 3 detected I3 Any INFO other than INFO 3 Transmit Infos on S/T (Upstream) I0 INFO 0 I2 INFO 2 I4 INFO 4 It Send Single Pulses (SSP). Send Continuous Pulses (SCP). Activation Indication AI 1100 Synchronous receiver, i.e. activation completed. Deactivation Indication DI 1111 Timer (32 ms) expired or INFO 0 received for a duration of 16 ms after deactivation request Indication Abbr. Code Remark

Description of Functional Blocks Data Sheet 71 2003-02-04

3.5.3 State Machine NT Mode

3.5.3.1 State Transition Diagram (NT)

Figure 37 State Transition Diagram (NT) G2 Pend. Act AR ARD i2 i3 Reset TIM RES i0 * G1 i0 Detected AR DC i0 * G2 Lost Framing S/T RSY AID ARD i2 i3 G1 Deactivated DI TIM 3) DC i0 i0 st at em_nt _s. vsd G4 Pend. Deact. TIM DR i0 i0 Test Mode i TIM SSP SCP it * DRDR G4 Wait for DR DI DR i0 * (i0*16ms)+32ms DC DC SSP SCP Any State DR DC Any State RES ARD1) ARD1) DR i3*AID2) RST ARD1) G2 Wait for AID AI ARD i2 i3 G3 Lost Framing U RSY RSY i2 * G3 Activated AI AID i4 i3 ARD1) AID2) i3*ARD1) i3*ARD DR DR DR RSY RSY DRRSY ARD1) AID2) 1) ARD = AR or ARL 2) AID =AI or AIL 3) DI if i0 TIM if i0 ARD1) i3*AID2) (i0*8ms)

Description of Functional Blocks Data Sheet 72 2003-02-04 Note: State ’Test Mode’ can be entered from any state except from state ’Test Mode’ itself , i.e. C/I-code ’SSP/SCP’ must not be followed by C/I-code ’SCP/SSP’ directly.

3.5.3.2 States (NT)

The transceiver is not transmitting. There is no signal detected on the S/T-interface, and no activation command is received in the C/I channel. The clocks are deactivated if the bit MODE1.CFS is set to 1. Activation is possible from the S/T interface and from the IOM-2 interface. G1 I0 Detected An INFO 0 is detected on the S/T-interface, translated to an “Activation Request” indication in the C/I channel. The transceiver is waiting for an AR command, which normally indicates that the transmission line upstream (usually a two-wire U interface) is synchronized. G2 Pending Activation As a result of the ARD command, an INFO 2 is sent on the S/T-interface. INFO 3 is not yet received. In case of ARL command, loop 2 is closed. G2 wait for AID INFO 3 was received, INFO 2 continues to be transmitted while the transceiver waits for a “switch-through” command AID from the device upstream. G3 Activated INFO 4 is sent on the S/T-interface as a result of the “switch through” command AID: the B and D-channels are transparent. On the command AIL, loop 2 is closed. G2 Lost Framing S/T This state is reached when the transceiver has lost synchronism in the state G3 activated. G3 Lost Framing U On receiving an RSY command which usually indicates that synchronization has been lost on the two-wire U interface, the transceiver transmits INFO 2.

Description of Functional Blocks Data Sheet 73 2003-02-04 G4 Pending Deactivation This state is triggered by a deactivation request DR, and is an unstable state. Indication DI (state “G4 wait for DR”) is issued by the transceiver when: either INFO 0 is received for a duration of 16 ms or an internal timer of 32 ms expires. G4 wait for DR Final state after a deactivation request. The transceiver remains in this state until DC is issued. Unconditional States Test Mode SSP Send Single Pulses Test Mode SCP Send Continuous Pulses

3.5.3.3 C/I Codes (NT)

Command Abbr. Code Remark Deactivation Request DR 0000 DR - Deactivation Request. Initiates a complete deactivation from the exchange side by transmitting INFO 0. Unconditional command. Reset RES 0001 Reset of state machine. Transmission of INFO 0. No reaction to incoming infos. RES is an unconditional command. Send Single Pulses SSP 0010 Send Single Pulses. Send Continuous Pulses SCP 0011 Send Continuous Pulses. Receiver not Synchronous RSY 0100 Receiver is not synchronous Activation Request AR 1000 Activation Request. This command is used to start an exchange initiated activation. Activation Request Loop ARL 1010 Activation request loop. The transceiver is requested to operate an analog loop-back close to the S/T-interface.

Description of Functional Blocks Data Sheet 74 2003-02-04 Activation Indication AI 1100 Synchronous receiver, i.e. activation completed. Activation Indication Loop AIL 1110 Activation Indication Loop Deactivation Confirmation DC 1111 Deactivation Confirmation. Transfers the transceiver into a deactivated state in which it can be activated from a terminal (detection of INFO 0 enabled). Indication Abbr. Code Remark Timing TIM 0000 Interim indication during deactivation procedure Receiver not Synchronous RSY 0100 Receiver is not synchronous Activation Request AR 1000 INFO 0 received from terminal. Activation proceeds. Illegal Code Violation CVR 1011 Illegal code violation received. This function has to be enabled in TR_CONF0.EN_ICV. Activation Indication AI 1100 Synchronous receiver, i.e. activation completed. Deactivation Indication DI 1111 Timer (32 ms) expired or INFO 0 received for a duration of 16 ms after deactivation request Command Abbr. Code Remark

Description of Functional Blocks Data Sheet 75 2003-02-04

3.5.4 Command / Indicate Channel Codes (C/I0) - Overview

The table below presents all defined C/I0 codes. A command needs to be applied continuously until the desired action has been initiated. Indications are strictly state orientated. Refer to the state diagrams in the previous sections for commands and indications applicable in various states. Code TE/LT-T LT-S NT Cmd Ind Cmd Ind Cmd Ind 0000T I M D R D R T I M D R T I M 0001R E S R E S R E S – R E S – 0010S S P T M A S S P – S S P – 0011S C P S L D S C P – S C P – 0100– R S Y – R S Y R S Y R S Y 1000A R 8 A R A R A R A R A R 1010A R L A R L A R L – A R L – 1011– C V R – C V R – C V R 1100– A I 8 – A I A I A I 1110– A I L – – A I L – 1111D I D C D C D I D C D I

Description of Functional Blocks Data Sheet 76 2003-02-04

3.6 Control Procedures

3.6.1 Example of Activation/Deactivation

An example of an activation/deactivation of the S/T interface initiated by the terminal with the time relationships mentioned in the previous chapters is shown in Figure 38. Figure 38 Example of Activation/Deactivation Initiated by the Terminal A_DEACT.DRW NT/LinecardTE INFO 0 INFO 1 INFO 2 INFO 3 INFO 4 INFO 0 INFO 0DR AI AR RSY 16 ms 0.5 ms max. 6 ms AR

Description of Functional Blocks Data Sheet 77 2003-02-04

3.6.2 Activation initiated by the Terminal

INFO 1 has to be transmitted as long as INFO 0 is received. INFO 0 has to be transmitted thereafter as long as no valid INFO (INFO 2 or INFO 4) is received. After reception of INFO 2 or INFO 4 transmission of INFO 3 has to be started. Data can be transmitted if INFO 4 has been received. Figure 39 Example of Activation/Deactivation initiated by the Terminal (TE). Activation/Deactivation completely under Software Control Note: RINF and XINF are Receive- and Transmit-INFOs of the registers TR_STA TR_CMD. act_deac_te-ext_s.vsd XINF='000' RINF='01' RINF='10' XINF='011' INFO 1 INFO 0 INFO 2 INFO 0 INFO 3 INFO 4 XINF='010' T1TE INFO 0 INFO 0 INFO 0 XINF='000' TE NT S/T InterfaceµC Interface T1TE: 2 to 6 frames (0.5 ms to 1.5 ms) T3TE: 4 frames (1 ms) T2TE: 2 frames (0.5 ms) T3TE RINF='00' T2TE RINF='11' TDDIS='1', TDDIS='0' TDDIS='1',

Description of Functional Blocks Data Sheet 78 2003-02-04

3.6.3 Activation initiated by the Network Termination NT

INFO 0 has to be transmitted as long as no valid INFO (INFO 2 or INFO 4) is received. After reception of INFO 2 or INFO 4 transmission of INFO 3 has to be started. Data can be transmitted if INFO 4 has been received. Figure 40 Example of Activation/Deactivation initiated by the Network Termination (NT). Activation/Deactivation completely under Software Control Note: RINF and XINF are Receive- and Transmit-INFOs of the registers TR_STA TR_CMD. act_deac_lt_ext_s.vsd RINF='01' RINF='10' XINF='011' INFO 0 INFO 2 INFO 3 INFO 4 RINF='11' T1TE INFO 0 INFO 0 INFO 0 T2TE T3TE XINF='000' RINF='00' TE NT S/T InterfaceµC Interface T1TE: 2 to 6 S/T frames (0.5 ms to 1.5 ms) T3TE: 4 S/T frames (1 ms) T2TE: 2 S/T frames (0.5 ms) TDDIS='1', TDDIS='0' TDDIS='1',

Description of Functional Blocks Data Sheet 79 2003-02-04

3.7 IOM-2 Interface

The SBCX-X supports the IOM-2 interface in linecard mode and in terminal mode with single clock and double clock. The IOM-2 interface consists of four lines: FSC, DCL, DD and DU. The rising edge of FSC indicates the start of an IOM-2 frame. The DCL and the BCL clock signals synchronize the data transfer on both data lines DU and DD. The DCL is twice the bit rate, the BCL rate is equal to the bit rate. The bits are shifted out with the rising edge of the first DCL clock cycle and sampled at the falling edge of the second clock cycle. The IOM-2 interface can be enabled/disabled with the DIS_IOM bit in the IOM_CR register. TE Mode A DCL signal and BCL signal (pin BCL/SCLK) output is provided and the FSC signal is generated by the receive DPLL which synchronizes it to the received S/T frame. The BCL clock together with the two serial data strobe signals (SDS1, SDS2) can be used to connect time slot oriented standard devices to the IOM-2 interface. If the transceiver is disabled (TR_CON.DIS_TR) the DCL and FSC pins become input. In this case the clock mode bit (IOM_CR.CLKM) selects between a double clock and a single clock input for DCL. The clock rate/frequency of the IOM-2 signals in TE mode are: DD, DU: 768 kbit/s FSC (o): 8 kHz DCL (o): 1536 kHz (double clock rate) BCL (o): 768 kHz (single clock rate) Option - Transceiver disabled (DIS_TR = ’1’): FSC (i): 8 kHz DCL (i): 1536 ... 4096 kHz, in steps of 512 kHz (double clock rate) LT-S, LT-T, NT, iNT Mode The IOM-2 clock signals FSC and BCL are input. In LT-T mode a 1536 kHz output clock synchronous to S is provided at pin SCLK which can directly be connected to the DCL input. DD, DU: data rate = DCL/2 kbit/s (LT-T mode) FSC (i): 8 kHz DCL (i): 512 ... 4096 kHz, in steps of 512 kHz (double clock rate) SCLK (o): 1536 kHz (LT-T mode), BCL derived via DCL/2 (LT-S/NT mode) Note: In all modes the direction of the data lines DU and DD is not fix but depending on the timeslot which can be seen in the figures below.

Description of Functional Blocks Data Sheet 80 2003-02-04 IOM-2 Frame Structure (TE Mode) The frame structure on the IOM-2 data port s (DU, DD) of a master device in IOM-2 terminal mode is shown in Figure 41. Figure 41 IOM /g210-2 Frame Structure in Terminal Mode The frame is composed of three channels  Channel 0 contains 144-kbit/s of user and signaling data (2B + D), a MONITOR programming channel (MON0) and a command/indication channel (CI0) for control and programming of the layer-1 transceiver.  Channel 1 contains two 64-kbit/s intercommunication channels (IC) plus a MONITOR and command/indicate channel (MON1, CI1) to program or transfer data to other IOM-2 devices.  Channel 2 is used for the TlC-bus access. Only the command/indicate bits are specified in this channel.

Description of Functional Blocks Data Sheet 81 2003-02-04 IOM-2 Frame Structure (LT-S, LT-T Modes) This mode is used in LT-S and LT-T applications. The frame is a multiplex of up to eight IOM-2 channels (DCL = 4096 kHz, see Figure 42), each of which has the structure described above. The reset value for assignment to one of the eight channels (0 to 7) is done via pin strapping (CH0-2), however the host can reprogram the selected timeslot in DCH_TSDP.TSS. Figure 42 Multiplexed Frame Structure of the IOM-2 Interface in Non-TE Timing Mode IOM-2 Frame Structure (NT Mode) In NT mode one IOM-2 channel is used (DCL=512 kHz). The channel structure is the same as described above. ITD09635 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH0 CH0CH7CH6CH5CH4CH3CH2CH1 B1 B2 MONITOR D C/I MM RX 125 FSC DCL DD DU sµ IOM CH0 IOM CH0 R R

Description of Functional Blocks Data Sheet 82 2003-02-04

3.7.1 IOM-2 Handler

The IOM-2 handler offers a great flexibility for handling the data transfer between the different functional units of the SBCX-X and voice/data devices connected to the IOM-2 interface. Additionally it provides a microcontroller access to all timeslots of the IOM-2 interface via the four controller data access registers (CDA). Figure 43 shows the architecture of the IOM-2 handler. For illustrating the functional description it contains all configuration and control registers of the IOM-2 handler. A detailed register description can be found in Chapter 4.3. The PCM data of the functional units  Transceiver (TR) and the  Controller data access (CDA) can be configured by programming the time slot and data port selection registers (TSDP). With the TSS bits (Time Slot Selection) the PCM data of the functional units can be assigned to each of the 32 PCM time slots of the IOM-2 frame. With the DPS bit (Data Port Selection) the output of each functional unit is assigned to DU or DD respectively. The input is assigned vice versa. With the data control registers (xxx_CR) the access to the data of the functional units can be controlled by setting the corresponding control bits (EN, SWAP). The IOM-2 handler also provides access to the  MONITOR channel (MON)  C/I channels (C/I0, C/I1) and  TIC bus (TIC) The access to these channels is controlled by the register MON_CR and DCI_CR. The IOM-2 interface with the two Serial Data Strobes (SDS1,2) is controlled by the control registers IOM_CR, SDS1_CR and SDS2_CR. The reset configuration of the SBCX-X IOM-2 handler corresponds to the defined frame structure and data ports of a master device in IOM-2 terminal mode (see Figure 41).

Description of Functional Blocks Data Sheet 83 2003-02-04 Figure 43 Architecture of the IOM Handler (Example Configuration) 3186_07 CDA Control ( DPS, TSS, EN_TBM, SWAP, EN_I1/0, EN_O1/0, MCDAxy, STIxy, STOVxy, ACKxy ) CDA Registers CDA10 CDA11 CDA20 CDA21 CDA_TSDPxy CDAx_CRx MCDA STI MSTI ASTI Controller Data Access (CDA) Control Monitor Data (DPS, CS2-0, EN_MON) MON_CR TIC Bus Disable (TIC_DIS) IOM_CR DCI_CR C/I1 (DPS_CI1, EN_CI1) Control Transceiver Data Access (DPS, TSS, CS2-0, EN_D, EN_B1R, EN_B1X, EN_B2R, EN_B2X ) TR_TSDP_BC1 TR_TSDP_BC2 TRC_CR D, B1, B2, C/I0 Data C/I1 Data C/I0 Data TIC Bus Data Monitor Data CDA Data Transceiver Data TR D-channel RX/TX B1-channel RX B1-channel TX MON Handler TIC Data Microcontroller Interface IOM_CR ( ENS_TSS, ENS_TSS+1, ENS_TSS+3, TSS, SDS_BCL IOM-2 Interface DU DD FSC DCL BCL / SCLK SDS1 IOM-2 Handler C/I0 (CS2-0) DCIC_CR B2-channel RX B2-channel TX SDS1_CR EN_BCL, CLKM, DIS_OD, DIS_IOM, DIOM_INV, DIOM_SDS Note: The registers shown above are used to control the corresponding functional block (e.g. programming of timeslot, data port, enabling/disabling, etc.) C/I Data Control C/I0 C/I1 SDS2 SDS2_CR

Description of Functional Blocks Data Sheet 84 2003-02-04

3.7.1.1 Controller Data Access (CDA)

With its four controller data access registers (CDA10, CDA11, CDA20, CDA21) the SBCX-X IOM-2 handler provides a very flexible solution for the host access to up to 32 IOM-2 time slots. The functional unit CDA (controller data access) allows with its control and configuration registers  looping of up to four independent PCM channels from DU to DD or vice versa over the four CDA registers  shifting of two independent PCM channels to another two independent PCM channels on both data ports (DU, DD). Between reading and writing the data can be manipulated (processed with an algorithm) by the microcontroller. If this is not the case a switching function is performed  monitoring of up to four time slots on the IOM-2 interface simultaneously  microcontroller read and write access to each PCM timeslot The access principle which is identical for the two channel register pairs CDA10/11 and CDA20/21 is illustrated in Figure 44. Each of the index variables x,y used in the following description can be 1 or 2 for x and 0 or 1 for y. The prefix ’CDA_’ from the register names has been omitted for simplification. To each of the four CDAxy data registers a TSDPxy register is assigned by which the time slot and the data port can be determined. With the TSS (Time Slot Selection) bits a time slot from 0...31 can be selected. With the DPS (Data Port Selection) bit the output of the CDAxy register can be assigned to DU or DD respectively. The time slot and data port for the output of CDAxy is always defined by its own TSDPxy register. The input of CDAxy depends on the SWAP bit in the control registers CRx.  If the SWAP bit = ’0’ (swap is disabled) the time slot and data port for the input and output of the CDAxy register is defined by its own TSDPxy register.  If the SWAP bit = ’1’ (swap is enabled) the input port and timeslot of the CDAx0 is defined by the TSDP register of CDAx1 and the input port and timeslot of CDAx1 is defined by the TSDP register of CDAx0. The input definition for timeslot and data port CDAx0 are thus swapped to CDAx1 and for CDAx1 swapped to CDAx0. The output timeslots are not affected by SWAP. The input and output of every CDAxy register can be enabled or disabled by setting the corresponding EN (-able) bit in the control register CDAx_CR. If the input of a register is disabled the output value in the register is retained. Usually one input and one output of a functional unit (transceiver, HDLC controller, CDA register) is programmed to a timeslot on IOM-2 (e.g. for B-channel transmission in upstream direction the HDLC controller writes data onto IOM and the transceiver reads data from IOM). For monitoring data in such cases a CDA register is programmed as described below under “Monitoring Data”. Besides that none of the IOM timeslots must be assigned more than one input and output of any functional unit.

Description of Functional Blocks Data Sheet 86 2003-02-04 Figure 45 Examples for Data Access via CDAxy Registers a) Looping Data b) Shifting (Switching) Data c) Switching and Looping Data TSa TSb TSc TSd CDA10 CDA11 CDA20 CDA21 TSa TSb TSc TSd DU DD TSa TSb TSc TSd CDA10 CDA11 CDA20 CDA21 DU DD b) Shifting Data a) Looping Data .TSS: .DPS .SWAP ’0’ ’1’’1’’0’’0’ ’0’ TSa TSb TSc TSd.TSS: .DPS .SWAP ’1’ ’1’’0’’1’’0’ ’1’ TSa TSb TSc TSd CDA10 CDA11 CDA20 CDA21 DU DD c) Switching Data TSa TSb TSc TSd.TSS: .DPS .SWAP ’1’ ’1’’1’’0’’0’ ’1’

Description of Functional Blocks Data Sheet 88 2003-02-04 Figure 47 Data Access when Shifting TSa to TSb on DU (DD) TSaDU TSb FSC CDAxy µC RD WR ACK STOV STI TSa STI TSa FSC CDAxy µC RD WR ACK STOV STI TSb TSa TSb (DD) (a,b: 0...31 and (b = a+1 or b <a) DU (DD) (a,b: 0...31 and b /g179 a+2) a) Shifting TSa /g174 TSb within one frame b) Shifting TSa /g174 TSb in the next frame *) if access by the µC is required

Description of Functional Blocks Data Sheet 90 2003-02-04 Synchronous Transfer While looping, shifting and switching the data can be accessed by the controller between the synchronous transfer interrupt (STI) and the status overflow interrupt (STOV). The microcontroller access to the CDAxy registers can be synchronized by means of four programmable synchronous transfer interrupts (STIxy)1) and synchronous transfer overflow interrupts (STOVxy) 2) in the STI register. Depending on the DPS bit in the corresponding CDA_TSDPxy register the STIxy is generated two (for DPS=’0’) or one (for DPS=’1’) BCL clock after the selected time slot (CDA_TSDPxy.TSS). One BCL clock is equivalent to two DCL clocks. In the following description the index xy 0 and xy 1 are used to refer to two different interrupt pairs (STI/STOV) out of the four CDA interrupt pairs (STI10/STOV10, STI11/ STOV11, STI20/STOV20, STI21/STOV21). An STOVxy 0 is related to its STIxy0 and is only generated if STIxy 0 is enabled and not acknowledged. However, if STIxy0 is masked, the STOVxy0 is generated for any other STIxy1 which is enabled and not acknowledged. Table 9 gives some examples for that. It is assumed that an STOV interrupt is only generated because an STI interrupt was not acknowledged before. In example 1 only the STIxy0 is enabled and thus STIxy0 is only generated. If no STI is enabled, no interrupt will be generated even if STOV is enabled (example 2). In example 3 STIxy 0 is enabled and generated and the corresponding STOVxy 0 is disabled. STIxy 1 is disabled but its STOVxy 1 is enabled, and therefore STOVxy 1 is generated due to STIxy 0. In example 4 additionally the corresponding STOVxy 0 is enabled, so STOVxy0 and STOVxy1 are both generated due to STIxy0. In example 5 additionally the STIxy 1 is enabled with the result that STOVxy 0 is only generated due to STIxy0 and STOVxy1 is only generated due to STIxy1. Compared to the previous example STOVxy 0 is disabled in example 6, so STOVxy 0 is not generated and STOVxy1 is only generated for STIxy1 but not for STIxy0. Compared to example 5 in example 7 a third STOVxy2 is enabled and thus STOVxy2 is generated additionally for both STIxy0 and STIxy1. 1) In order to enable the STI interrupts the input of the corresponding CDA register has to be enabled. This is also valid if only a synchronous write access is wanted. The enabling of the output alone does not effect an STI interrupt. 2) In order to enable the STOV interrupts the output of the corresponding CDA register has to be enabled. This is also valid if only a synchronous read access is wanted. The enabling of the input alone does not effect an interrupt.

Description of Functional Blocks Data Sheet 91 2003-02-04 An STOV interrupt is not generated if all stimulating STI interrupts are acknowledged. An STIxy must be acknowledged by setting the ACKxy bit in the ASTI register until two BCL clocks (for DPS=’0’) or one BCL clocks (for DPS=’1’) before the time slot which is selected for the appropriate STIxy. The interrupt structure of the synchronous transfer is shown in Figure 49. Figure 49 Interrupt Structure of the Synchronous Data Transfer Table 9 Examples for Synchronous Transfer Interrupts Enabled Interrupts (Register MSTI) Generated Interrupts (Register STI) STI STOV STI STOV xy 0 -x y 0 -E x a m p l e 1 -x y 0 --E x a m p l e 2 xy0 xy 1 xy 0 xy 1 Example 3 xy0 xy 0 ; xy1 xy 0 xy 0 ; xy1 Example 4 xy0 ; xy1 xy 0 ; xy1 xy 0 xy1 xy0 xy1 Example 5 xy0 ; xy1 xy 1 xy0 xy1 xy1 Example 6 xy0 ; xy1 xy 0 ; xy1 ; xy2 xy0 xy1 xy0 ; xy2 xy1 ; xy2 Example 7 STI11 MSTI STI STI10 STI20 STI21 STOV10 STOV11 STOV20 STOV21 STI11 STI10 STI20 STI21 STOV10 STOV11 STOV20 STOV21 ACK11 ASTI ACK10 ACK20 ACK21 ST MOS TRAN WOV Interrupt ISTAMASK MOS TRAN WOV ST CICCIC

Description of Functional Blocks Data Sheet 93 2003-02-04 Restrictions Concerning Monitoring and Shifting Data Due to the hardware design, there are some restrictions for the CDA shifting data function and for the CDA monitoring data function. The selection of the CDA registers is restricted if other functional blocks of the SBCX-X (transceiver cores, CI handler, Monitor handler, TIC bus etc.) access the corresponding timeslot. If no functional block is assigned to a certain timeslot, any CDA register can be used for monitoring or shifting it. If a timeslot is already occupied by a functional block in a certain transmission direction, only CDA registers with odd numbers (CDA11/21) can be assigned to odd timeslots and CDA registers with even numbers (CDA10/20) can be assigned to even timeslots in the same transmission direction. For the other transmission direction every CDA register can be used. (Example: If TS 5 is already occupied in DD direction, only CDA11 and 21 can be used for monitoring it. For monitoring TS 5 in DU direction, also CDA10 or CDA20 could be used.) If above guideline is not considered, data can be overwritten in corresponding timeslots. In this context no general rules can be derived in which way the data are overwritten. The usage of the looping data and switching data functions are unrestricted. Restrictions Concerning Read/Write Access If data shall be read out from a certain transmission direction and other data shall be written in the opposite transmission direction in the same timeslot, only special CDA register combinations can be used. The correct behavior can be achieved with the following CDA register combinations: With other register combinations unintended loops or erroneous monitorings can occur or wrong data is written to the IOM interface. Unexpected Write/Read Behavior of CDA Registers If inputs and outputs are disabled, the programmed values of CDA10/11/20/21 registers cannot be read back. Instead of the expected value the content of the previous programming can be read out. The programmed value (5A H in the following example) will be fetched if the output is enabled. Table 10 CDA Register Combinations with Correct Read/Write Access C D A R e g i s t e r C o m b i n a t i o n 1234 Data of the downstream timeslot is read by CDA10 CDA11 CDA20 CDA21 Data is written to the upstream timeslot from CDA20 CDA21 CDA10 CDA11

Description of Functional Blocks Data Sheet 94 2003-02-04 Example: w CDA1_CR = 00H (inputs and outputs are disabled) w CDA10 = 5AH (example) r CDA10 = FFH (old value of previous programming) w CDA1_CR = 02H (output of CDA10 is enabled) r CDA10 = 5AH (the programmed value can be read back)

3.7.2 Serial Data Strobe Si gnal and Strobed Data Clock

For time slot oriented standard devices connected to the IOM-2 interface the SBCX-X provides two independent data strobe signals SDS1 and SDS2. Instead of a data strobe signal a strobed IOM-2 bit clock can be provided on pin SDS1 and SDS2.

3.7.2.1 Serial Data Strobe Signal

The two strobe signals can be generated with every 8-kHz frame and are controlled by the registers SDS1/2_CR. By programming the TSS bits and three enable bits (ENS_TSS, ENS_TSS+1, ENS_TSS+3) a data strobe can be generated for the IOM-2 time slots TS, TS+1 and TS+3 and any combination of them. The data strobes for TS and TS+1 are always 8 bits long (bit7 to bit0) whereas the data strobe for TS+3 is always 2 bits long (bit7, bit6). Figure 51 shows three examples for the generation of a strobe signal. In example 1 the SDS is active during channel B2 on IOM-2 whereas in the second example during IC2 and MON1. The third example shows a strobe signal for 2B+D channels which can be used e.g. for an IDSL (144kbit/s) transmission.

Description of Functional Blocks Data Sheet 95 2003-02-04 Figure 51 Data Strobe Signal FSC DD,DU M R M XD CI0 SDS1,2 (Example1) SDS1,2 (Example2) SDS1,2 (Example3) TSS ENS_TSS ENS_TSS+1 ENS_TSS+3 Example 1: = '0 = '0' = '1' = '0' TSS ENS_TSS ENS_TSS+1 ENS_TSS+3 Example 2: = '5 = '1' = '1' = '0' TSS ENS_TSS ENS_TSS+1 ENS_TSS+3 Example 3: = '0 = '1' = '1' = '1' TS0 TS11TS10TS9TS8TS7TS6TS5TS4TS3TS2TS1 TS0 TS1 B1 B2 MON0 IC1 IC2 MON1 M R M XCI1 strobe.vsd For all examples SDS_CONF.SDS1/2_BCL must be set to “0”.

Description of Functional Blocks Data Sheet 96 2003-02-04

3.7.2.2 Strobed IOM-2 Bit Clock

The strobed IOM-2 bit clock is active during the programmed window. Outside the programmed window a ’0’ is driven. Two examples are shown in Figure 52. Figure 52 Strobed IOM-2 Bit Clock. Register SDS_CONF Programmed to 01 H The strobed bit clock can be enabled in SDS_CONF.SDS1/2_BCL. FSC DD,DU M R M XD CI0 SDS1 (Example1) SDS1 (Example2) TS0 TS11TS10TS9TS8TS7TS6TS5TS4TS3TS2TS1 TS0 TS1 B1 B2 MON0 IC1 IC2 MON1 M R M XCI1 bcl_strobed.vsd TSS ENS_TSS ENS_TSS+1 ENS_TSS+3 Example 1: = '0 = '0' = '0' = '1' TSS ENS_TSS ENS_TSS+1 ENS_TSS+3 Example 2: = '5 = '1' = '1' = '0' Setting of SDS1_CR: For all examples SDS_CONF.SDS1_BCL must be set to “1”.

Description of Functional Blocks Data Sheet 97 2003-02-04

3.7.3 IOM-2 Monitor Channel

The IOM-2 MONITOR channel (see Figure 53) is utilized for information exchange in the MONITOR channel between a master mode device and a slave mode device. The MONTIOR channel data can be controlled by the bits in the MONITOR control register (MON_CR). For the transmission of the MONITOR data one of the IOM-2 channels (3 IOM-2 channels in TE mode, 8 channels in non TE mode) can be selected by setting the MONITOR channel selection bits (MCS) in the MONITOR control register (MON_CR). The DPS bit in the same register selects between an output on DU or DD respectively and with EN_MON the MONITOR data can be enabled/disabled. The default value is MONITOR channel 0 (MON0) enabled and transmission on DD. Figure 53 Examples of MONITOR Channe l Applications in IOM-2 TE Mode The MONITOR channel of the SBCX-X can be used in following applications which are illustrated in Figure 53: A s a master device the SBCX-X can program and control other devices attached to the IOM-2 which do not need a parallel microcontroller interface e.g. ARCOFI-BA PSB 2161. This facilitates redesigning existing terminal designs in which e.g. an interface of an expansion slot is realized with IOM-2 interface and monitor programming. 3086_08 MONITOR Handler Layer 1 V/D Module (e.g. ARCOFI-BA) IOM-2 MONITOR Channel µC MONITOR Handler Layer 1 V/D Module (e.g. ISAR34) IOM-2 MONITOR Channel µCMaster Device MONITOR Handler Layer 1 V/D Module (e.g. ISAR34) IOM-2 MONITOR Channel µC Data Exchange between two µC Systems µC Slave Device

Description of Functional Blocks Data Sheet 98 2003-02-04 A s a slave device the transceiver part of the SBCX-X is programmed and controlled from a master device on IOM-2 (e.g. ISAR 34 PSB 7115). This is used in applications where no microcontroller is connected directly to the SBCX-X in order to simplify host interface connection. The HDLC controlling is processed by the master device therefore the HDLC data is transferred via IOM-2 interface directly to the master device. F o r data exchange between two microcontroller systems attached to two different devices on one IOM-2 backplane. Use of the MONITOR channel avoids the necessity of a dedicated serial communication path between the two systems. This simplifies the system design of terminal equipment.

3.7.3.1 Handshake Procedure

The MONITOR channel operates on an asynchronous basis. While data transfers on the bus take place synchronized to frame sync (FSC), the flow of data is controlled by a handshake procedure using the MONITOR Channel Receive (MR) and MONITOR Channel Transmit (MX) bits. Data is placed onto the MONITOR channel and the MX bit is activated. This data will be transmitted once per 8-kHz frame until the transfer is acknowledged via the MR bit. The MONITOR channel protocol is described in the following section and Figure 54 illustrates this. The relevant control and status bits for transmission and reception are listed in Table 11 and Table 12. Table 11 Transmit Direction Control/ Status Bit Register Bit Function Control MOCR MXC MX Bit Control MIE Transmit Interrupt Enable Status MOSR MDA Data Acknowledged MAB Data Abort MSTA MAC Transmission Active Table 12 Receive Direction Control/ Status Bit Register Bit Function Control MOCR MRC MR Bit Control MRE Receive Interrupt Enable Status MOSR MDR Data Received MER End of Reception

Description of Functional Blocks Data Sheet 99 2003-02-04 Figure 54 MONITOR Channel Protocol (IOM-2) Before starting a transmission, the microprocessor should verify that the transmitter is inactive, i.e. that a possible previous transmission has been terminated. This is indicated by a ’0’ in the MONITOR Channel Active MAC status bit. After having written the MONITOR Data Transmit (MOX) register, the microprocessor sets the MONITOR Transmit Control bit MXC to ’1’. This enables the MX bit to go active (’0’), indicating the presence of valid MONITOR data (contents of MOX) in the corresponding frame. As a result, the receiving device stores the MONITOR byte in its MONITOR Receive MOR register and generates an MDR interrupt status. Alerted by the MDR interrupt, the microprocessor reads the MONITOR Receive (MOR) register. When it is ready to accept data (e.g. based on the value in MOR, which in a point-to-multipoint application might be the address of the destination device), it sets the MR control bit MRC to ’1’ to enable the receiver to store succeeding MONITOR channel bytes and acknowledge them according to the MONITOR channel protocol. In addition, it enables other MONITOR channel interrupts by setting MONITOR Interrupt Enable (MIE) to ’1’. ITD10032 MON MX Transmitter MR 11FF FF 1 1 ADR 0 1 00DATA1 01DATA1 ADR 0 0 DATA1 0 1 DATA1 0 0 00DATA2 01DATA2 DATA2 0 1 DATA2 0 0 FF 1 0 FF 1 0 FF 1 1 FF 1 1 Receiver MIE = 1 MOX = ADR MXC = 1 MAC = 1 MOX = DATA1 MDA Int. MDA Int. MDA Int. MXC = 0 MDR Int. RD MOR (=ADR) MRC = 1 MDR Int. MDR Int. MRC = 0 MER Int. Pµ µP 125 µs RD MOR (=DATA1) RD MOR (=DATA2) MOX = DATA2 MAC = 0

Description of Functional Blocks Data Sheet 100 2003-02-04 As a result, the first MONITOR byte is acknowledged by the receiving device setting the MR bit to ’0’. This causes a MONITOR Data Acknowledge MDA interrupt status at the transmitter. A new MONITOR data byte can now be written by the microprocessor in MOX. The MX bit is still in the active (0) state. The transmitter indicates a new byte in the MONITOR channel by returning the MX bit active after sending it once in the inactive state. As a result, the receiver stores the MONITOR byte in MOR and generates a new MDR interrupt status. When the microprocessor has read the MOR register, the receiver acknowledges the data by returning the MR bit active after sending it once in the inactive state. This in turn causes the transmitter to generate an MDA interrupt status. This "MDA interrupt – write data – MDR interrupt – read data – MDA interrupt" handshake is repeated as long as the transmitter has data to send. Note that the MONITOR channel protocol imposes no maximum reaction times to the microprocessor. When the last byte has been acknowledged by the receiver (MDA interrupt status), the microprocessor sets the MONITOR Transmit Control bit MXC to ’0’. This enforces an inactive (’1’) state in the MX bit. Two frames of MX inactive signifies the end of a message. Thus, a MONITOR Channel End of Reception MER interrupt status is generated by the receiver when the MX bit is received in the inactive state in two consecutive frames. As a result, the microprocessor sets the MR control bit MRC to 0, which in turn enforces an inactive state in the MR bit. This marks the end of the transmission, making the MONITOR Channel Active MAC bit return to ’0’. During a transmission process, it is possible for the receiver to ask a transmission to be aborted by sending an inactive MR bit value in two consecutive frames. This is effected by the microprocessor writing the MR control bit MRC to ’0’. An aborted transmission is indicated by a MONITOR Channel Data Abort MAB interrupt status at the transmitter. The MONITOR transfer protocol rules are summarized in the following section:  A pair of MX and MR in the inactive state for two or more consecutive frames indicates an idle state or an end of transmission. A start of a transmission is initiated by the transmitter by setting the MXC bit to ’1’ enabling the internal MX control. The receiver acknowledges the received first byte by setting the MR control bit to ’1’ enabling the internal MR control.  The internal MX,MR control indicates or acknowledges a new byte in the MON slot by toggling MX,MR from the active to the inactive state for one frame.  Two frames with the MR-bit set to inactive indicate a receiver request for abort.  The transmitter can delay a transmission sequence by sending the same byte continuously. In that case the MX-bit remains active in the IOM-2 frame following the first byte occurrence. Delaying a transmission sequence is only possible while the receiver MR-bit and the transmitter MX-bit are active. S i n c e a double last-look criterion is implemented the receiver is able to receive the MON slot data at least twice (in two consecutive frames), the receiver waits for the acknowledge of the reception of two identical bytes in two successive frames.

Description of Functional Blocks Data Sheet 101 2003-02-04  To control this handshake procedure a collision detection mechanism is implemented in the transmitter. This is done by making a collision check per bit on the transmitted MONITOR data and the MX bit.  Monitor data will be transmitted repeatedly until its reception is acknowledged or the transmission time-out timer expires.  Two frames with the MX bit in the inactive state indicates the end of a message (EOM).  Transmission and reception of monitor messages can be performed simultaneously. This feature is used by the SBCX-X to send back the response before the transmission from the controller is completed (the SBCX-X does not wait for EOM from controller).

3.7.3.2 Error Treatment

In case the SBCX-X does not detect identical monitor messages in two successive frames, transmission is not aborted. Instead the SBCX-X will wait until two identical bytes are received in succession. A transmission is aborted of the SBCX-X if  an error in the MR handshaking occurs  a collision on the IOM-2 bus of the MONITOR data or MX bit occurs  the transmission time-out timer expires A reception is aborted by the device if  an error in the MX handshaking occurs or  an abort request from the opposite device occurs MX/MR Treatment in Error Case In the master mode the MX/MR bits are under control of the microcontroller through MXC or MRC, respectively. An abort is indicated by an MAB interrupt or MER interrupt, respectively. In the slave mode the MX/MR bits are under control of the device. An abort is always indicated by setting the MX/MR bit inactive for two or more IOM-2 frames. The controller must react with EOM. Figure 55 shows an example for an abort requested by the receiver, Figure 56 shows an example for an abort requested by the transmitter and Figure 57 shows an example for a successful transmission.

Description of Functional Blocks Data Sheet 103 2003-02-04

3.7.3.3 MONITOR Channel Programming as a Master Device

As a master device the SBCX-X can program and control other devices attached to the IOM-2 interface. The master mode is selected by default if the serial control interface (SCI) is used by the host. The monitor data is written by the microprocessor in the MOX register and transmitted via IOM-2 DD (DU) line to the programmed/controlled device e.g. ARCOFI-BA PSB 2161 or IEC-Q TE PSB 21911. The transfer of the commands in the MON channel is regulated by the handshake protocol mechanism with MX, MR which is described in the previous chapter Chapter 3.7.3.1. If the transmitted command was a read command the slave device responds by sending the requested data. The data structure of the transmitted monitor message depends on the device which is programmed. Therefore the first byte of the message is a specific address code which contains in the higher nibble a MONITOR channel address to identify different devices. The length of the messages depends on the accessed device and the type of MONITOR command.

3.7.3.4 MONITOR Channel Programming as a Slave Device

In applications without direct host controller connection the SBCX-X must operate in the MONITOR slave mode which can be selected by pinstrapping the microcontroller interface pins according Table 3 respectively in Chapter 3.2. As a slave device the transceiver part of the SBCX-X is programmed and controlled by a master device at the IOM-2 interface. All programming data required by the SBCX-X is received in the MONITOR time slot on the IOM-2 and is transferred in the MOR register. The transfer of the commands in the MON channel is regulated by the handshake protocol mechanism with MX, MR which is described in the previous Chapter 3.7.3.1. The first byte of the MONITOR message must contain in the higher nibble the MONITOR channel address code which is ’1010’ for the SBCX-X. The lower nibble distinguishes between a programming command or an identification command. Identification Command In order to be able to identify unambiguously different hardware designs of the SBCX-X by software, the following identification command is used: The SBCX-X responds to this DD identification sequence by sending a DU identification sequence: DESIGN: six bit code, specific for each device in order to identify differences in operation e.g. 000001 SBCX-X PEB 3081 Version 1.4 D D 1 s t b y t e v a l u e 10100000 D D 2 n d b y t e v a l u e 00000000

Description of Functional Blocks Data Sheet 104 2003-02-04 This identification sequence is usually done once, when the terminal is connected for the first time. This function is used so that the software can distinguish between different possible hardware configurations. However this sequence is not compulsory. Programming Sequence The programming sequence is characterized by a ’1’ being sent in the lower nibble of the received address code. The data structure after this first byte and the principle of a read/ write access to a register is similar to the structure of the serial control interface described in Chapter 3.2.2. For write access the header 43 H/47H can be used and for read access the header 40H/44H. All registers can be read back when setting the R/W bit in the byte for the command/ register address. The SBCX-X responds by sending its IOM-2 specific address byte (A1h) followed by the requested data. Note: Application Hint: It is not allowed to disable the MX- and MR-control in the programming device at the same time! First, the MX-control must be disabled, then the /g109C has to wait for an End of Reception before the MR-control may be disabled. Otherwise, the SBCX-X does not recognize an End of Reception.

3.7.3.5 MONITOR Time-Out Procedure

To prevent lock-up situations in a MONITOR transmission a time-out procedure can be enabled by setting the time-out bit (TOUT) in the MONITOR configuration register (MCONF). An internal timer is always started when the transmitter must wait for the reply of the addressed device. After 5 ms without reply the timer expires and the transmission will be aborted with a EOM (End of Message) command by setting the MX bit to ’1’ for two consecutive IOM-2 frames. D U 1 s t b y t e v a l u e 10100000 DU 2nd byte value 0 1 DESIGN <IDENT> D D 1 s t b y t e v a l u e 10100001 DD 2nd byte value Header Byte DD 3rd byte value R/W Register Address DD 4th byte value Data 1 DD (nth + 3) byte value Data n

Description of Functional Blocks Data Sheet 105 2003-02-04

3.7.3.6 MONITOR Interrupt Logic

Figure 58 shows the MONITOR interrupt structure of the SBCX-X. The MONITOR Data Receive interrupt status MDR has two enable bits, MONITOR Receive interrupt Enable (MRE) and MR bit Control ( MRC). The MONITOR channel End of Reception MER, MONITOR channel Data Acknowledged MDA and MONITOR channel Data Abort MAB interrupt status bits have a common enable bit MONITOR Interrupt Enable MIE. MRE prevents the occurrence of MDR status, including when the first byte of a packet is received. When MRE is active (1) but MRC is inactive, the MDR interrupt status is generated only for the first byte of a receive packet. When both MRE and MRC are active, MDR is always generated and all received MONITOR bytes - marked by a 1-to-0 transition in MX bit - are stored. (Additionally, an active MRC enables the control of the MR handshake bit according to the MONITOR channel protocol.) Figure 58 MONITOR Interrupt Structure ST MOS TRAN WOV Interrupt ISTAMASK ST MOS TRAN WOV MRE MDR MIE MDA MER MAB MOSR MOCR CICCIC

Description of Functional Blocks Data Sheet 106 2003-02-04

3.7.4 C/I Channel Handling

The Command/Indication channel carries real-time status information between the SBCX-X and another device connected to the IOM-2 interface.  One C/I channel (called C/I0) conveys the commands and indications between the layer-1 and the C/I handler of the SBCX-X. It can be accessed by an external layer-2 device e.g. to control the layer-1 activation/deactivation procedures. C/I0 channel access may be arbitrated via the TIC bus access protocol. In this case the arbitration is done in IOM-2 channel 2 (see Figure 41). The C/I0 channel is accessed via register CIR0 (in receive direction, layer-1 to layer- 2) and register CIX0 (in transmit direction, layer-2 to layer-1). The C/I0 code is four bits long. A listing and explanation of the layer-1 C/I codes can be found in Chapter 3.5.4. In the receive direction, the code from layer-1 is continuously monitored, with an interrupt being generated anytime a change occurs (ISTA.CIC). A new code must be found in two consecutive IOM-2 frames to be considered valid and to trigger a C/I code change interrupt status (double last look criterion). In the transmit direction, the code written in CIX0 is continuously transmitted in C/I0.  A second C/I channel (called C/I1) can be used to convey real time status information between the SBCX-X and various non-layer-1 peripheral devices e.g. PSB 2161 ARCOFI-BA. The C/I1 channel consists of four or six bits in each direction.The width can be changed from 4bit to 6bit by setting bit CIX1.CICW. In 4-bit mode 6-bits are written whereby the higher 2 bits must be set to “1” and 6-bits are read whereby only the 4 LSBs are used for comparison and interrupt generation (i.e. the higher two bits are ignored). The C/I1 channel is accessed via registers CIR1 and CIX1. A change in the received C/I1 code is indicated by an interrupt status without double last look criterion. CIC Interrupt Logic Figure 59 shows the CIC interrupt structure. A CIC interrupt may originate – from a change in received C/I channel 0 code (CIC0) or – from a change in received C/I channel 1 code (CIC 1).

Description of Functional Blocks Data Sheet 107 2003-02-04 The two corresponding status bits CIC0 and CIC1 are read in CIR0 register. CIC1 can be individually disabled by clearing the enable bit CI1E in the CIX1 register. In this case the occurrence of a code change in CIR1 will not be displayed by CIC1 until the corresponding enable bit has been set to one. Bits CIC0 and CIC1 are cleared by a read of CIR0. An interrupt status is indicated every time a valid new code is loaded in CIR0 or CIR1. The CIR0 is buffered with a FIFO size of two. If a second code change occurs in the received C/I channel 0 before the first one has been read, immediately after reading of CIR0 a new interrupt will be generated and the new code will be stored in CIR0. If several consecutive codes are detected, only the first and the last code is obtained at the first and second register read, respectively. For CIR1 no FIFO is available. The actual code of the received C/I channel 1 is always stored in CIR1. Figure 59 CIC Interrupt Structure

3.7.5 D-Channel Access Control

D-channel access control is defined to guarantee all connected TEs and HDLC controllers a fair chance to transmit data in the D-channel. Collisions are possible  on the IOM-2 interface if there is more than one HDLC controller connected or  on the S-interface when there is more than one terminal connected in a point to multipoint configuration (NT /g174TE1 … TE8). Both arbitration mechanisms are implemented in the SBCX-X and will be described in the following two chapters. ST MOS TRAN CIC WOV Interrupt ISTAMASK CIC1CI1E CIC0 CIR0CIX1 MOS TRAN WOV ST CIC

Description of Functional Blocks Data Sheet 108 2003-02-04

3.7.5.1 TIC Bus D-Channel Access Control

The TIC bus is imlemented to organize the access to the layer-1 functions provided in the SBCX-X (C/I-channel) and to the D-channel from up to 7 external communication controllers (Figure 60). Note: The TIC Bus can be used in TE/iNT mode only. In other modes it has to be switched off in order not to disturb the layer-1 control. This is done by setting bit DIM 1 in register Mode D and bit 4 in register IOM_CR. For more details please refer to the application note “Reconfigurable PBX”. To this effect the outputs of the D-channel controllers (e.g. ICC - ISDN Communication Controller PEB 2070) are wired-or (negative logic, i.e. a “0” wins) and connected to pin DU. The inputs of the ICCs are connected to pin DD. External pull-up resistors on DU/ DD are required. The arbitration mechanism must be activated by setting TR_MODE2.DIM2-0=00x. Figure 60 Applications of TIC Bus in IOM-2 Bus Configuration The arbitration mechanism is implemented in the last octet in IOM-2 channel 2 of the IOM-2 interface (Figure 61). An access request to the TIC bus may either be generated by software via a µP access to the C/I channel or by one of the D-channel controllers (ICC). A software access request to the bus is effected by setting the BAC bit (CIX0 register) to ’1’. 3081_09 ICC (7) ICC (2) ICC (1) SBCX-X NT TIC-Bus on IOM-2 S-Interface U-Interface ICC

Description of Functional Blocks Data Sheet 109 2003-02-04 In the case of an access request to the C/I channel, the SBCX-X checks the Bus Accessed-bit BAC (bit 5 of last octet of CH2 on DU, see Figure 61) for the status "bus free“, which is indicated by a logical ’1’. If the bus is free, the SBCX-X transmits its individual TIC bus address TAD. The SBCX-X sends its TIC bus address TAD and compares it bit by bit with the value on DU. If a sent bit set to ’1’ is read back as ’0’ because of the access of another source with a lower TAD wishing access to D- or C/ I-channel, the SBCX-X withdraws immediately from the TIC bus, i.e. the remaining TAD bits are not transmitted. The TIC bus is occupied by the device which sends its address error-free. If more than one device attempt to seize the bus simultaneously, the one with the lowest address values wins. This one will set BAC=0 on TIC bus and starts D-channel transmission in the same frame. Figure 61 Structure of Last Octet of Ch2 on DU When the TIC bus is seized by the ICC, the bus is identified to other devices as occupied via the DU Ch2 Bus Accessed-bit state ’0’ until the access request is withdrawn. After a successful bus access, the ICC is automatically set into a lower priority class, that is, a new bus access cannot be performed until the status "bus free" is indicated in two successive frames. If none of the devices connected to the IOM-2 interface request access to the D and C/ I channels, the TIC bus address 7 will be present. The device with this address will therefore have access, by default, to the D and C/I channels. DU

Description of Functional Blocks Data Sheet 110 2003-02-04

3.7.5.2 S-Bus Priority Mechanism for D-Channel

The S-bus access procedure specified in ITU I.430 was defined to organize D-channel access with multiple TEs connected to a single S-bus (Figure 63). To implement collision detection the D (channel) and E (echo) bits are used. The D-channel S-bus condition is indicated towards the IOM-2 interface with the S/G bit, i.e. the availability of the S/T interface D channel is indicated in bit 5 "Stop/Go" (S/G) of the DD last octet of Ch2 channel (Figure 62). S/G = 1 : stop S/G = 0 : go Figure 62 Structure of Last Octet of Ch2 on DD The Stop/Go bit is available to other layer-2 devices connected to the IOM-2 interface to determine if they can access the S/T bus D channel. The access to the D-channel is controlled by a priority mechanism which ensures that all competing TEs are given a fair access chance. This priority mechanism discriminates among the kind of information exchanged and information exchange history: Layer-2 frames are transmitted in such a way that signalling information is given priority (priority class 1) over all other types of information exchange (priority class 2). Furthermore, once a TE having successfully completed the transmission of a frame, it is assigned a lower level of priority of that class. The TE is given back its normal level within a priority class when all TEs have had an opportunity to transmit information at the normal level of that priority class. The priority mechanism is based on a rather simple method: A TE not transmitting layer-2 frames sends binary 1s on the D-channel. As layer-2 frames are delimited by flags consisting of the binary pattern “01111110” and zero bit insertion is used to prevent flag imitation, the D-channel may be considered idle if more than seven consecutive 1s are detected on the D-channel. Hence by monitoring the D echo channel, the TE may determine if the D-channel is currently used by another TE or not. ITD09693 D CI1MON1IC2IC1CI0MON0B2B1 MR MX MX MR S/G A/B A/BS/G Stop/Go Available/Blocked DD EE

Description of Functional Blocks Data Sheet 111 2003-02-04 A TE may start transmission of a layer-2 frame first when a certain number of consecutive 1s has been received on the echo channel. This number is fixed to 8 in priority class 1 and to 10 in priority class 2 for the normal level of priority; for the lower level of priority the number is increased by 1 in each priority class, i.e. 9 for class 1 and 11 for class 2. A TE, when in the active condition, is monitoring the D echo channel, counting the number of consecutive binary 1s. If a 0 bit is detected, the TE restarts counting the number of consecutive binary 1s. If the required number of 1s according to the actual level of priority has been detected, the TE may start transmission of an HDLC frame. If a collision occurs, the TE immediately shall cease transmission, return to the D-channel monitoring state, and send 1s over the D-channel. Figure 63 D-Channel Access Control on the S-Interface 3081_10 D-channel control SBCX-X PEB 3081 NT S-Interface D-Bits E-Bits U-Interface TE 1 TE 2 TE 8 D-channel control SBCX-X PEB 3081 D-channel control SBCX-X PEB 3081

Description of Functional Blocks Data Sheet 112 2003-02-04 S-Bus D-channel Access Control in the SBCX-X The above described priority mechanism is fully implemented in the SBCX-X. For this purpose the D-channel collision detection according to ITU I.430 must be enabled by setting TR_MODE2.DIM2-0 to ’0x1’. In this case the transceiver continuously compares the received E-echo bits with its own transmitted D data bits. Depending on the priority class selected, 8 (priority 8) or 10 (priority 10) consecutive ONEs (high priority level) need to be detected before the transceiver sends valid D-channel data on the upstream D-bits on S. In low priority level 9 (priority 8) or 11 (priority 10) consecutive ONEs are required. The priority class (priority 8 or priority 10) is selected by transferring the appropriate activation command via the Command/Indication (C/I) channel of the IOM-2 interface to the transceiver. If the activation is initiated by a TE, the priority class is selected implicitly by the choice of the activation command. If the S-interface is activated from the NT, an activation command selecting the desired priority class should be programmed at the TE on reception of the activation indication (AI8 or AI10). In the activated state the priority class may be changed whenever required by simply programming the desired activation request command (AR8 or AR10).

3.7.5.3 S-Bus D-Channel Control in LT-T

If the TE frame structure on the IOM-2 interface is selected, the same D-channel access procedures as described in Chapter 3.7.5.2 are used in LT-T mode. For other frame structures used in LT-T mode, D-channel access on S is handled similarly, with the difference that the S/G bit is not available on IOM-2 but only on the S/G bit output pin (SGO).

3.7.5.4 D-Channel Control in the Intelligent NT (TIC- and S-Bus)

In intelligent NT applications (selected via register TR_MODE.MODE2-0) one or more D-channel controllers on the IOM-2 interface share the upstream D-channel with all connected TEs on the S interface. The transceiver incorporates an elaborate statemachine for D-channel priority handling on IOM-2. For the access to the D-channel a similar arbitration mechanism as on the S interface (writing D-bits, reading back E-bits) is performed for all D-channel sources on IOM-2. Due to this an equal and fair access is guaranteed for all D-channel sources on both the S interface and the IOM-2 interface. This arbitration mechanism is only available in IOM-2 TE mode (12 PCM timeslots) per frame with enabled TIC bus. The access to the upstream D-channel is handled via the S/G bit for the HDLC controllers and via E-bit for all connected terminals on S (E-bits are inverted to block the terminals on S). Furthermore, if more than one HDLC source is requesting D-channel access on IOM-2 the TIC bus mechanism is used.

Description of Functional Blocks Data Sheet 113 2003-02-04 The arbiter permanently counts the “1s” in the upstream D-channel on IOM-2. If the necessary number of “1s” is counted and an HDLC controller on IOM-2 requests upstream D-channel access (BAC bit is set to 0), the arbiter allows this D-channel controller immediate access and blocks other TEs on S (E-bits are inverted). Similar as on the S-interface the priority for D-channel access on IOM-2 can be configured to 8 or 10 (TR_CMD.DPRIO). The upstream device can stop all D-channel sources by setting the A/B-bit to 0. The S/ G bit is not evaluated in this mode. The configuration settings of the SBCX-X in intelligent NT applications are summarized in Table 13. Note: For mode selection in the TR_MODE register the MODE1/2 bits are used to select intelligent NT mode, MODE0 selects NT or LT-S state machine. With the configuration settings shown above the SBCX-X in intelligent NT applications provides for equal access to the D-channel for terminals connected to the S-interface and for D-channel sources on IOM-2. For a detailed understanding the following sections provide a complete description on the procedures used by the D-channel priority handler on IOM-2, although it may not be necessary to study that in order to use this mode. Table 13 SBCX-X Configuration Settings in Intelligent NT Applications Configuration Description Configuration Setting Select intelligent NT mode Transceiver Mode Register: TR_MODE.MODE0 = 0 (NT state machine) or TR_MODE.MODE0 = 1 (LT-S state machine) TR_MODE.MODE1 = 1 TR_MODE.MODE2 = 1 Enable S/G bit evaluation Transceiver Mode Register 2: TR_MODE2.DIM2-0 = 001

Description of Functional Blocks Data Sheet 114 2003-02-04 1. NT D-Channel Controller Transmits Upstream In the initial state (’Ready’ state) neither the local D-channel sources on IOM-2 nor any of the terminals connected to the S-bus transmit in the D-channel. The SBCX-X S-transceiver thus receives BAC = “1” (IOM-2 DU line) and transmits S/G = “1” (IOM-2 DD line). The access will then be established according to the following procedure:  Local D-channel source verifies that BAC bit is set to ONE (currently no bus access).  Local D-channel source issues TIC bus address and verifies that no controller with higher priority requests transmission (TIC bus access must always be performed even if no other D-channel sources are connected to IOM-2).  Local D-channel source issues BAC = “0” to block other sources on IOM-2 and to announce D-channel access.  SBCX-X S-transceiver pulls S/G bit to ZERO (’Idle’ state) as soon as n D-bits = ’1’ are counted on IOM-2 (see note) to allow for further D-channel access.  SBCX-X S-transceiver transmits inverted echo channel (E bits) on the S-bus to block all connected S-bus terminals (E = D  Local D-channel source commences with D data transmission on IOM-2 as long as it receives S/G = “0”.  After D-channel data transmission is completed the controller sets the BAC bit to ONE.  SBCX-X S-transceiver transmits non-inverted echo (E = D).  SBCX-X S-transceiver pulls S/G bit to ONE (’Ready’ state) to block the D-channel controller on IOM-2. Note: “Local D-channel source” means any D-channel source on the IOM-2 interface. Right after transmission the S/G bit is pulled to ’1’ until n successive D-bits = ’1’ occur on the IOM-2 interface. As soon as n D-bits = ’1’ are seen, the S/G bit is set to ’0’ and the SBCX-X D-channel controller may start transmission again (if TIC bus is occupied). This allows an equal access for D-channel sources on IOM-2 and on the S interface. The number n depends on configuration settings (selected priority 8 or 10) and the condition of the previous transmission, i.e. if an abort was seen (n = 8 or 10, respectively) or if the last transmission was successful (n = 9 or 11, respectively). Figure 64 illustrates the signal flow in an intelligent NT and the algorithm of the D-channel priority handler on IOM-2 implemented in the SBCX-X.

Description of Functional Blocks Data Sheet 115 2003-02-04 2. Terminal Transmits D-Channel Data Upstream The initial state is identical to that described in the last paragraph. When one of the connected S-bus terminals needs to transmit in the D-channel, access is established according to the following procedure:  SBCX-X S-transceiver (in intelligent NT) recognizes that the D-channel on the S-bus is active.  SBCX-X S-transceiver transfers S-bus D-channel data transparently through to the upstream IOM-2 bus (IOM-2 channel 0). For both cases described above the exchange indicates via the A/B bit (controlled by layer 1) that D-channel transmission on this line is permitted (A/B = “1”). Data transmission could temporarily be prohibited by the exchange when only a single D-channel controller handles more lines (A/B = “0”, ELIC-concept). In case the exchange prohibits D data transmission on this line the A/B bit is set to “0” (block). For U PN applications with S extension this forces the intelligent NT SBCX-X S-transceiver to transmit an inverted echo channel on the S-bus, thus disabling all terminal requests, and switches S/G to A/B, which blocks the D-channel controller in the intelligent NT. Note: Although the SBCX-X S-transceiver operates in LT-S mode and is pinstrapped to IOM-2 channel 0 or 1 it will write into IOM-2 channel 2 at the S/G bit position. Figure 64 Data Flow for Collision Resolution Procedure in Intelligent NT SBCX-X D-channel controller 1 (TE mode timing) U transceiver IOM-2 Masterdevice, e.g. IEC-Q TE DU DD DDDS/G BACD S/G A/B BAC TBA DSD-channel E-channel TE TE TE Exchange DIOM 3081_03 D-channel controller 2 (e.g. ICC PEB2070)

Description of Functional Blocks Data Sheet 116 2003-02-04

3.7.6 Activation/Deactivation of IOM-2 Interface

The IOM-2 interface can be switched off in the inactive state, reducing power consumption to a minimum. In this deactivated state is FSC = ’1’, DCL and BCL = ’0’ and the data lines are ’1’. The IOM-2 interface can be kept active while the S interface is deactivated by setting the CFS bit to "0" (MODE1 register). This is the case after a hardware reset. If the IOM-2 interface should be switched off while the S interface is deactivated, the CFS bit should be set to ’1’. In this case the internal oscillator is disabled when no signal (INFO 0) is present on the S bus and the C/I command is ’1111’ = DIU. If the TE wants to activate the line, it has first to activate the IOM-2 interface either by using the "Software Power Up" function (IOM_CR.SPU bit) or by setting the CFS bit to "0" again. The deactivation procedure is shown in Figure 65. After detecting the code DIU (Deactivate Indication Upstream) the layer 1 of the SBCX-X responds by transmitting DID (Deactivate Indication Downstream) during subsequent frames and stops the timing signals synchronously with the end of the last C/I (C/I0) channel bit of the fourth frame. Figure 65 Deactivation of the IOM-2 Interface The clock pulses will be enabled again when the DU line is pulled low (bit SPU in the IOM_CR register), i.e. the C/I command TIM = "0000" is received by layer 1, or when a non-zero level on the S-line interface is detected (if TR_CONF0.LDD=0). The clocks are turned on after approximately 0.2 to 4 ms depending on the oscillator. IOM/g210-2 Deactiv ated DCDCDCDC DI DI DI DI DI DI DI DI DI B1 B2 D CIO D CIO DCL DD DU FSC IOM/g210-2 ITD09655_s.vsd DRDRDRDRDR

Description of Functional Blocks Data Sheet 117 2003-02-04 DCL is activated such that its first rising edge occurs with the beginning of the bit following the C/I (C/I0) channel. After the clocks have been enabled this is indicated by the PU code in the C/I channel and, consequently, by a CIC interrupt. The DU line may be released by resetting the Software Power Up bit IOM_CR.SPU = ’0’ and the C/I code written to CIX0 before (e.g. TIM or AR8) is output on DU. The SBCX-X supplies IOM-2 timing signals as long as there is no DIU command in the C/I (C/I0) channel. If timing signals are no longer required and activation is not yet requested, this is indicated by programming DIU in the CIX0 register. Figure 66 Activation of the IOM-2 interface ITD09656 FSC DU DD FSC DU DD DCL SPU = 1 SPU = 0 CIC : CIXO = TIM Int. TIM PU B1MXMR 0.2 to 4 ms 132 x DCL TIM TIM PU PU PU PU R IOM -CH1 R IOM -CH2 IOM -CH2 R IOM R -CH1 Note: The value “132 x DCL” is only valid for IOM configurations with 3 IOM channels.

Description of Functional Blocks Data Sheet 118 2003-02-04 Asynchronous Awake (LT-S, NT, Int. NT mode) The transceiver is in power down mode (deactivated state) and MODE1.CFS=1 (TR_CONF0.LDD is don’t care in this case). Due to any signal on the line the level detect circuit will asynchronously pull the DU line on IOM-2 to “0” which is deactivated again after 2 ms if the oscillator is fully operational. If the oscillator is just starting up in operational mode, the 2 ms duration is extended correspondingly.

3.8 Auxiliary Interface

The AUX interface provides various functions, which depend on the operation mode (TE, LT-T, LT-S, NT or intelligent NT mode) selected by pins MODE0 and MODE1/EAW (see Table 14). After reset the pins are switched as inputs until further configuration is done by the host. General Purpose I/O AUX0-2 (TE, Int. NT mode) These pins can be used as programmable I/O lines. As inputs (AOE.OEx=1) the state at the pin is latched in when the host performes read operation to register ARX. As outputs (AOE.OEx=0) the value in register ATX is driven on the pins with a minimum delay after the write operation to this register is performed. They can be configured as open drain (ACFG1.ODx=0) or push/pull outputs (ACFG1.ODx=1). The status (’1’ or ’0’) at output pins can be read back from register ARX, which may be different from the ATX value, e.g. if another device drives a different level. Channel Select CH0-2 (LT-T, LT-S, NT mode) In linecard mode one FSC frame is a multiplex of up to eight IOM-2 channels, each of them consisting of B1-, B2-, MONITOR-, D- and C/I-channel and MR- and MX-bits. One of eight channels on the IOM-2 interface is selected by CH0-2. These pins must be strapped to VDD or VSS according to Table 15. Table 14 AUX Pin Functions Pin TE, Int. NT mode LT-T, LT-S, NT mode AUX0 AUX0 (i/o) CH0 (i) AUX1 AUX1 (i/o) CH1 (i) AUX2 AUX2 (i/o) CH2 (i)

Description of Functional Blocks Data Sheet 119 2003-02-04 For DCL = 1.536 MHz one of the IOM-2 channels 0 - 2 can be selected, for DCL = 4.096 MHz any of the eight IOM-2 channels can be selected. The channel select pins have direct effect on the timeslot selection of the following registers:  TR_TSDP_BC1  TR_TSDP_BC2  TR_CR, TRC_CR  DCI_CR, DCIC_CR M O N _ C R Table 15 IOM-2 Channel Selection CH2 CH1 CH0 Channel on IOM-2 0 000 0 011 0 102 0 113 1 004 1 015 1 106 1 117

Detailed Register Description Data Sheet 120 2003-02-04

4 Detailed Register Description

The register mapping of the SBCX-X is shown in Figure 67. Figure 67 Register Mapping of the SBCX-X The register set ranging from 22 H-3FH pertains to the transceiver and C/I-channel handler registers. 3081_04 (Not used) IOM-2 and MONITOR Handler (Not used) *1) 40h 22h 70h FFh Transceiver, C/I Handler 60h Interrupt, General Configuration 00h

Detailed Register Description Data Sheet 121 2003-02-04 The address range from 40 H-5BH is assigned to the IOM handler with the registers for timeslot and data port selection (TSDP) and the control registers (CR) for the transceiver data (TR), Monitor data (MON), C/I data (CI) and controller access data (CDA), serial data strobe signal (SDS), IOM interface (IOM) and synchronous transfer interrupt (STI). The address range from 5CH-5FH pertains to the MONITOR handler. General interrupt and configuration registers are contained in the address range 60H-65H. The register summaries of the SBCX-X are shown in the following tables containing the abbreviation of the register name and the register bits, the register address, the reset values and the register type (Read/Write). A detailed register description follows these register summaries. The register summaries and the description are sorted in ascending order of the register address. Transceiver, C/I-Channel Handler, Auxiliary Interface N A M E76543210 A D D R R / W R E S reserved 00 21H TR_ MODE2

00000 D I M 2 D I M 1 D I M 0 2 2

CIR0 CODR0 CIC0 CIC1 S/G BAS 2E H RF 3 H CIX0 CODX0 TBA2 TBA1 TBA0 BAC 2E H WF E H CIR1 CODR1 CICW CI1E 2F H RF E H CIX1 CODX1 CICW CI1E 2F H WF E H TR_ CONF0 DIS_ TR BUS EN_ ICV

0 L1SW 0 EXLP LDD 30 H R/W 01H

TR_ CONF1 0R P L L _ ADJ EN_ SFSC 00xxx 3 1 H R/W TR_ CONF2 DIS_ TX PDS 0 RLP 0 0 SGP SGD 32 H R/W 80H

Detailed Register Description Data Sheet 122 2003-02-04 TR_STA RINF SLIP ICV 0 FSYN 0 LD 33 H R0 0 H TR_CMD XINF DPRIO TDDIS PD LP_A 0 34 H R/W 08H SQRR1 MSYN MFEN 0 0 SQR11SQR12SQR13SQR14 35 H R4 0 H SQXR1 0 MFEN 0 0 SQX11SQX12SQX13 SQX14 35 H W4 F H SQRR2 SQR21SQR22SQR23SQR24SQR31SQR32SQR33SQR34 36 H R0 0 H SQXR2 SQX21SQX22SQX23SQX24SQX31SQX32SQX33 SQX34 36 H W0 0 H SQRR3 SQR41SQR42SQR43SQR44SQR51SQR52SQR53SQR54 37 H R0 0 H SQXR3 SQX41SQX42SQX43SQX44SQX51SQX52SQX53 SQX54 37 H W0 0 H ISTATR 0 x x x LD RIC SQC SQW 38 H R0 0 H MASKTR 1 1 1 1 LD RIC SQC SQW 39 H R/W FFH TR_ MODE 0 0 0 0 DCH_ INH MODE MODE MODE 3AH R/W 00H reserved 3B H A C F G 1 00000 O D 2 O D 1 O D 0 3 C H R/W 00H ACFG2 0 0 0 0 ACL LED 0 0 3D H R/W 00H A O E 11111 O E 2 O E 1 O E 0 3 E H R/W FFH A R X ----- A R 2 A R 1 A R 0 3 F H R A T X 00000 A T 2 A T 1 A T 0 3 F H W0 0 H Transceiver, C/I-Channel Handler, Auxiliary Interface N A M E76543210 A D D R R / W R E S

Detailed Register Description Data Sheet 123 2003-02-04 IOM Handler (Timeslot , Data Port Selection, CDA Data and CDA Control Register) N a m e 76543210 A D D R R / W R E S CDA10 Controller Data Access Register (CH10) 40 H R/W FFH CDA11 Controller Data Access Register (CH11) 41 H R/W FFH CDA20 Controller Data Access Register (CH20) 42 H R/W FFH CDA21 Controller Data Access Register (CH21) 43 H R/W FFH CDA_ TSDP10 DPS 0 0 TSS 44 H R/W 00H CDA_ TSDP11 DPS 0 0 TSS 45 H R/W 01H CDA_ TSDP20 DPS 0 0 TSS 46 H R/W 80H CDA_ TSDP21 DPS 0 0 TSS 47 H R/W 81H reserved 48-4B H TR_ TSDP_ BC1 DPS 0 0 TSS 4C H R/W 00H TR_ TSDP_ BC2 DPS 0 0 TSS 4DH R/W 01 H CDA1_ CR

00 E N _

EN_I1 EN_I0 EN_O1EN_O0 SWAP 4E H R/W 00H CDA2_ CR EN_I1 EN_I0 EN_O1EN_O0 SWAP 4F H R/W 00H

Detailed Register Description Data Sheet 124 2003-02-04 IOM Handler (Control Registers, Synchronous Transfer Interrupt Control), MONITOR Handler N a m e 76543210 A D D R R / W R E S TR_CR (CI_CS=0) EN_ D EN_ B2R EN_ B1R EN_ B2X EN_ B1X CS2-0 50 H R/W F8H TRC_CR (CI_CS=1)

00000 C S 2 - 0 5 0 H R/W 00H

DCI_CR (CI_CS=0) DPS_ CI1 EN_ CI1 000000 5 3 H R/W 80H DCIC_CR (CI_CS=1)

00000 C S 2 - 0 5 3 H R/W 00H

MON_CR DPS EN_ MON

000 C S 2 - 0 5 4 H R/W 40H

SDS1_CR ENS_ TSS ENS_ TSS+1 ENS_ TSS+3 TSS 55 H R/W 00H SDS2_CR ENS_ TSS ENS_ TSS+1 ENS_ TSS+3 TSS 56 H R/W 00H IOM_CR SPU DIS_ AW CI_CS TIC_ DIS EN_ BCL CLKM DIS_ OD DIS_ IOM 57H R/W 08H STI STOV STOV STOV STOV STI STI STI STI 58H R0 0 H A S T I 0000 A C K ACK ACK ACK 58H W0 0 H MSTI STOV STOV STOV STOV STI STI STI STI 59H R/W FFH SDS_ CONF

0000 D I O M _

DIOM_ SDS SDS2_ BCL SDS1_ BCL 5AH R/W 00H MCDA MCDA21 MCDA20 MCDA11 MCDA10 5B H RF F H

Detailed Register Description Data Sheet 125 2003-02-04 MOR MONITOR Receive Data 5C H RF F H MOX MONITOR Transmit Data 5C H WF F H M O S R M D R M E R M D A M A B 0000 5 D H R0 0 H M O C R M R E M R C M I E M X C 0000 5 E H R/W 00H M S T A 00000 M A C 0 T O U T 5 F H R0 0 H M C O N F 0000000 T O U T 5 F H W0 0 H Interrupt, General Configuration Registers N A M E76543210 A D D R R / W R E S ISTA 0 0 ST CIC AUX TRAN MOS 0 60 H R0 0 H MASK 1 1 ST CIC AUX TRAN MOS 1 60 H WF F H AUXI 0 0 EAW WOV TIN 0 0 0 61 H R0 0 H AUXM 1 1 EAW WOV TIN 1 1 1 61 H WF F H MODE1 0 0 0 WTC1 WTC2 CFS RSS2 RSS1 62 H R/W 00H M O D E 2 0000 I N T _ POL 0 0 PPSDX 63 H R/W 00H ID 0 0 DESIGN 64 H R0 1 H SRES RES_ CI 0 0 RES_ MON

0 RES_

RES_ TR RES_ RSTO 64H W0 0 H TIMR TMD 0 CNT 65 H R/W 00H reserved 66 H- 6FH

Detailed Register Description Data Sheet 126 2003-02-04

4.1 Transceiver and C/I Registers

4.1.1 TR_MODE2 - Transceiver Mode Register 2

Value after reset: 00H DIM2-0 ... Digital Interface Modes These bits define the characteristics of the IOM Data Ports (DU, DD). The DIM0 bit enables/disables the collission detection. The DIM1 bit enables/disables the TIC bus access. The effect of the individual DIM bits is summarized in the table below. Example: ’010’ selects transparent D-channel, collision detection disabled and TIC bus disabled. TR_ MODE2 0 0 0 0 0 DIM2 DIM1 DIM0 RD/WR (22) DIM2 DIM1 DIM0 Characteristics 0 0 Transparent D-channel, the collission detection is disabled 0 1 Stop/go bit evaluated for D-channel access handling 0 0 Last octet of IOM channel 2 used for TIC bus access 0 1 TIC bus access is disabled 1 xxR e s e r v e d

Detailed Register Description Data Sheet 127 2003-02-04

4.1.2 CIR0 - Command/Indication Receive 0

Value after reset: F3H CODR0 ... C/I Code 0 Receive Value of the received Command/Indication code. A C/I-code is loaded in CODR0 only after being the same in two consecutive IOM-frames and the previous code has been read from CIR0. CIC0 ... C/I Code 0 Change A change in the received Command/Indication code has been recognized. This bit is set only when a new code is detected in two consecutive IOM-frames. It is reset by a read of CIR0. CIC1 ... C/I Code 1 Change A change in the received Command/Indication code in IOM-channel 1 has been recognized. This bit is set when a new code is detected in one IOM-frame. It is reset by a read of CIR0. S/G ... Stop/Go Bit Monitoring Indicates the availability of the upstream D-channel on the S/T interface. 1: Stop 0: Go BAS ... Bus Access Status Indicates the state of the TIC-bus: 0: the SBCX-X itself occupies the D- and C/I-channel 1: another device occupies the D- and C/I-channel Note: The CODR0 bits are updated every time a new C/I-code is detected in two consecutive IOM-frames. If several consecutive valid new codes are detected and CIR0 is not read, only the first and the last C/I code is made available in CIR0 at the first and second read of that register, respectively. CIR0 CODR0 CIC0 CIC1 S/G BAS RD (2E)

Detailed Register Description Data Sheet 128 2003-02-04

4.1.3 CIX0 - Command/Indication Transmit 0

Value after reset: FEH CODX0 ... C/I-Code 0 Transmit Code to be transmitted in the C/I-channel 0. The code is only transmitted if the TIC bus is occupied. If TIC bus is enabled but occupied by another device, only “1s” are transmitted. TBA2-0 ... TIC Bus Address Defines the individual address for the SBCX-X on the IOM bus. This address is used to access the C/I- and D-channel on the IOM interface. Note: If only one device is liable to transmit in the C/I- and D-channels of the IOM it should always be given the address value ’7’. BAC ... Bus Access Control Only valid if the TIC-bus feature is enabled (MODED.DIM2-0). If this bit is set, the SBCX-X will try to access the TIC-bus to occupy the C/I-channel even if no D-channel frame has to be transmitted. It should be reset when the access has been completed to grant a similar access to other devices transmitting in that IOM-channel. Note: Access is always granted by default to the SBCX-X with TIC-Bus Address (TBA2-0, STCR register) ’7’, which has the lowest priority in a bus configuration.

4.1.4 CIR1 - Command/Indication Receive 1

Value after reset: FEH CODR1 ... C/I-Code 1 Receive CICW, CI1E ... C/I-Channel Width, C/I-Channel 1 Interrupt Enable These two bits contain the read back values from CIX1 register (see below). CIX0 CODX0 TBA2 TBA1 TBA0 BAC WR (2E) CIR1 CODR1 CICW CI1E RD (2F)

Detailed Register Description Data Sheet 129 2003-02-04

4.1.5 CIX1 - Command/Indication Transmit 1

Value after reset: FEH CODX1 ... C/I-Code 1 Transmit Bits 7-2 of C/I-channel 1 timeslot. CICW... C/I-Channel Width CICW selects between a 4 bit (’0’) and 6 bit (’1’) C/I1 channel width. The C/I1 handler always reads and writes 6-bit values but if 4-bit is selected, the higher two bits are ignored for interrupt generation. However in write direction the full CODX1 code is transmitted, i.e. the host must write the higher two bits to “1”. CI1E ... C/I-Channel 1 Interrupt Enable Interrupt generation ISTA.CIC of CIR0.CIC1 is enabled (1) or masked (0).

4.1.6 TR_CONF0 - Transceiver Configuration Register 0

Value after reset: 01H DIS_TR ... Disable Transceiver Setting DIS_TR to “1” disables the transceiver. In order to reenable the transceiver again, a transceiver reset must be issued (SRES.RES_TR = 1). The transceiver must not be reenabled by setting DIS_TR from “1” to “0”. For general information please refer to Chapter 3.3.9. BUS ... Point-to-Point / Bus Selection (NT/LT-S/Int. NT mode only) 0: Adaptive Timing (Point-to-Point, extended passive bus). 1: Fixed Timing (Short passive bus). CIX1 CODX1 CICW CI1E WR (2F) TR_ CONF0 DIS_ TR BUS EN_ ICV

0 L1SW 0 EXLP LDD RD/WR (30)

Detailed Register Description Data Sheet 130 2003-02-04 EN_ICV ... Enable Illegal Code Violation 0: normal operation 1: ICV enabled. The receipt of at least one illegal code violation within one multiframe is indicated by the C/I indication ’1011’ (CVR) in two consecutive IOM frames. L1SW ... Enable Layer 1 State Machine in Software 0: Layer 1 state machine of the SBCX-X is used 1: Layer 1 state machine is disabled. The functionality can be realized in software. The commands can be written to register TR_CMD and the status can be read from TR_STA. For general information please refer to Chapter 3.5. EXLP ... External loop In case the analog loopback is activated with C/I = ARL or with the LP_A bit in the TR_CMD register the loop is a 0: internal loop next to the line pins 1: external loop which has to be closed between SR1/2 and SX1/SX2 Note:The external loop is only useful if bit DIS_TX of register TR_CONF2 is set to ’0’. For general information please refer to Chapter 3.3.10. LDD ... Level Detection Discard 0: Automatic clock generation after detection of any signal on the line in power down state 1: No clock generation after detection of any signal on the line in power down state Note: If an interrupt by the level detect circuitry is generated, the microcontroller has to set this bit to ’0’ for an activation of the S/T interface.

Detailed Register Description Data Sheet 131 2003-02-04

4.1.7 TR_CONF1 - Transceiver Configuration Register 1

Value after reset: 0xH RPLL_ADJ ... Receive PLL Adjustment 0: DPLL tracking step is 0.5 XTAL period per S-frame 1: DPLL tracking step is 1 XTAL period per S-frame EN_SFSC ... Enable Short FSC 0: No short FSC is generated 1: A short FSC is generated once per multiframe (every 40th IOM frame) x ... Undefined The value of these bits depends on the selected mode. It is important to note that these bits must not be overwritten to a different value when accessing this register.

4.1.8 TR_CONF2 - Transmitter Configuration Register 2

Value after reset: 80H DIS_TX ... Disable Line Driver 0: Transmitter is enabled 1: Transmitter is disabled For general information please refer to Chapter 3.3.9. TR_ CONF1 0R P L L _ ADJ EN_ SFSC 00xxx R D / W R ( 3 1 ) TR_ CONF2 DIS_ TX PDS 0 RLP 0 0 SGP SGD RD/WR (32)

Detailed Register Description Data Sheet 132 2003-02-04 PDS ... Phase Deviation Select Defines the phase deviation of the S-transmitter. 0: The phase deviation is 2 S-bits minus 7 oscillator periods plus analog delay plus delay of the external circuitry. 1: The phase deviation is 2 S-bits minus 9 oscillator periods plus analog delay plus delay of the external circuitry. For general information please refer to Chapter 3.3.7. RLP ... Remote Line Loop 0: Remote Line Loop open 1: Remote Line Loop closed For general information please refer to Chapter 3.3.10. SGP ... Stop/Go Bit Polarity Defines the polarity of the S/G bit output on pin SGO. 0: low active (SGO=0 means “go”; SGO=1 means “stop”) 1: high active (SGO=1 means “go”; SGO=0 means “stop”) SGD ... Stop/Go Bit Duration Defines the duration of the S/G bit output on pin SGO. 0: active during the D-channel timeslot 1: active during the whole corresponding IOM frame (starts and ends with the beginning of the D-channel timeslot) Note: Outside the active window of SGO (defined in SGD) the level on pin SGO remains in the “stop”-state depending on the selected polarity (SGP), i.e. SGO=1 (if SGP=0) or SGO=0 (if SGP=1) outside the active window.

Detailed Register Description Data Sheet 133 2003-02-04

4.1.9 TR_STA - Transceiver Status Register

Value after reset: 00H Important: This register is used only if the Layer 1 state machine of the SBCX-X is disabled (TR_CONF0.L1SW = 1) and implemented in software! With the SBCX-X layer 1 state machine enabled, the signals from this register are automatically evaluated. For general information please refer to Chapter 3.5. RINF ... Receiver INFO 00: Received INFO 0 01: Received any signal except INFO 0,2,3,4 10: Reserved (NT mode) or INFO 2 (TE mode) 11: Received INFO 3 (NT mode) or INFO 4 (TE mode) SLIP ... SLIP Detected A ’1’ in this bit position indicates that a SLIP is detected in the receive or transmit path. ICV ... Illegal Code Violation 0: No illegal code violation is detected 1: Illegal code violation (ANSI T1.605) in data stream is detected FSYN ... Frame Synchronization State 0: The S/T receiver is not synchronized 1: The S/T receiver has synchronized to the framing bit F LD ... Level Detection 0: No receive signal has been detected on the line. 1: Any receive signal has been detected on the line. TR_ STA RINF SLIP ICV 0 FSYN 0 LD RD (33)

Detailed Register Description Data Sheet 134 2003-02-04

4.1.10 TR_CMD - Transceiver Command Register

Value after reset: 08H Important: This register is only writable if the Layer 1 state machine of the SBCX-X is disabled (TR_CONF0.L1SW = 1)! With the SBCX-X layer 1 state machine enabled, the signals from this register are automatically generated, but nevertheless this register can always be read. DPRIO can also be written in intelligent NT mode. XINF ... Transmit INFO 000: Transmit INFO 0 001: reserved 010: Transmit INFO 1 (TE mode) or INFO 2 (NT mode) 011: Transmit INFO 3 (TE mode) or INFO 4 (NT mode) 100: Send continous pulses at 192 kbit/s alternating or 96 kHz rectangular, respectively (SCP) 101: Send single pulses at 4 kbit/s with alternating polarity corresponding to 2 kHz fundamental mode (SSP) 11x: reserved DPRIO ... D-Channel Priority (always writable in Int. NT mode) 0: Priority Class 1 for D channel access on IOM (Int. NT) or on S interface (TE/LT-T) 1: Priority Class 2 for D channel access on IOM (Int. NT) or on S interface (TE/LT-T) TDDIS ... Transmit Data Disabled (TE mode) 0: The B and D channel data are transparently transmitted on the S/T interface if INFO 3 is being transmitted 1: The B and D channel data are set to logical ’1’ on the S/T interface if INFO 3 is being transmitted PD ... Power Down 0: The transceiver is set to operational mode 1: The transceiver is set to power down mode For general information please refer to Chapter 3.5.1.2. TR_ CMD XINF DPRIO TDDIS PD LP_A 0 RD/WR (34)

Detailed Register Description Data Sheet 135 2003-02-04 LP_A ... Loop Analog The setting of this bit corresponds to the C/I command ARL. 0: Analog loop is open 1: Analog loop is closed internally or externally according to the EXLP bit in the TR_CONF0 register For general information please refer to Chapter 3.3.10.

4.1.11 SQRR1 - S/Q-Channel Receive Register 1

Value after reset: 40H For general information please refer to Chapter 3.3.2. MSYN ... Multiframe Synchronization State 0: The S/T receiver has not synchronized to the received FA and M bits 1: The S/T receiver has synchronized to the received FA and M bits MFEN ... Multiframe Enable Read-back of the MFEN bit of the SQXR register SQR11-14 ... Received S Bits Received S bits in frames 1, 6, 11 and 16 (TE mode) received Q bits in frames 1, 6, 11 and 16 (NT mode). SQRR MSYN MFEN 0 0 SQR11 SQR12 SQR13 SQR14 RD (35)

Detailed Register Description Data Sheet 136 2003-02-04

4.1.12 SQXR1- S/Q-Channel TX Register 1

Value after reset: 4FH MFEN ... Multiframe Enable Used to enable or disable the multiframe structure (see Chapter 3.3.2) 0: S/T multiframe is disabled 1: S/T multiframe is enabled Readback value in SQRR1. SQX11-14 ... Transmitted S/Q Bits Transmitted Q bits (FA bit position) in frames 1, 6, 11 and 16 (TE mode), transmitted S bits (FA bit position) in frames 1, 6, 11 and 16 (NT mode).

4.1.13 SQRR2 - S/Q-Channel Receive Register 2

Value after reset: 00H SQR21-24, SQR31-34... Received S Bits (TE mode only) Received S bits in frames 2, 7, 12 and 17 (SQR21-24, subchannel 2), and in frames 3, 8, 13 and 18 (SQR31-34, subchannel 3). SQXR1 0 MFEN 0 0 SQX11 SQX12 SQX13 SQX14 WR (35) SQRR2 SQR21 SQR22 SQR23 SQR24 SQR31 SQR32 SQR33 SQR34 RD (36)

Detailed Register Description Data Sheet 137 2003-02-04

4.1.14 SQXR2 - S/Q-Channel TX Register 2

Value after reset: 00H SQX21-24, SQX31-34... Transmitted S Bits (NT mode only) Transmitted S bits in frames 2, 7, 12 and 17 (SQX21-24, subchannel 2), and in frames 3, 8, 13 and 18 (SQX31-34, subchannel 3).

4.1.15 SQRR3 - S/Q-Channel Receive Register 3

Value after reset: 00H SQR41-44, SQR51-54... Received S Bits (TE mode only) Received S bits in frames 4, 9, 14 and 19 (SQR41-44, subchannel 4), and in frames 5, 10, 15 and 20 (SQR51-54, subchannel 5).

4.1.16 SQXR3 - S/Q-Channel TX Register 3

Value after reset: 00H SQX41-44, SQX51-54... Transmitted S Bits (NT mode only) Transmitted S bits in frames 4, 9, 14 and 19 (SQX41-44, subchannel 4), and in frames 5, 10, 15 and 20 (SQX51-54, subchannel 5).

4.1.17 ISTATR - Interrupt Status Register Transceiver

Value after reset: 00H SQXR2 SQX21 SQX22 SQX23 SQX24 SQX31 SQX32 SQX33 SQX34 WR (36) SQRR3 SQR41 SQR42 SQR43 SQR44 SQR51 SQR52 SQR53 SQR54 RD (37) SQXR3 SQX41 SQX42 SQX43 SQX44 SQX51 SQX52 SQX53 SQX54 WR (37)

Detailed Register Description Data Sheet 138 2003-02-04 For all interrupts in the ISTATR register the following logical states are defined: 0: Interrupt is not acitvated 1: Interrupt is acitvated x ... Reserved Bits set to “1” in this bit position must be ignored. LD ... Level Detection Any receive signal has been detected on the line. This bit is set to “1” (i.e. an interrupt is generated if not masked) as long as any receiver signal is detected on the line. RIC ... Receiver INFO Change RIC is activated if one of the TR_STA bits RINF or ICV has changed. This bit is reset by reading the TR_STA register. SQC ... S/Q-Channel Change A change in the received S-channel (TE) or Q-channel (NT) has been detected. The new code can be read from the SQRxx bits of registers SQRR1-3 within the duration of the next multiframe (5 ms). This bit is reset by a read access to the corresponding SQRRx register. SQW ... S/Q-Channel Writable The S/Q channel data for the next multiframe is writable. The register for the Q (S) bits to be transmitted (received) has to be written (read) within the duration of the next multiframe (5 ms). This bit is reset by writing register SQXRx.

4.1.18 MASKTR - Mask Transceiver Interrupt

Value after reset: FFH ISTATR 0 x x x LD RIC SQC SQW RD (38) MASKTR 1 1 1 1 LD RIC SQC SQW RD/WR (39)

Detailed Register Description Data Sheet 139 2003-02-04 The transceiver interrupts LD, RIC, SQC and SQW are enabled (0) or disabled (1).

4.1.19 TR_MODE - Transceiver Mode Register 1

Value after reset: 000000xxB For general information please refer also to Chapter 3.7.5.4. DCH_INH ... D-Channel Inhibit (NT, LT-S, Int. NT mode only) Setting this bit to ’1’ has the effect that the S-transceiver blocks the access to the D-channel on S by inverting the E-bits. The pin DCI, which performs the same funtion, is internally combined (EXOR-logic) with DCH_INH, i.e. either setting the bit to ’1’ or pulling the pin high will block the D-channel access, however activating pin and bit simultaneously must not be done. If this bit was not set before, reading DCH_INH reflects the status on pin DCI, i.e. the D-channel inhibit function is controlled by the pin. If the function should be controlled by programming DCH_INH, the pin DCI must be strapped to “0” or “1”. MODE2-0 ... Transceiver Mode 000: TE mode 001: LT-T mode 010: NT mode 011: LT-S mode 110: Intelligent NT mode (with NT state machine) 111: Intelligent NT mode (with LT-S state machine) 100: reserved 101: reserved Note: The three modes TE, LT-T and LT-S can be selected by pin strapping (reset values for bits TR_MODE.MODE0,1 loaded from pins MODE0,1), all other modes are programmable only. TR_ MODE

0000 D C H _

RD/WR (3A)

Detailed Register Description Data Sheet 140 2003-02-04

4.2 Auxiliary Interface Registers

4.2.1 ACFG1 - Auxiliary Configuration Register 1

Value after reset: 00H For general information please refer to Chapter 3.8. OD2-0 ... Output Driver Select for AUX2 - AUX0 0: output is open drain 1: output is push/pull Note: The ODx configuration is only valid if the corresponding output is enabled in the AOE register. AUX0-2 are only available in TE and Int. NT mode and not in all other modes (used as channel select).

4.2.2 ACFG2 - Auxiliary Configuration Register 2

Value after reset: 00H ACL ... ACL Function Select 0: Pin ACL automatically indicates the S-bus activation status by a LOW level. 1: The output state of ACL is programmable by the host in bit LED. Note: An LED with preresistance may directly be connected to ACL. LED ... LED Control If enabled (ACL=1) the LED with preresistance connected between VDD and ACL is switched ... 0: Off (high level on pin ACL) 1: On (low level on pin ACL) ACFG1 0 0 0 0 0 OD2 OD1 OD0 RD/WR (3C) ACFG2 0 0 0 0 ACL LED 0 0 RD/WR (3D)

Detailed Register Description Data Sheet 141 2003-02-04

4.2.3 AOE - Auxiliary Output Enable Register

Value after reset: FFH For general information please refer to Chapter 3.8. OE2-0 ... Output Enable for AUX2 - AUX0 0: Pin AUX2-0 is configured as output. The value of the corresponding bit in the ATX register is driven on AUX2-0. 1: Pin AUX2-0 is configured as input. The value of the corresponding bit can be read from the ARX register. Note: In NT and LT modes the pins AUX0-2 are not available as I/O pins.

4.2.4 ARX - Auxiliary Interface Receive Register

Value after reset: (not defined) AR2-0 ... Auxiliary Receive The value of AR2-0 always reflects the level at pin AUX2-0 at the time when ARX is read by the host even if a pin is configured as output. Note: In NT and LT modes the pins AUX0-2 are not available as I/O pins. AOE 1 1 1 1 1 OE2 OE1 OE0 RD/WR (3E) A R X ----- A R 2 A R 1 A R 0 R D ( 3 F )

Detailed Register Description Data Sheet 142 2003-02-04

4.2.5 ATX - Auxiliary Interface Transmit Register

Value after reset: 00H AT2-0 ... Auxiliary Transmit A ’0’ or ’1’ in AT2-0 will drive a low or a high level at pin AUX2-0 if the corresponding output is enabled in the AOE register. Note: In NT and LT modes the pins AUX0-2 are not available as I/O pins.

4.3 IOM-2 and MONITOR Handler

4.3.1 CDAxy - Controller Data Access Register xy

Data registers CDAxy which can be accessed from the controller. ATX 0 0 0 0 0 AT2 AT1 AT0 WR (3F) CDAxy Controller Data Access Register RD/WR (40-43) Register Register Address Value after Reset CDA10 40 H FFH CDA11 41 H FFH CDA20 42 H FFH CDA21 43 H FFH

Detailed Register Description Data Sheet 143 2003-02-04

4.3.2 XXX_TSDPxy - Time Slot and Data Port Selection for CHxy

This register determines the time slots and the data ports on the IOM-2 interface for the data channels ’xy’ of the functional units ’XXX’ which are Controller Data Access (CDA) and Transceiver (TR). The position of B-channel data from the S-interface is programmed in TR_TSDP_BC1 and TR_TSDP_BC2. DPS ... Data Port Selection 0:The data channel xy of the functional unit XXX is output on DD. The data channel xy of the functional unit XXX is input from DU. 1:The data channel xy of the functional unit XXX is output on DU. The data channel xy of the functional unit XXX is input from DD. Note: For the CDA (controller data access) data the input is determined by the CDA_CRx.SWAP bit. If SWAP = ’0’ the input for the CDAxy data is vice versa to the output setting for CDAxy. If the SWAP = ’1’ the input from CDAx0 is vice versa to the output setting of CDAx1 and the input from CDAx1 is vice versa to the output TSS ... Timeslot Selection Selects one of 32 timeslots (0...31) on the IOM-2 interface for the data channels. Note: The reset values for TR_TSDP_BC1/2 are depending on the mode selection (MODE0/1) and channel selection (CH0-2). XXX_ TSDPxy DPS 0 0 TSS RD/WR (44-4D) Register Register Address Value after Reset CDA_TSDP10 44 H 00H ( = output on B1-DD) CDA_TSDP11 45 H 01H ( = output on B2-DD) CDA_TSDP20 46 H 80H ( = output on B1-DU) CDA_TSDP21 47 H 81H ( = output on B2-DU) TR_TSDP_BC1 4C H 00H ( = transceiver output on B1-DD), see note TR_TSDP_BC2 4D H 01H ( = transceiver output on B2-DD), see note

Detailed Register Description Data Sheet 144 2003-02-04

4.3.3 CDAx_CR - Control Register Controller Data Access CH1x

For general information please refer to Chapter 3.7.1.1. EN_TBM ... Enable TIC Bus Monitoring 0: The TIC bus monitoring is disabled 1: The TIC bus monitoring with the CDAx0 register is enabled. The TSDPx0 register must be set to 08H for monitoring from DU or 88H for monitoring from DD, respectively. (This selection is only valid if IOM_CR.TIC_DIS = 0). EN_I1, EN_I0 ... Enable Input CDAx0, CDAx1 0: The input of the CDAx0, CDAx1 register is disabled 1: The input of the CDAx0, CDAx1 register is enabled EN_O1, EN_O0 ... Enable Output CDAx0, CDAx1 0: The output of the CDAx0, CDAx1 register is disabled 1: The output of the CDAx0, CDAx1 register is enabled SWAP ... Swap Inputs 0: The time slot and data port for the input of the CDAxy register is defined by its own TSDPxy register. The data port for the CDAxy input is vice versa to the output setting for CDAxy. 1: The input (time slot and data port) of the CDAx0 is defined by the TSDP register of CDAx1 and the input of CDAx1 is defined by the TSDP register of CDAx0. The data port for the CDAx0 input is vice versa to the output setting for CDAx1. The data port for the CDAx1 input is vice versa to the output setting for CDAx0. The input definition for time slot and data port CDAx0 are thus swapped to CDAx1 and for CDAx1 to CDAx0. The outputs are not affected by the SWAP bit. CDAx_ CR EN_I1 EN_I0 EN_O EN_O SWA P RD/WR (4E-4F) Register Register Address Value after Reset CDA1_CR 4E H 00H CDA2_CR 4F H 00H

Detailed Register Description Data Sheet 145 2003-02-04 4.3.4 TR_CR - Control Register Transceiver Data (IOM_CR.CI_CS=0) Value after reset: F8H Read and write access to this register is only possible if IOM_CR.CI_CS = 0. EN_D ... Enable Transceiver D-Channel Data EN_B2R ... Enable Transceiver B2 Receive Data EN_B1R ... Enable Transceiver B1 Receive Data EN_B2X ... Enable Transceiver B2 Transmit Data EN_B1X ... Enable Transceiver B1 Transmit Data This register is used to individually enable/disable the D-channel (both RX and TX direction) and the receive/transmit paths for the B-channels of the S-transceiver. 0: The corresponding data path to the transceiver is disabled. 1: The corresponding data path to the transceiver is enabled. Note: “Receive Data” refers to the data which is received on the S interface and forwarded to IOM-2. “Transmit data” refers to the data which is coming from IOM-2 and transmitted on the S interface. CS2-0 ... Channel Select for Transceiver D-channel This register is used to select one of eight IOM channels to which the transceiver D-channel data is related to. Note: The reset value is determined by the channel select pins CH2-0 which are directly mapped to CS2-0. It should be noted that writing TR_CR.CS2-0 will also write to TRC_CR.CS2-0 and therefore modify the channel selection for the transceiver C/I0 data. TR_CR EN_ D EN_ B2R EN_ B1R EN_ B2X EN_ B1X CS2-0 RD/WR (50)

Detailed Register Description Data Sheet 146 2003-02-04 4.3.5 TRC_CR - Control Register Transceiver C/I0 (IOM_CR.CI_CS=1) Value after reset: 00H Write access to this register is possible if IOM_CR.CI_CS = 0 or IOM_CR.CI_CS = 1. Read access to this register is possible only if IOM_CR.CI_CS = 1. CS2-0 ... Channel Select for the Transceiver C/I0 Channel This register is used to select one of eight IOM channels to which the transceiver C/I0 channel data is related to. The reset value is determined by the channel select pins CH2- 0 and the MODE2-bit. 4.3.6 DCI_CR - Control Register for CI1 Handler (IOM_CR.CI_CS=0) Value after reset: 80H Read and write access to this register is only possible if IOM_CR.CI_CS = 0. It should be noted that a writing the DCI_CR register will also perform a write access to DCIC_CR, i.e. the lower 3 bits of DCI_CR will be written to DCIC_CR.CS2-0. DPS_CI1 ... Data Port Selection CI1 Handler Data 0: The CI1 handler data is output on DD and input from DU 1: The CI1 handler data is output on DU and input from DD EN_CI1 ... Enable CI1 Handler Data 0: CI1 handler data access is disabled 1: CI1 handler data access is enabled Note: The timeslot for the C/I1 handler cannot be programmed but is fixed to IOM channel 1. TRC_CR 0 0 0 0 0 CS2-0 RD/WR (50) DCI_CR DPS_ CI1 EN_ CI1

000000 R D / W R ( 5 3 )

Detailed Register Description Data Sheet 147 2003-02-04 4.3.7 DCIC_CR - Control Register for CI0 Handler (IOM_CR.CI_CS=1) Value after reset: 00H Write access to this register is possible if IOM_CR.CI_CS = 0 or IOM_CR.CI_CS = 1. Read access to this register is possible only if IOM_CR.CI_CS = 1. CS2-0 ... Channel Select for C/I0 Handler This register is used to select one of eight IOM channels. If enabled, the data of the C/I0 handler is connected to the corresponding C/I0 timeslot of that IOM channel. The reset value is determined by the channel select pins CH2-0 which are mapped to CS2-0. DCIC_CR 0 0 0 0 0 CS2-0 RD/WR (53)

Detailed Register Description Data Sheet 148 2003-02-04

4.3.8 MON_CR - Control Register Monitor Data

Value after reset: 40H For general information please refer to Chapter 3.7.3. DPS ... Data Port Selection 0: The Monitor data is output on DD and input from DU 1: The Monitor data is output on DU and input from DD EN_MON ... Enable Output 0: The Monitor data input and output is disabled 1: The Monitor data input and output is enabled CS2-0 ... MONITOR Channel Selection 000: The MONITOR data is input/output on MON0 (3rd timeslot on IOM-2) 001: The MONITOR data is input/output on MON1 (7th timeslot on IOM-2) 010: The MONITOR data is input/output on MON2 (11th timeslot on IOM-2) 111: The MONITOR data is input/output on MON7 (31st timeslot on IOM-2) Note: The reset value is determined by the channel select pins CH2-0 which are directly mapped to CS2-0. MON_CR DPS EN_ MON

000 C S 2 - 0 R D / W R ( 5 4 )

Detailed Register Description Data Sheet 149 2003-02-04

4.3.9 SDSx_CR - Control Register Serial Data Strobe x

Value after reset: 00H This register is used to select position and length of the strobe signals. The length can be any combination of two 8-bit timeslot (ENS_TSS, ENS_TSS+1) and one 2-bit timeslot (ENS_TSS+3). ENS_TSS ... Enable Serial Data Strobe of timeslot TSS ENS_TSS+1 ... Enable Serial Data Strobe of timeslot TSS+1 0: The serial data strobe signal SDSx is inactive during TSS, TSS+1 1: The serial data strobe signal SDSx is active during TSS, TSS+1 ENS_TSS+3 ... Enable Serial Data Strobe of timeslot TSS+3 (D-Channel) 0: The serial data strobe signal SDSx is inactive during the D-channel (bit7, 6) of TSS+3 1: The serial data strobe signal SDSx is active during the D-channel (bit7, 6) of TSS+3 TSS ... Timeslot Selection Selects one of 32 timeslots on the IOM-2 interface (with respect to FSC) during which SDSx is active high or provides a strobed BCL clock output (see SDS_CONF.SDS1/ 2_BCL). The data strobe signal allows standard data devices to access a programmable channel. SDSx_CR ENS_ TSS ENS_ TSS+1 ENS_ TSS+3 TSS RD/WR (55-56) Register Register Address Value after Reset SDS1_CR 55 H 00H SDS2_CR 56 H 00H

Detailed Register Description Data Sheet 150 2003-02-04

4.3.10 IOM_CR - Control Register IOM Data

Value after reset: 08H SPU ... Software Power Up 0: The DU line is normally used for transmitting data 1: Setting this bit to ’1’ will pull the DU line to low. This will enforce connected layer 1 devices to deliver IOM-clocking. After a subsequent ISTA.CIC-interrupt (C/I-code change) and reception of the C/I-code ”PU” (Power Up indication in TE-mode) the microcontroller writes an AR or TIM command as C/I-code in the CIX0-register, resets the SPU bit and waits for the following CIC-interrupt. For general information please refer to Chapter 3.7.6. DIS_AW ... Disable Asynchronous Awake (for NT, LT-S and Int. NT mode) Setting this bit to “1” disables the Asynchronous Awake function of the transceiver. CI_CS ... C/I Channel Selection The channel selection for D-channel and C/I-channel is done in the channel select bits CH2-0 of register TR_CR (for the trans ceiver) and DCI_CR (for the C/I-channel controller). 0: A write access to CS2-0 has effect on the configuration of D- and C/I-channel, whereas a read access delivers the D-channel configuration only. 1: A write access to CS2-0 has effect on the configuration of the C/I-channel only, whereas a read access delivers the C/I-channel configuration only. TIC_DIS ... TIC Bus Disable 0: The last octet of IOM channel 2 (12th timeslot) is used as TIC bus (in a frame timing mode with 12 timeslots only). 1: The TIC bus is disabled. The last octet of the last IOM time slot (TS 11) can be used as every time slot. IOM_CR SPU DIS_ AW CI_CS TIC_ DIS EN_ BCL CLKM DIS_ OD DIS_ IOM RD/WR (57)

Detailed Register Description Data Sheet 151 2003-02-04 EN_BCL ... Enable Bit Clock BCL/SCLK 0: The BCL/SCLK clock is disabled 1: The BCL/SCLK clock is enabled. CLKM ... Clock Mode If the transceiver is disabled (DIS_TR = ’1’) or in NT, LT-S and Int. NT mode the DCL from the IOM-2 interface is an input. 0: A double bit clock is connected to DCL 1: A single bit clock is connected to DCL For general information please refer to Chapter 3.7. DIS_OD ... Disable Open Drain Drivers 0: DU/DD are open drain drivers 1: DU/DD are push pull drivers DIS_IOM ... Disable IOM DIS_IOM should be set to ’1’ if external devices connected to the IOM interface should be “disconnected“ e.g. for power saving purposes or for not disturbing the internal IOM connection. However, the SBCX-X internal operation is independent of the DIS_IOM bit. 0: The IOM interface is enabled 1: The IOM interface is disabled. The FSC, DCL clock outputs have high impedance; clock inputs are active; DU, DD data line inputs are switched off and outputs have high impedance; except in TE/LT-T mode the DU line is input (“0”-level causes activation), so the DU pin must be terminated (pull up resistor).

Detailed Register Description Data Sheet 152 2003-02-04

4.3.11 STI - Synchronous Transfer Interrupt

Value after reset: 00H For all interrupts in the STI register the following logical states are applied: 0: Interrupt is not activated 1: Interrupt is activated The interrupts are automatically reset by reading the STI register. For general information please refer to Chapter 3.7.1.1. STOVxy ... Synchronous Transfer Overflow Interrupt Enabled STOV interrupts for a certain STIxy interrupt are generated when the STIxy has not been acknowledged in time via the ACKxy bit in the ASTI register. This must be one (for DPS=’0’) or zero (for DPS=’1’) BCL clocks before the time slot which is selected for the STOV. STIxy ... Synchronous Transfer Interrupt Depending on the DPS bit in the corresponding TSDPxy register the Synchronous Transfer Interrupt STIxy is generated two (for DPS=’0’) or one (for DPS=’1’) BCL clock after the selected time slot (TSDPxy.TSS). Note: STOVxy and ACKxy are useful for synchronizing microcontroller accesses and receive/transmit operations. One BCL clock is equivalent to two DCL clock cycles. STI STOV STOV STOV STOV STI STI STI STI RD (58)

Detailed Register Description Data Sheet 153 2003-02-04

4.3.12 ASTI - Acknowledge Synchronous Transfer Interrupt

Value after reset: 00H For general information please refer to Chapter 3.7.1.1. ACKxy ... Acknowledge Synchronous Transfer Interrupt After an STIxy interrupt the microcontroller has to acknowledge the interrupt by setting the corresponding ACKxy bit to “1”.

4.3.13 MSTI - Mask Synchro nous Transfer Interrupt

Value after reset: FFH For the MSTI register the following logical states are applied: 0: Interrupt is not masked 1: Interrupt is masked For general information please refer to Chapter 3.7.1.1. STOVxy ... Synchronous Transfer Overflow for STIxy Mask bits for the corresponding STOVxy interrupt bits. STIxy ... Synchronous Transfer Interrupt xy Mask bits for the corresponding STIxy interrupt bits. ASTI 0 0 0 0 ACK ACK ACK ACK WR (58) MSTI STOV STOV STOV STOV STI STI STI STI RD/WR (59)

Detailed Register Description Data Sheet 154 2003-02-04

4.3.14 SDS_CONF - Configuration Register for Serial Data Strobes

Value after reset: 00H For general information on SDS1/2_BCL please refer to Chapter 3.7.2. DIOM_INV ... DU/DD on IOM Timeslot Inverted 0: DU/DD are active during SDS1 HIGH phase and inactive during the LOW phase. 1: DU/DD are active during SDS1 LOW phase and inactive during the HIGH phase. This bit has only effect if DIOM_SDS is set to ’1’ otherwise DIOM_INV is don’t care. DIOM_SDS ... DU/DD on IOM Controlled via SDS1 0: The pin SDS1 and its configuration settings are used for serial data strobe only. The IOM-2 data lines are not affected. 1: The DU/DD lines are deactivated during the High/Low phase (selected via DIOM_INV) of the SDS1 signal. The SDS1 timeslot is selected in SDS1_CR. SDSx_BCL ... Enable IOM Bit Clock for SDSx 0: The serial data strobe is generated in the programmed timeslot. 1: The IOM bit clock is generated in the programmed timeslot. SDS_ CONF DIOM_ SDS SDS2_ BCL SDS1_ BCL RD/WR (5A)

Detailed Register Description Data Sheet 155 2003-02-04

4.3.15 MCDA - Monitoring CDA Bits

Value after reset: FFH MCDAxy ... Monitoring CDAxy Bits Bit 7 and Bit 6 of the CDAxy registers are mapped into the MCDA register. This can be used for monitoring the D-channel bits on DU and DD and the ’Echo bits’ on the TIC bus with the same register

4.3.16 MOR - MONITOR Receive Channel

Value after reset: FFH Contains the MONITOR data received in the IOM-2 MONITOR channel according to the MONITOR channel protocol. The MONITOR channel (0-7) can be selected by setting the monitor channel select bit MON_CR.MCS.

4.3.17 MOX - MONITOR Transmit Channel

Value after reset: FFH Contains the MONITOR data to be transmitted in IOM-2 MONITOR channel according to the MONITOR channel protocol.The MONITOR channel (0-7) can be selected by setting the monitor channel select bit MON_CR.MCS MCDA MCDA21 MCDA20 MCDA11 MCDA10 RD (5B) Bit7 Bit6 Bit7 Bit6 Bit7 Bit6 Bit7 Bit6 MOR Monitor Receiver Data RD (5C) MOX Monitor Transmit Data WR (5C)

Detailed Register Description Data Sheet 156 2003-02-04

4.3.18 MOSR - MONITOR Interrupt Status Register

Value after reset: 00H MDR ... MONITOR channel Data Received MER ... MONITOR channel End of Reception MDA ... MONITOR channel Data Acknowledged The remote end has acknowledged the MONITOR byte being transmitted. MAB ... MONITOR channel Data Abort

4.3.19 MOCR - MONITOR Control Register

Value after reset: 00H MRE ... MONITOR Receive Interrupt Enable 0: MONITOR interrupt status MDR generation is masked 1: MONITOR interrupt status MDR generation is enabled MRC ... MR Bit Control Determines the value of the MR bit: 0: MR is always ’1’. In addition, the MDR interrupt is blocked, except for the first byte of a packet (if MRE = 1). 1: MR is internally controlled by the SBCX-X according to MONITOR channel protocol. In addition, the MDR interrupt is enabled for all received bytes according to the MONITOR channel protocol (if MRE = 1). MOSR MDR MER MDA MAB 0 0 0 0 RD (5D) MOCR MRE MRC MIE MXC 0 0 0 0 RD/WR (5E)

Detailed Register Description Data Sheet 157 2003-02-04 MIE ... MONITOR Interrupt Enable MONITOR interrupt status MER, MDA, MAB generation is enabled (1) or masked (0). MXC ... MX Bit Control Determines the value of the MX bit: 0: The MX bit is always ’1’. 1: The MX bit is internally controlled by the SBCX-X according to MONITOR channel protocol.

4.3.20 MSTA - MONITOR Status Register

Value after reset: 00H MAC ... MONITOR Transmit Channel Active The data transmisson in the MONITOR channel is in progress. TOUT ... Time-Out Read-back value of the TOUT bit.

4.3.21 MCONF - MONITOR Configuration Register

Value after reset: 00H TOUT... Time-Out 0: The monitor time-out function is disabled 1: The monitor time-out function is enabled M S T A 00000 M A C 0 T O U T R D ( 5 F ) M C O N F 0000000 T O U T W R ( 5 F )

Detailed Register Description Data Sheet 158 2003-02-04

4.4 Interrupt and General Configuration

4.4.1 ISTA - Interrupt Status Register

Value after reset: 00H For all interrupts in the ISTA register following logical states are applied: 0: Interrupt is not acitvated 1: Interrupt is acitvated ST ... Synchronous Transfer This interrupt is generated to enable the microcontroller to lock on to the IOM timing for synchronous transfers. The source can be read from the STI register. CIC ... C/I Channel Change A change in C/I channel 0 or C/I channel 1 has been recognized. The actual value can be read from CIR0 or CIR1. AUX ... Auxiliary Interrupts Signals an interrupt generated from external awake (pin EAW), watchdog timer overflow (WOV) or from the timer (TIN). The sour ce can be read from the auxiliary interrupt register AUXI. TRAN ... Transceiver Interrupt An interrupt originated in the transceiver in terrupt status register (ISTATR) has been recognized. MOS ... MONITOR Status A change in the MONITOR Status Register (MOSR) has occured. Note: A read of the ISTA register clears none of the interrupts. They are only cleared by reading the corresponding status register. ISTA 0 0 ST CIC AUX TRAN MOS 0 RD (60)

Detailed Register Description Data Sheet 159 2003-02-04

4.4.2 MASK - Mask Register

Value after reset: FFH For the MASK register following logical states are applied: 0: Interrupt is enabled 1: Interrupt is disabled Each interrupt source in the ISTA register can selectively be masked/disabled by setting the corresponding bit in MASK to ’1’. Masked interrupt status bits are not indicated when ISTA is read. Instead, they remain internally stored and pending, until the mask bit is reset to ’0’. Note: In the event of a C/I channel change, CIC is set in ISTA even if the corresponding mask bit in MASK is set, but no interrupt is generated.

4.4.3 AUXI - Auxiliary Interrupt Status Register

Value after reset: 00H For all interrupts in the ISTA register following logical states are applied: 0: Interrupt is not acitvated 1: Interrupt is acitvated EAW ... External Awake Interrupt An interrupt from the EAW pin has been detected. WOV ... Watchdog Timer Overflow Signals the expiration of the watchdog timer, which means that the microcontroller has failed to set the watchdog timer control bits WTC1 and WTC2 (MODE1 register) in the correct manner. A reset pulse has been generated by the SBCX-X. TIN ... Timer Interrupt An interrupt originated from the timer is recognized, i.e the timer has expired. MASK 1 1 ST CIC AUX TRAN MOS 1 WR (60) AUXI 0 0 EAW WOV TIN 0 0 0 RD (61)

Detailed Register Description Data Sheet 160 2003-02-04

4.4.4 AUXM - Auxiliary Mask Register

Value after reset: FFH For the MASK register following logical states are applied: 0: Interrupt is enabled 1: Interrupt is disabled Each interrupt source in the AUXI register can selectively be masked/disabled by setting the corresponding bit in AUXM to ’1’. Masked interrupt status bits are not indicated when AUXI is read. Instead, they remain internally stored and pending, until the mask bit is reset to ’0’.

4.4.5 MODE1 - Mode1 Register

Value after reset: 00H WTC1, 2 ... Watchdog Timer Control 1, 2 After the watchdog timer mode has been selected (RSS = ’11’) the watchdog timer is started. During every time period of 128 ms the microcontroller has to program the WTC1 and WTC2 bit in the following sequence to reset and restart the watchdog timer. If WTC1/2 is not written fast enough in this way, the timer expires and a WOV-interrupt (AUXI register) together with a reset pulse is generated. AUXM 1 1 EAW WOV TIN 1 1 1 WR (61) MODE1 0 0 0 WTC1 WTC2 CFS RSS2 RSS1 RD/WR (62) WTC1 WTC2

Detailed Register Description Data Sheet 161 2003-02-04 CFS ... Configuration Select This bit determines clock relations and recovery on S/T and IOM interfaces. 0: The IOM interface clock and frame signals are always active, "Power Down" state included. The states "Power Down" and "Power Up" are thus functionally identical except for the indication: PD = 1111 and PU = 0111. With the C/I command Timing (TIM) the microcontroller can enforce the "Power Up" state and with C/I command Deactivation Indication (DI) the "Power Down" state is reached again. However, it is also possible to activate the S-interface directly with the C/I command Activate Request (AR 8/10/L) without the TIM command. 1: The IOM interface clock and frame signals are normally inactive ("Power Down"). For activating the IOM-2 clocks the "Power Up" state can be induced by software (IOM_CR.SPU) or by resetting CFS again. After that the S-interface can be activated with the C/I command Activate Request (AR 8/10/L). The "Power Down" state can be reached again with the C/I command Deactivation Indication (DI). Note: After reset the IOM interface is always active. To reach the "Power Down" state the CFS-bit has to be set. For general information please refer to Chapter 3.3.8. RSS2, RSS1... Reset Source Selection 2,1 The SBCX-X reset sources for the RSTO output pin can be selected according to the table below. RSS C/I Code Change EAW Watchdog TimerBit 1 Bit 0 0 0 -- -- -- 0 1 (reserved) 1 0 xx- - 1 1 -- -- x

Detailed Register Description Data Sheet 162 2003-02-04  If RSS = ’00’ no above listed reset source is selected and therefore no reset is generated at RSTO.  Watchdog Timer After the selection of the watchdog timer (RSS = ’11’) the timer is reset and started. During every time period of 128 ms the microcontroller has to program the WTC1 and WTC2 bits in two consecutive bit pattern (see description of the WTC1, 2 bits) otherwise the watchdog timer expires and a reset pulse of 125 µs /g163t/g163250 µs is generated. Deactivation of the watchdog timer is only possible with a hardware reset.  If RSS = ’10’ is selected the following two reset sources generate a reset pulse of 125 µs /g163 t /g163/g32250 µs at the RSTO pin: - External (Subscriber) Awake (EAW) The EAW input pin serves as a request signal from the subscriber to initiate the awake function in a terminal and generates a reset pulse (in TE mode only). - Exchange Awake (C/I Code) A C/I Code change generates a reset pulse. After a reset pulse generated by the SBCX-X and the corresponding interrupt (WOV or CIC) the actual reset source can be read from the ISTA.

4.4.6 MODE2 - Mode2 Register

Value after reset: 00H INT_POL ... Interrupt Polarity Selects the polarity of the interrupt pin INT. 0: low active with open drain characteristic (default) 1: high active with push pull characteristic PPSDX ... Push/Pull Output for SDX (SCI Interface) 0: The SDX pin has open drain characteristic 1: The SDX pin has push/pull characteristic MODE2 0 0 0 0 INT_ POL 0 0 PPSDX RD/WR (63)

Detailed Register Description Data Sheet 163 2003-02-04

4.4.7 ID - Identification Register

Value after reset: 01H DESIGN ... Design Number The design number allows to identify different hardware designs of the SBCX-X by software. 01H: Version 1.4 (all other codes reserved)

4.4.8 SRES - Software Reset Register

Value after reset: 00H RES_xx ... Reset Functional Block xx A reset can be activated on the functional block C/I-handler, Monitor channel, IOM handler, S-transceiver and to pin RSTO. Setting one of these bits to “1” causes the corresponding block to be reset for a duration of 4 BCL clock cycles, except RES_RSTO which is activated for a duration of ID 0 0 DESIGN RD (64) SRES RES_ CI 0 0 RES_ MON RES_ TR RES_ RSTO WR (64)

Detailed Register Description Data Sheet 164 2003-02-04

4.4.9 TIMR - Timer Register

Value after reset: 00H TMD ... Timer Mode The timer can be used in two different modes of operation. 0: Count Down Timer. An interrupt is generated only once after a time period of 1 ... 63 ms. 1: Periodic Timer. An interrupt is periodically generated every 1 ... 63 ms (see CNT). CNT ... Timer Counter 0: Timer off. By writing ’0’ to CNT the timer is immediately stopped. A value different from that determines the time period after which an interrupt will be generated. If the timer is already started with a certain CNT value and is written again before an interrupt has been released, the timer will be reset to the new value and restarted again. An interrupt is indicated to the host in AUXI.TIN. Note: Reading back this value delivers back the current counter value which may differ from the programmed value if the counter is running. TIMR TMD 0 CNT RD/WR (65)

Electrical Characteristics

5 Electrical Characteristics

5.1 Absolute Maximum Ratings

Note: Stresses above those listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. The supply voltage must show a monotonic rise. Parameter Symbol Limit Values Unit min. max. Ambient temperature under bias TA 0+ 7 0 ° C Storage temperature TSTG – 55 150 °C Input/output voltage on any pin with respect to ground VS – 0.3 5.25 V Maximum voltage on any pin with respect to ground Vmax 5.5 V

5.2 DC Characteristics

VDD/VSS = 3.3 V/g32/g177 5%; TA = 0 to 70 °C Parameter Symbol Limit Values Unit Test Condition min. typ. max. H-input level (except pins SR1/2) VIH 2.0 5.25 V L-input level (except pins SR1/2) VIL – 0.3 0.8 V H-output level (except pin XTAL2, SX1/2) VOH 2.4 V IOH = - 400 /g109A L-output level (except pin XTAL2, SX1/2) VOL 0.45 V IOL = 6 mA (DU, DD, C768) IOL = 4.5 mA (ACL) IOL = 2 mA (all others) Input leakage current Output leakage current (all pins except SX1/2,SR1/2,XTAL1/2) ILI ILO ± 1 ± 1 /g109A /g109A 0V< VIN<VDD 0V< VOUT<VDD Power supply current- Power Down - Clocks Off - Clocks On IPD1 IPD2 300 /g109A mA Inputs at VSS / VDD No output loads except SX1,2 (50 /g87/g41 Power supply current - S operational (96 kHz) - B1=00H,B2=FFH, D=0 IOP1 IOP2 IOP3 mA mA mA DCL=1536 kHz DCL=4096 kHz DCL=1536 kHz

5.3 Capacitances

TA = 25 °C, VDD = 3.3 V /g177/g325 % VSSA = 0 V, VSS = 0 V, fc = 1 MHz, unmeasured pins grounded. Parameter Symbol Limit Values Unit Remarks min. max. Input Capacitance I/O Capacitance CIN CI/O pF pF All pins except SX1,2 and XTAL1,2 Output Capacitance against VSS COUT 10 pF pins SX1,2

5.4 Oscillator Specification

Recommended Oscillator Circuits Figure 68 Oscillator Circuits Note: It is important to note that the load capacitance depends on the recommendation XTAL1 Clock Characteristics (external oscillator input) Parameter Symbol Limit Values Unit Frequency f 7.680 MHz Frequency calibration tolerance max. 100 ppm Load capacitance C L max. 40 pF Oscillator mode fundamental Parameter Limit Values min. max. Duty cycle 1:2 2:1 ITS09659 N.C. Oscillator External Signal Crystal Oscillator Mode Driving from External Source 4141 pF33 33 pF CL LC

5.5 AC Characteristics

TA = 0 to 70 °C, VDD = 3.3 V /g177 5 % Inputs are driven to 2.4 V for a logical "1" and to 0.45 V for a logical "0". Timing measurements are made at 2.0 V for a logical "1" and 0.8 V for a logical "0". The AC testing input/output waveforms are shown in Figure 69. Figure 69 Input/Output Waveform for AC Tests ITS09660 = 100LoadC Test Under Device 0.45 2.4 2.0 0.80.8 2.0 Test Points pF

5.6 IOM-2 Interface Timing

Data is transmitted with the rising edge of DCL and sampled with its falling edge. Below figure shows double clock mode timing (the length of a timeslot is 2 DCL cycles), however, the timing parameters are valid both in single and double clock mode. For the direction of DU,DD (input or output) please refer to Chapter 3.4. Figure 70 IOM-2 Timing (TE mode)

Figure 71 IOM-2 Timing (LT-S, LT-T, NT mode) Parameter Symbol Limit Values Unit min. max. IOM output data delay t IOD 60 ns IOM input data setup t IIS 4n s IOM input data hold t IIH 3n s FSC strobe delay (see note) t FSD -135 15 ns Strobe signal delay t SDD 50 ns BCL delay t BCD 30 ns Frame sync setup t FSS 20 ns Frame sync hold t FSH 30 ns Frame sync width t FSW 40 ns t FSS t FSH t FSW FSC (I) DCL (I) DU/DD (I) IIHt IISt DU/DD (O) Bit 0 Bit 0 SDDt SDS (O) t IOD ITT09680 t FSS t FSH

Note: Min. value in synchronous state, max. value in non-synchronous state. This results in a phase shift of FSC when the S-Bus gets activated, this is the FSC signal is shifted by 135 ns. This applies only to TE mode. DCL Clock Output Characteristics Figure 72 Definition of Clock Period and Width DCL Clock Input Characteristics Symbol Limit Values Unit Test Condition min. typ. max. tP 585 651 717 ns osc /g177 100 ppm tWH 260 325 391 ns osc /g177 100 ppm tWL 260 325 391 ns osc /g177 100 ppm Parameter Limit Values Unit min. max. Duty cycle 40 60 % 2.3 V

5.7 Serial Control Interface (SCI) Timing

min. max. SCL cycle time t1 200 ns SCL high time t2/g32 100 ns SCL low time t3/g32 100 ns CS setup time t4/g32 2n s CS hold time t5 10 ns SDR setup time t6/g32 10 ns SDR hold time t7/g32 6n s SDX data out delay t8/g32 30 ns CS high to SDX tristate t9 40 ns CS SCL SDR SDX t4 t2 t3 t6 t7

5.8 Reset

Figure 74 Reset Signal RES Parameter Symbol Limit Values Unit Test Conditions min. Length of active low state tRES 4 ms Power On/Power Down to Power Up (Standby) 2 x DCL clock cycles During Power Up (Standby) 21150_26 RES t RES

5.9 S-Transceiver

Parameter Symbol Limit Values Unit Test Condition min. typ. max. VDD= 3.3 V /g177 5 %; VSS= 0 V; TA = 0 to 70 °C Absolute value of output pulse amplitude | VSX2 – VSX1 | V X 1.17 V RL = /g165 Transmitter output current IX 26 mA RL = 5.6 /g87 Transmitter output impedance (SX1,2) ZX 10 k/g87 /g87 Inactive or during binary one; during binary zero R L = 50 /g87 Receiver Input impedance (SR1,2) ZR 30 k /g87VDD = 3.3 V

5.10 Recommended Transformer Specification

Note: In TE/LT-T mode, at the pulse shape measurement with a load of 400 /g87 (e.g. K 1403 approval test “Pulse shape”) overshots might occur with a leakage inductance greater than 6 /g109H. Parameter Symbol Limit Values Unit Test Condition min. typ. max. Transformer ratio 1:1 Main inductance L 25 mH mH no DC current, 10 kHz 2.5 mA DC current, 10 kHz Leakage inductance L L 8 µH µH NT/LT-S mode, 10 kHz TE/LT-T mode, 10 kHz Capacitance between primary and secondary side C8 0 p F 1 k H z Copper resistance R 1.7 2.0 2.3 W

5.11 Line Overload Protection

The maximum input current for the S-transceiver lines (under overvoltage conditions) is given as a function of the width of a rectangular input current pulse. The desctruction limits are shown in Figure 75. Figure 75 Maximum Line Input Current 21150_35 t [s]10-8 10-7 10-6 10-5 10-4 10-3 10-2 i [A] 1.5 0.80 0.65 0.52 0.40

5.12 EMC / ESD Aspects

To improve performance with respect to EMC and ESD requirements it is recommended to provide additional capacitors in the middle tap of the transformers (see Figure 76 either on the chip side of the transformer (option 1) or on the S bus side (option 2), but not on both sides. This improves EMC immunity acording to EN55024 which is mandatory since 2001-07- 01. Note: The figure does not show any other components required for protection circuit in receive and transmit direction as this is not affected by including C1 and C2. Figure 76 Transformer Circuitry AC AC AC Ck1 Cp2Cp1 Cp4Cp3 Ck4 Transmitter (NT) Transmitter (TE) SR1 SR2 SX1 SX2 Ck2 Ck3 Test Generator 0.15MHz - 80MHz carrier with 1 kHz, 80% amplitude modulated signal Couple Capacity: Ck1 /g185 Ck2 /g185 Ck3 /g185 Ck4 Parasitic Capacity: Cp1 /g185 Cp2 /g185 Cp3 /g185 Cp4 Test Setup C1, C2 required to supress common mode signals (option 1) C1 and C2 are also possible at this position (option 2) 21150_34

6 Package Outlines

Does not include plastic or metal protrusion of 0.25 max. per side D D 1Index Marking 0.6 x 45˚ 13.2 A 0.3 +0.15 0.8 B D 0.2 0.2 A-B A-B 0.25 MIN. A-B0.2 C M 2.45 MAX. CD 0.1 44x +0.1 -0.052 ±0.15 44x 4xH H 0.88 0.15 MAX.7˚ -0.02 +0.08 13.2 10 1) P-MQFP-44 (Plastic Metric Quad Flat Package) GPM05622 You can find all of the current packages, types of packing, and others on the Infineon Internet Page “Products”: http://www.infineon.com/products. Dimensions in mmSMD = Surface Mounted Device

(Plastic Thin Quad Flat Package) GPP05612 You can find all of the current packages, types of packing, and others on the Infineon Internet Page “Products”: http://www.infineon.com/products. Dimensions in mmSMD = Surface Mounted Device

Transceiver, C/I-Channel Handler, Auxiliary Interface N A M E76543210 A D D R R / W R E S reserved 00 H- 21H TR_ MODE2 CIR0 CODR0 CIC0 CIC1 S/G BAS 2E H RF 3 H CIX0 CODX0 TBA2 TBA1 TBA0 BAC 2E H WF E H CIR1 CODR1 CICW CI1E 2F H RF E H CIX1 CODX1 CICW CI1E 2F H WF E H TR_ CONF0 DIS_ TR BUS EN_ ICV TR_ CONF1 0R P L L _ ADJ EN_ SFSC 00xxx 3 1 H R/W TR_ CONF2 DIS_ TX PDS 0 RLP 0 0 SGP SGD 32 H R/W 80H TR_STA RINF SLIP ICV 0 FSYN 0 LD 33 H R0 0 H TR_CMD XINF DPRIO TDDIS PD LP_A 0 34 H R/W 08H SQRR1 MSYN MFEN 0 0 SQR11SQR12SQR13SQR14 35 H R4 0 H SQXR1 0 MFEN 0 0 SQX11SQX12SQX13 SQX14 35 H W4 F H SQRR2 SQR21SQR22SQR23SQR24SQR31SQR32SQR33SQR34 36 H R0 0 H SQXR2 SQX21SQX22SQX23SQX24SQX31SQX32SQX33 SQX34 36 H W0 0 H SQRR3 SQR41SQR42SQR43SQR44SQR51SQR52SQR53SQR54 37 H R0 0 H SQXR3 SQX41SQX42SQX43SQX44SQX51SQX52SQX53 SQX54 37 H W0 0 H

ISTATR 0 x x x LD RIC SQC SQW 38 H R0 0 H MASKTR 1 1 1 1 LD RIC SQC SQW 39 H R/W FFH TR_ MODE 0 0 0 0 DCH_ INH MODE MODE MODE 3AH R/W 00H reserved 3B H A C F G 1 00000 O D 2 O D 1 O D 0 3 C H R/W 00H ACFG2 0 0 0 0 ACL LED 0 0 3D H R/W 00H A O E 11111 O E 2 O E 1 O E 0 3 E H R/W FFH A R X ----- A R 2 A R 1 A R 0 3 F H R A T X 00000 A T 2 A T 1 A T 0 3 F H W0 0 H IOM Handler (Timeslot , Data Port Selection, CDA Data and CDA Control Register) N a m e 76543210 A D D R R / W R E S CDA10 Controller Data Access Register (CH10) 40 H R/W FFH CDA11 Controller Data Access Register (CH11) 41 H R/W FFH CDA20 Controller Data Access Register (CH20) 42 H R/W FFH CDA21 Controller Data Access Register (CH21) 43 H R/W FFH CDA_ TSDP10 DPS 0 0 TSS 44 H R/W 00H CDA_ TSDP11 DPS 0 0 TSS 45 H R/W 01H CDA_ TSDP20 DPS 0 0 TSS 46 H R/W 80H Transceiver, C/I-Channel Handler, Auxiliary Interface N A M E76543210 A D D R R / W R E S

CDA_ TSDP21 DPS 0 0 TSS 47 H R/W 81H reserved 48-4B H TR_ TSDP_ BC1 DPS 0 0 TSS 4C H R/W 00H TR_ TSDP_ BC2 DPS 0 0 TSS 4DH R/W 01 H CDA1_ CR EN_I1 EN_I0 EN_O1EN_O0 SWAP 4E H R/W 00H CDA2_ CR EN_I1 EN_I0 EN_O1EN_O0 SWAP 4F H R/W 00H IOM Handler (Control Registers, Synchronous Transfer Interrupt Control), MONITOR Handler N a m e 76543210 A D D R R / W R E S TR_CR (CI_CS=0) EN_ D EN_ B2R EN_ B1R EN_ B2X EN_ B1X CS2-0 50 H R/W F8H TRC_CR (CI_CS=1) DCI_CR (CI_CS=0) DPS_ CI1 EN_ CI1 000000 5 3 H R/W 80H DCIC_CR (CI_CS=1) MON_CR DPS EN_ MON SDS1_CR ENS_ TSS ENS_ TSS+1 ENS_ TSS+3 TSS 55 H R/W 00H

SDS2_CR ENS_ TSS ENS_ TSS+1 ENS_ TSS+3 TSS 56 H R/W 00H IOM_CR SPU DIS_ AW CI_CS TIC_ DIS EN_ BCL CLKM DIS_ OD DIS_ IOM 57H R/W 08H STI STOV STOV STOV STOV STI STI STI STI 58H R0 0 H A S T I 0000 A C K ACK ACK ACK 58H W0 0 H MSTI STOV STOV STOV STOV STI STI STI STI 59H R/W FFH SDS_ CONF DIOM_ SDS SDS2_ BCL SDS1_ BCL 5AH R/W 00H MCDA MCDA21 MCDA20 MCDA11 MCDA10 5B H RF F H MOR MONITOR Receive Data 5C H RF F H MOX MONITOR Transmit Data 5C H WF F H M O S R M D R M E R M D A M A B 0000 5 D H R0 0 H M O C R M R E M R C M I E M X C 0000 5 E H R/W 00H M S T A 00000 M A C 0 T O U T 5 F H R0 0 H M C O N F 0000000 T O U T 5 F H W0 0 H Interrupt, General Configuration Registers N A M E76543210 A D D R R / W R E S ISTA 0 0 ST CIC AUX TRAN MOS 0 60 H R0 0 H MASK 1 1 ST CIC AUX TRAN MOS 1 60 H WF F H AUXI 0 0 EAW WOV TIN 0 0 0 61 H R0 0 H AUXM 1 1 EAW WOV TIN 1 1 1 61 H WF F H MODE1 0 0 0 WTC1 WTC2 CFS RSS2 RSS1 62 H R/W 00H

M O D E 2 0000 I N T _ POL 0 0 PPSDX 63 H R/W 00H ID 0 0 DESIGN 64 H R0 1 H SRES RES_ CI 0 0 RES_ MON RES_ TR RES_ RSTO 64H W0 0 H TIMR TMD 0 CNT 65 H R/W 00H reserved 66 H- 6FH Interrupt, General Configuration Registers N A M E76543210 A D D R R / W R E S

A Absolute maximum ratings 165 AC characteristics 169 ACFG1 register 140 ACFG2 register 140 ACKxy bits 153 ACL bit 140 Activation 76 Activation indication - pin ACL 35 Activation LED 35 Activation/deactivation of IOM-2 interface 116 AOE register 141 Appendix 180 Applications 16 AR2-0 bits 141 Architecture 23 ARX register 141 ASTI register 153 Asynchronous awake 118 AT2-0 bits 142 ATX register 142 AUX bit 158 AUXI register 159 Auxiliary interface 118 AUXM register 160 B BAC bit 128 BAS bit 127 BUS bit 129 C C/I channel 106 Capacitances 167 CDA_TSDPxy registers 143 CDAx_CR register 144 CDAxy registers 142 CFS bit 160 CI_CS bit 150 CI1E bit 128 CIC bit 158 CIC1/0 bits 127 CICW bit 128 CIR0 register 127 CIR1 register 128 CIX0 register 128 CIX1 register 129 CLKM bit 150 Clock generation 53 CNT bits 164 CODR0 bits 127 CODR1 bits 128 CODX0 bits 128 CODX1 bits 129 Control of layer-1 58 Controller data access 84 D DC characteristics 166 DCH_INH bit 139 D-channel access control Intelligent NT 112 S-bus D-channel control in LT-T 112 S-bus priority mechanism 110 TIC bus 108 DCI_CR register 146 Deactivation 76 Delay between IOM-2 and S 42 DESIGN bits 163 Device architecture 23 DIM2-0 bits 126 DIS_AW bit 150 DIS_IOM bit 150 DIS_OD bit 150 DIS_TR bit 129 DIS_TX bit 131 DPRIO bit 134 DPS bit 143, 148 DPS_CI1 bit 146 E EAW bit 159 Electrical characteristics 165 EN_B2/1R bits 145

EN_B2/1X bits 145 EN_BCL bit 150 EN_CI1 bit 146 EN_D bit 145 EN_I0 bit 144 EN_I1 bit 144 EN_ICV bit 129 EN_MON bit 148 EN_O0 bit 144 EN_O1 bit 144 EN_SFSC bit 131 EN_TBM bit 144 ENS_TSSx bits 149 Exchange awake 32 EXLP bit 129 External reset input 32 F Features 14 FSYN bit 133 Functional blocks 23 I I/O lines 118 ICV bit 133 ID register 163 INT_POL bit 162 Intelligent NT 112 Interrupt structure 29 IOM_CR register 150 IOM-2 79 Frame structure (LT) 81 Frame structure (NT) 81 Frame structure (TE) 80 Handler 82 Interface Timing 169 LT-S, LT-T, NT modes 79 Monitor channel 97 TE mode 79 ISTA register 158 ISTATR register 137 J Jitter 56 L L1SW bit 129 LD bit 133, 137 LDD bit 129 LED bit 140 LED output 35 Level detection 50 Logic symbol 15 Looping data 85 LP_A bit 134 LT-T mode 112 M MAB bit 156 MAC bit 157 MASK register 159 MASKTR register 138 MCDA register 155 MCDAxy bits 155 MCONF register 157 MDA bit 156 MDR bit 156 MER bit 156 MFEN bit 135, 136 Microcontroller interfaces 25 MIE bit 156 MOCR register 156 MODE1 register 160 MODE2 register 162 MODE2-0 bits 139 MON_CR register 148 Monitor channel Error treatment 101 Handshake procedure 98 Interrupt logic 105 Master device 103 Slave device 103 Time-out procedure 104 Monitoring data 89

O OD2-0 bits 140 OE2-0 bits 141 Oscillator 168 Oscillator clock output 57 Overview 11 P Package Outlines 178 PD bit 134 PDS bit 131 Pin configuration 17 PPSDX bit 162 R Receive PLL 56 Register description 120 RES_xxx bits 163 Reset generation 31 Reset source selection 31 Reset timing 173 RIC bit 137 RINF bits 133 RLP bit 131 RPLL_ADJ bit 131 RSS2/1 bits 160 S S/G bit 114, 127 S/T-Interface 36 Circuitry 47 Coding 38 Delay compensation 50 External protection circuitry 47 Multiframing 40 Receiver characteristics 46 Transceiver enable/disable 50 Transmitter characteristics 45 S-bus priority mechanism 110 SCI - serial control interface 26 SCI interface timing 172 SDS 94 SDS_CONF register 154 SDS2/1_BCL bits 154 SDSx_CR registers 149 Serial data strobe 94 SGD bit 131 SGP bit 131 Shifting data 85 SLIP bit 133 Software reset 32 SPU bit 150 SQC bit 137 SQR11-14 bits 135 SQR21-24 bits 136 SQR31-34 bits 136 SQR41-44 bits 137 SQR51-54 bits 137 SQRR1 register 135 SQRR2 register 136 SQRR3 register 137 SQW bit 137 SQX11-14 bits 136 SQX21-24 137 SQX31-34 bits 137 SQX41-44 bits 137 SQX51-54 bits 137 SQXR1 register 136 SQXR2 register 137 SQXR3 register 137 SRES register 163 ST bit 158 State machine

STIxy bits 152, 153 Stop/Go bit 114, 127 STOVxy bits 152, 153 Strobed data clock 94 Subscriber awake 32 SWAP bit 144 Synchronous transfer 90 T TBA2-0 bits 128 TDDIS bit 134 Test functions 51 TIC bus 108 TIC_DIS bit 150 Timer 33 TIMR register 164 TIN bit 159 TMD bit 164 TOUT bit 157 TR_CMD register 134 TR_CONF0 register 129 TR_CONF1 register 131 TR_CONF2 register 131 TR_CR register 145 TR_MODE register 139 TR_MODE2 register 126 TR_STA register 133 TR_TSDP_BC1/2 registers 143 TRAN bit 158 Transceiver enable/disable 50 Transformer specification 175 TSS bits 143, 149 Typical applications 16 W Watchdog timer 32 WOV bit 159 WTC1/2 bits 160 X XINF bits 134

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