PEB2050-N | DigiCamel IC Datasheet

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PEB2050 SIEMENS | Alldatasheet

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Technical content

Features

@ Board controller for up to 16 subscribers of a digital switching system @ Designed for different PCM systems @ Time-siot assignment freely programmable for all subscribers connected @ Control of voice, data, signaling and line board parameters to minimize hardware require- ments and to simplify software @ Provides two full duplex PCM highways for the system interface @ System control uses the HDLC protocol with X.25 level 2 functions performed by the PBC @ Standard pP interface @ Two DMA channels for expansion of internal buffer capability of 16 bytes per direction @ uP access to all internal data streams including time-slot oriented data streams @ Support of subscriber circuits by generating timing signals @ Single +5 V power supply @ Low power consumption 136

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a Pin Definitions and Functions Pin No.| Pin No. Function PL-CC | P-DIP ) 1 SIP 4 Subscriber These interface ports are used for bi- : . interface port directional, bit-serial transfer of speech, . . (input/output) data and control words to and from the . . signal processing codec Fitter (SICOF) . . or standard codec. Corresponding with

4 SIP7 the direction signal, the PBC PEB 2050

is transmitting during the high level of DIR within the first half of a 125 ps frame. 5 5 RxHWD 1 | Receive highway | Receive PCM highway 1 interface. data (input) 6 6 RxHWD0 | Receive highway | Receive PCM highway 0 interface. data (input) The PBC serially receives a PCM word (8 bits) through one of these leads at the programmed time slot. 7 7 TxHWD 1 | Transmit highway | Output of the transmit side onto the data (output) send PCM highway 1 (serial bus). The 8-bit PCM word is serially sent out on this pin at the programmed time slot. Tristate output.

8 TSC1 Tristate control Normally high, this signal goes low

(output, active low) | while the PBC is transmitting an 8-bit PCM word on the PCM highway 1.

9 TxHWD 0 | Transmit highway | Output of the transmit side onto the

data (output) send PCM highway 0. 10 TSTO Tristate control Tristate control of highway 0. (output, active low) "1 "1 SYP Synchronization SYP is a frame synchronization pulse which resets the on-chip time-slot counters. 12 SCLK Slave clock Clock output for the peripheral devices. (output) The signals between the codec filter and the PBC are latched and transmit- ted with the rising edge of SCLK.

13 SIGS/DMIR | Signal strobe (out- | The SIGS output supplies a program-

put, active high)/ mable strobe signal. In the DMA mode, direct memory input | this pin is used as DMA input request. request (output, active high) Siemens Components, Inc. 138

Pin Definitions and Functions (cont'd) Pin No. | Pin No. Function PL-CC | P-DIP 14 14 DIR/DMOR | Direction DIR isan8-kHzsymmetricframe signal (output, active which controls the direction of data high)/direct transfer from and to the peripheral memory output devices. The PBC is able to receive request (output, data during the low state of DIR. active high) In the DMA mode this pin is used as DMA output request. DMIR and DMOR are generated by the PBC-internal HDLC receiver or trans- mitter and are used for handshaking during the DMA transfer. 15 15 TxSD Transmit signaling | This line transmits the serial data to the data (output) dedicated HDLC channel. 16 16 TSC 2 Tristate control to 2 | Normally high, this signal goes low (output, active low) | while the PBC is transmitting an HDLC message. 17 17 Receive signaling | This line receives the serial data from data (input) the HDLC channel. 19 18 cs Chip select CS is used to address the PBC. A low (input, active low) | level at this input enables the PBC to accept commands or data from a pP within a write cycle, or to transmit data during a read cycle.

20 ALE Address latch A high level at this input indicates that

enable (input, the data on the external bus is an | active high) address selecting one of the PBC-inter- nal sources or destinations. Latching into the address latch occurs during the high-low transition. 2 jz [vs | Grounctiowy 25 21 CLK Clock Astandard TTL clock provides the basic (input) timing of the controller. The clock is synchronous to the PCM clock. 26 22 RD Read strobe RD is used together with CS to transfer (input, active low) | data from the PBC to a uP or memory. Siemens Components, Inc. 139

36 WR Write strobe During the low state of WR data can be

(input, active low) | transferred from the 4P or memory to the PBC.

37 DACKO DMA acknow- DACK 0 and DACK 7 are used to

Jedge (inputs, acknowledge the DMA output and DMA 38 DACK 1 active low) input request, respectively. 39 35 INT/TYP —_| Interrupt The signal is pulled down, when the request (output, PBC is requesting an interrupt. In that active low) case, the uP should enter an interrupt routine for reading status register 1.

40 RESET Reset (input, A high on this input forces the PBC

active high) into reset state. The minimum reset pulse is 16 complete clock cycles. 41 | 137 sIPO These interface ports are used for bi- .! : . directional, bit-serial transfer of speech, . : . data and control words to and from the . . . signal processing codec filter (SICOFI) . . . or standard codec. Corresponding with : : . the direction signal, the PBC PEB 2050 . . . is transmitting during the high level of 33 40 SIP3 DIR within the first half of a 125 ps frame. Siemens Components, inc. 140

SIP +> _ ! Subscriber CSN KO PCM — PCM ' Interface Unit _ aha _ Interface Unit <= Highways Pp * — sIP7 iq ] oR = = i SIGs yy SCLK Timing | Bus Interface SYP Controt Unit | Controt Unit CLK — - RESET Special Purpose L —— TSA Module Registers oo + 7 L PBC Bus = GND Saar 4 SEE GE yO — ba TxSD Bus Interface HOLC Xx FIFO 8! FIFO Registers Controller RxD TSC Z ran A NZ £PU Bus Sa yo —Y uP Registers CPU Interface ttt he Uy | CS ALE RD WR INT 00-07 DMIR MOR DACKO.DACKT Siemens Components, Inc. 141

Description of the Functional Blocks The PBC has been designed especially for use in peripheral subscriber boards, but its functional flexibility also permits its application in various parts of a digital exchange tele- communications system. Used in peripheral subscriber boards it performs two essential functions: 1) Exchange of control data between a central processing unit, an on-board processing unit and individual subscriber connections. The PBC supports the ISO/CCITT’s HDLC communication-line protocol. An application-specific, PBC-internal controller controls the distribution of data on the board. 2) The time-slot controlled transfer of PCM data (64 Kbaud channels) between the PCM highways and the subscriber connections. Data transfer between both parts, such as signaling through PCM highways (common channel) or the access of the on-board yP to 64 Kbaud channels, are considerably simplified by the IC. The two central functional blocks are reflected in the circuit structure: The PCM synchro- nous portion constitutes the interfaces to the subscribers and the PCM highways. It com- prises the following functional blocks: @ SIU (Serial Interface Unit) with last look logic @ PIU (PCM Interface Unit) @ CAM (Contents-Addressable Memory) @ TCU (Timing Control Unit) @ MODE register @ PBC bus The asynchronous portion constitutes the interface to the local microprocessor (8-bit Parallel). and to the central control (serial HDLC interface) and comprises the following functional blocks: @ HDLC controller @ Pinterface | @ \\1P control and status register @ ULCU (User Level Control Unit) The two portions are interconnected by the following functional blocks: @ X FIFO (Transmit FIFO) ® Bidirectional FIFO @ BICU (Bus Interface Control Unit) @ BIR (Bus Interface Register) Siemens Components, Inc. 143

a Maximum Ratings Parameter emer [awe Po Range of Operation Total power consumption ee cs DC Characteristics Ty =0 to 70°C; Veg = 5 V £0.25 V; GND=0V Parameter eee L-output voltage Vou v To. =+1.6 mA H-output voltage Vou v Ton = —400 pA Input leakage current Ty BA Vin= Voc to 0 V Output leakage current To. -10 HA Vout = Voc to. 0 V Voc supply current Toc 70 mA Voc =5V Siemens Components, Inc. 144

Ty = 25°C; Voc = GND =0V [Limit Values Parra Pe eee Input capacitance Cw pF Input/output capacitance [co =| Sits tS i Output capacitance Cour 15 pF unmeasured pins AC Characteristics T,= 0 to 70°C; Vg = 5 V40.25 V; GND=0V Microprocessor Interface Read Cycle — amt an — Address hold after ALE lt —[20-tsti‘d?:Ci‘é‘CC#Cins RD control interval case 1") lt _-[2xcp | sds RD control interval case 22) lt [10 | [ns Write Cycle WA control interval case 1") [tw _-|2xcp | sd ns WR control interval case 22) [m [5 | |ns 4) Case 1: read, write of Bl FIFO and X FIFO 2) Case 2: all other registers Siemens Components, Inc. 145

faa, ALE / \\ / \\ ten my ty ———4 ae {| ?7—s or tal ta Tro, |toe, oe Xe a Write Cycle Petey i -—— _ Tow fun oe TTX Fee XT ep tom) + nor } \\ ton | altel (BACK i te tan 4 tee TS. tor tap +} Fe DMA Write tow — Omir } \\ ORK \\ / toe ay lal DO tw ye Baik { f poet, 8 Fe Siemens Components, Inc. 147

tose | Z r “ys RxHWO DIR XTX XZ. ocR=1 four #— | 7; Rx HWD Li OCR=0 fosna foun *) Common channel mode togaa 75 NS Siemens Components, Inc. 150

PCM Interface (cont'd) Parameter Lamon fae Toon _| Test Condon Transmit Timing Data ole tine OOK= 0 [town [45 | 160 | ne | 6, = 200 Data float on TS EXIT [tx [35 [80 [ns | C= 1600F Time slot x to enable DOX = 1 [tsone | 40 | 100 =| ns | = 180 pF Transmit Timing i | CLK } TeHWO if OCx=0 —* fox — Fouxr bo Pex

1 TxHWO

| OCX=1 oy an ins ! \\ Dcx=0 ; | TE DCK=1 —> tone Siemens Components, Inc. 151

AC Testing Input, Output Waveform AC Testing Load Circuit 2.0, 20 Device Test Points“ Under 08 ‘oa Test Cuong = 50 pF aus , zt T Load AC testing: inputs are driven at 2.4 V for a logic “1” and at 0.45 V for a logic “0”. Timing measurements are made at 2.0 V for a logic “1" and at 0.8 V for a logic “0”. Siemens Components, Inc. 153

Product Information

PEB2050-N specifications and overview.

Summary

Peripheral Board Controller(PBC)

Description

Peripheral Board Controller(PBC)

Source title PEB2050-N Datasheet(PDF) - Siemens Semiconductor Group

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