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Features
Up to 2A continuous Output voltage range from 1.0V to 3.6V by external select resistors Input voltage range 4.6V – 6.0V Current mode control, pulse-by-pulse current limit, current sharing enabled and (N+K) redundancy compatible shutdown mode SYNC function, 100 kHz – 5 MHz lock range with selectable 500 kHz /1 MHz free running frequency Shutdown pin, Power Good output pin for supply sequencing Better than 1% typical initial accuracy (25°C) Control inputs compatible with TTL, LVTTL, LVCMOS (2.5V and 3.3V) and 5V CMOS Available in ceramic hermetic packaging and in bare die form 32-lead ceramic package Figure 2. Package Type Figure 1. Typical Application Diagram Table 1. Radiation Performance
Table 2. Electrical Specifications
Table 2. Electrical Specifications (Continued)
Table 3. Pin Descriptions Figure 3. Pin Layout (Top View) Table 4. Operating Ranges Table 5. Absolute Maximum Ratings ranges for extended periods may reduce reliability.
1 AGND Analog ground
2 VREF
3 EAINP Error Amplifier (+) input, loop to VREF
4 EAINM Error Amplifier (-) input, load feedback
5 EAOUT Error Amplifier output/loop to ISET
6 ISET Current Setpoint input/loop to EAOUT
7 ICOMP Variable current compensation/
8 RSET Resistor to set reference current
9 SYNCOb Loopthrough complement output
10 PGOOD Power Good flag output
11 RSEL Reference resistor selection
23 OUT Switch power output
30 SDb Shutdown (L)/enable input
32 SScap Soft Start timing cap input
Table 6. Electrostatic Discharge (ESD) Ratings devices are immune to latch-up. minority carrier elements are not used.
Figure 6. Thermal Derating Curve
5 A / cm2) by
achieving a current density of <1.5 x 105 A / cm2. Figure 4. Efficiency Curves Over Output Figure 5. Efficiency Curves Over Typical
Figure 7. Block Diagram
The PE99151 is a radiation-hardened point-of-load buck regulator. This highly integrated switching regulator contains two synchronous power switches capable of delivering up to 2A of continuous current. The PE99151 is designed to operate from a wide 5V bus and provide 1.0V to 3.6V supply rails for analog, digital and RF payloads. The internal oscillator can operate at 500 kHz or 1 MHz. Optionally, the switching frequency can be synchronized to an external reference from 100 kHz to 5 MHz. Current limiting is adjustable with an external resistor and is achieved through peak current mode control. An external resistor also provides adjustable slope compensation to optimize stability and closed loop bandwidth across output voltage and switching frequency range. Loop compensation is externally adjustable to meet application transient response while still maintaining stability requirements. The output is tri-stated when the SDb pin is low to enable hot-spare capability. Peak Current Mode Control Loop The PE99151 uses a peak current mode control architecture. At the falling edge of either the internal oscillator or, if present, the external reference, the high side switch turns on. The input voltage is then connected to the load voltage through the high side switch and the inductor for a time greater than the minimum-on-time. Current in the inductor begins to ramp approximately as IN – VOUT )/L. Energy is stored in the inductor during this period. As the inductor current rises, current through the high side switch is sensed and compared to a current threshold. The inductor current continues to ramp until the current threshold is reached. At this point the high side switch turns off and the low side switch turns on for at least the minimum-off-time. Energy stored in the inductor during the previous phase is discharged into the load supply rail through the low side switch and the inductor. Inductor current decreases at a rate of approximately V OUT/L. The low side switch stays on until the next falling edge of the reference clock. In order to prevent unintended harmonics or spurs, the part does not exit continuous conduction mode. Whether the current threshold was met in the previous clock cycle or not, a minimum-off-time, followed by a minimum-on-time immediately follows the falling edge of the reference clock. While providing improved bandwidth and inherent current limiting, all current mode control switching regulators require slope compensation to ensure stability across all application conditions. The PE99151 provides adjustable slope compensation to allow the designer to optimize transient response and stability requirements. The compensation ramp is provided through the ICOMP pin. Inboard of the ICOMP pin is the CICOMP capacitor which can be used to generate an RC compensation ramp by tying the ICOMP pin to either V OUT or VIN through an external resistor to produce the desired ramp. See the design guide for selection of the appropriate resistor value. The RC ramp is reset anytime the low side switch is on by a FET switch. Current Threshold and Over Current Protection The current mode control threshold current is set by the ISET pin which is driven by the voltage control loop from the EAOUT pin. The PE99151 takes the voltage applied to the ISET pin, subtracts 0.7V (typ) and applies that voltage to the R SET resistor. An internal RSET resistor will be used if the RSEL pin is grounded or an external RSET resistor connected to the RSET pin is used if the RSEL pin is tied high. The current flowing through the R SET resistor is then used as a scaled current reference for the inductor current threshold comparison. The scaling ratio is defined as GIREF in Table 2. Over current protection is achieved by limiting the maximum voltage applied to the internal or external RSET resistor to the VMAXRSET value listed in Table 2. Thus, the current limit can be adjusted by selection of the external R SET resistor. This flexibility allows characterization and testing to a high current in the lab while still limiting the current to lower level in the application. Voltage Control Loop The output voltage is achieved by controlling the ISET pin. The PE99151 contains an amplifier with both of the positive and negative input terminals, EAINP and EAINM respectively, and the output terminal EAOUT all pinned out to package pins. This allows for flexible configurations of the voltage reference, error amplifier, feedback networks and the current mode control loop. In normal configuration the error amp senses the output voltage, V OUT, through a resistor divider that produces a 1.000V division at the target VOUT. It compares that feedback voltage to the 1.000V reference and increases the voltage applied to the ISET pin when the output voltage is low and decreases the voltage applied to the ISET pin when the output voltage is high. Loop compensation is required to attenuate the frequency content at and above the switching frequency and to achieve the desired phase margin in the voltage control loop. See the Design Guide for instructions on designing the compensation network.
©2010-2013 Peregrine Semiconductor Corp. All rights reserved. Document No. DOC-29314-2 │ UltraCMOS® Power Management Solutions Accurate Voltage Reference The PE99151 contains an accurate 1.000V reference which is used to drive an accurate output voltage. The 1.000V reference is trimmed at the factory to within ±1% of 1.000V at 25°C. Soft start The soft start circuit uses the voltage on the SSCAP pin to limit (pull down) the external VREF pin. This allows the designer to limit the output voltage ramp rate. Voltage tracking is specified on the VREF pin for applications that require an external tracking capability. The SSCAP pin is internally connected to a 16 pF (typ) cap to ground and to a 3V internal rail through a 1.2 MΩ (typ) resistor. When the SDb pin is low, the SSCAP pin is pulled to ground by a 12 KΩ (typ) resistor. When the shutdown signal is released the pull down switch is released and the voltage on the SSCAP pin begins to ramp up toward 3V. The ramp rate can be increased by tying the SSCAP pin to the 5V input rail through an external resistor. The pin is 5V capable. The ramp rate can also be slowed by connecting the SSCAP pin to ground through a supplemental capacitor. Under Voltage Lockout An internal under voltage lockout feature prevents the PE99151 from powering up before input voltage rises above the UVLO threshold of 4.2V (typ). 400 mV (typ) of hysteresis is built-in to prevent false-triggering of the UVLO circuit. The under voltage lockout must be cleared and the SDb pin must be released before the part will be enabled. Power Good Flag The PGOOD pin is an open drain output that can be used to sense when the output voltage of the converter has converged to within 10% (typ) of it’s final value. This pin can also be used to provide limited power sequencing when cascaded with the SDb pin of another PE99151 part. Internal circuitry senses when the voltage at the EAINM pin has reached to within 10% (typ) of an internal 1.000V reference voltage. When this happens, an internal counter begins counting reference clock cycles and continues counting as long as this condition remains true. When the counter has reached 64, the circuit will assert PGOOD. When EAINM exits the PGOOD window, there is a 30 mV (typ) hysteresis to prevent chatter when entering or exiting the window. If during the count, the EAINM pin exits the PGOOD threshold, the counter is reset, PGOOD is not asserted and the count will begin again when EAINM re-enters the PGOOD window. When exiting the PGOOD state, once EAINM is outside of the PGOOD threshold window, an internal counter begins counting and will de-assert PGOOD when it counts 64 reference clock cycles. If during the count, the EAINM pin re-enters the PGOOD threshold, the counter is reset, PGOOD is not de-asserted and the count will begin again when EAINM exits the PGOOD window. Synchronous (External Reference) or Asynchronous (Internal Reference) Switching Frequency The PE99151 contains an internal oscillator capable of operating at 1 MHz when the SYNC pin is tied to VIN or left open or at 500 kHz when the SYNC pin is tied to ground. This reference clock is used in the current mode control loop to time the rising edge of the OUT pin and as a global internal clock reference. When the SYNC pin is actively clocked at a rate of 100 kHz to 5 MHz, the internal oscillator uses the clocked sync pulse train as the global internal clock reference. Whether operating synchronously or asynchronously, the open drain SYNCOb pin contains the inverted internal clock reference. This inverted clock signal can be used to aid in the design of polyphase (n=2) power supplies.
current to send to the load. when VOUT has reached the target output voltage. Figure 8. Output Voltage Selection Rfb2 not installed. This is equivalent to directly connecting VOUT to EAINM. selections place restrictions on the Inductor selection. needs to be made early in the design process. requirements are introduced. mode compensation dynamic range. stability, reduce output ripple and improve efficiency.
discussed in the efficiency section of the Design Guide. along with their size and cost. Figure 9. Output Capacitor Selection drop is increased but the VOUT recovery time is shorter. the ripple, droop, and stability requirements over frequency. selecting the input capacitors. attenuate the high frequency conducted EMI. the X7R capacitors have very low DC voltage de-rating.
and losses associated with external passive components. inductor, the output capacitor and the input capacitor. under a variety of conditions. capacitors absorbing the ripple current. dissipated in the LSS when it is on. performance under a variety of conditions. resistor connecting the RSET pin to ground. Figure 10. PE99151 Current Limits
optimize transient response and stability requirements. L is the inductance of the output inductor. dividing by the GICOMP parameter in Table 2. Figure 11. PE99151 Slope Compensation a voltage mode control loop as shown in Figure 12. be replaced with a voltage controlled current source. network contains one pole in the voltage control loop.
to set a dominant pole in the loop to ensure stability. and for the required phase margin and loop bandwidth. to cancel the load pole at minimum load. system and the dominant pole location reduce together. impedance variation over process and temperature. available in the PE9915x Design Tool. Figure 12. PE99151 Control Loops
Figure 13. Package Drawing
Table 7. Ordering Information Figure 14. Marking Specifications specifications for product development. Specifications and features may change in any manner without notice. of this information. Use shall be entirely at the user’s own risk. No patent rights or licenses to any circuits described in this datasheet are implied or granted to any third party. are trademarks of Peregrine Semiconductor Corp. For sales and contact information please visit www.psemi.com.