DATASHEET SEARCH SITE | WWW.ALLDATASHEET.COM
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 16
Technical content
Features
3.5 GHz operation ÷10/11 dual modulus prescaler Phase detector output Serial or direct mode access Frequency selectivity: comparison frequency / 218 Low power: –35 mA @ 3.3V Radiation tolerant Ultra-low phase noise Pin compatible with the PE9763 (reference application note AN24 at www.psemi.com)
66 GND
51 N/C
Figure 2. Pin Configurations (Top View) Table 1. Pin Descriptions 1 R0 Direct Input R counter bit0 (LSB). 2 R1 Direct Input R counter bit1. 3 R2 Direct Input R counter bit2. 4 R3 Direct Input R counter bit3. 5 R4 Direct Input R counter bit4. 6 R5 Direct Input R counter bit5 (MSB). 7 K0 Direct Input K counter bit0 (LSB). 8 K1 Direct Input K counter bit1. 13 K2 Direct Input K counter bit2. 14 K3 Direct Input K counter bit3. 15 K4 Direct Input K counter bit4. 11 VDD Note 1 Digital core VDD. 12 VDD Note 1 Digital core VDD. 16 K5 Direct Input K counter bit5. 17 K6 Direct Input K counter bit6.
18 K7 Direct Input K counter bit7. 19 K8 Direct Input K counter bit8. 20 K9 Direct Input K counter bit9. 21 K10 Direct Input K counter bit10. 22 K11 Direct Input K counter bit11. 23 K12 Direct Input K counter bit12. 24 K13 Direct Input K counter bit13. 25 K14 Direct Input K counter bit14. 26 K15 Direct Input K counter bit15. 27 K16 Direct Input K counter bit16. 28 K17 Direct Input K counter bit17 (MSB). 29 VDD Note 1 Digital core VDD. 30 VDD Note 1 Digital core VDD. 33 M0 Direct Input M counter bit0 (LSB). 34 M1 Direct Input M counter bit1.
35 M2 Direct Input M counter bit2
36 M3 Direct Input M counter bit3. M4 Direct Input M counter bit4. data are transferred to the secondary register on S_WR rising edge. M5 Direct Input M counter bit5. SDATA Serial Input Binary serial data input. Input data entered MSB first. M6 Direct Input M counter bit6. the 8-bit enhancement register (E_WR “high”) on the rising edge of SCLK. 40 M7 Direct Input M counter bit7. 41 M8 Direct Input M counter bit8 (MSB). 42 A0 Direct Input A counter bit0 (LSB). A1 Direct Input A counter bit1. the enhancement register on the rising edge of SCLK. 44 A2 Direct Input A counter bit2. 45 A3 Direct Input A counter bit3 (MSB). 46 DIRECT Both Input Direct mode select. “High” enables direct mode. “Low” enables serial mode. 47 Pre_en Direct Input Prescaler enable, active “low”. When “high”, FIN bypasses the prescaler. 48 VDD Note 1 Digital core VDD. Table 1. Pad Descriptions (Cont.)
Notes: 1. All V DD pads are connected by diodes and must be supplied with the same positive voltage level.
- All digital input pads have 70 k Ω pull-down resistors to ground.
52 VDD Note 1 Prescaler VDD. 53 FIN Both Input Prescaler input from the VCO. 3.5 GHz max frequency.
54 FIN Both Input
this pin and be connected in series with a 50Ω resistor directly to the ground plane.
58 CEXT Both Output
pedance, otherwise LD is a logic low (“0”). 60 DOUT Both Output Data out function, enabled in enhancement mode. 61 VDD Note 1 Output driver/VDD. 63 PD_D Both Output PD_D pulses down when fp leads fc. 65 PD_U Both Output PD_U pulses down when fc leads fp. 67 VDD Note 1 Output driver/VDD. 69 VDD Note 1 Phase detector VDD. 73 fr Both Input Reference frequency input. 74 VDD Note 1 Reference VDD. 75 V DD Note 1 Digital core VDD. 77 ENH Both Input Enhancement mode. When asserted low (“0”), enhancement register bits are functional. 79 MS2_SEL Both Input MASH 1-1 select. “High” selects MASH 1-1 mode. “Low” selects the MASH 1-1-1 mode.
80 RND_SEL Both Input
the phase detector comparison frequency / 219.
Table 2. Absolute Maximum Ratings Electrostatic Discharge (ESD) Precautions exceeding the rating specified in Table 4. Table 4. ESD Ratings
- Pin 60 is a test pin only. It is not used in normal operation.
hanced low-dose-rate sensitivity.
Table 5. DC Characteristics @ VDD = 3.30V, –40 °C < TA < +85 °C, unless otherwise specified
Table 6. AC Characteristics @ VDD = 3.30V, –40 °C < TA < +85 °C, unless otherwise specified5 Notes: 1. f Clk is verified during the functional pattern test. Serial programming sections of the functional pattern are clocked at 10 MHz to verify fClk specification.
- CMOS logic levels can be used to drive reference input if DC coupled. Voltage input needs to be a minimum of 0.5 V PP. For optimum phase noise performance,
the reference input falling edge rate should be faster than 80 mV/ns.
- Parameter is guaranteed through characterization only and is not tested.
- Parameter is verified during the element evaluation and are not tested for die sales.
- All information in Table 6 is not tested at wafer sort.
275 MHz ≤ Freq ≤ 3200 MHz –5 5 dBm
depending on the value of the modulus select. achieve the desired fractional step. modes and a lock detect output. Figure 3. Functional Block Diagram
Setting the Pre_en control bit “low” enables the ÷10/11 prescaler. The main counter chain then divides the RF input frequency (FIN) by an integer or fractional number derived from the values in the “M” and “A” counters and the DSM input word K. The accumulator size is 18 bit, so the fractional value is fixed from the ratio K/2 18. There is an additional bit in the DSM that acts like an extra bit (19 th bit). This bit is enabled by asserting the pin RAND_SEL to “high”. Enabling this bit has the benefit of reducing the spurious levels. However, a small frequency offset will occur. This positive frequency offset is calculated with the following equation. foffset = [FR / (R+1)] / 219 (1) All of the following equations do not take into account this frequency offset. If this offset is important to a specific frequency plan, appropriate account needs to be taken. In the normal mode, the output from the main counter chain (f p) is related to the VCO frequency (FIN) by the following equation: where A ≤ M + 1, 1 ≤ M ≤ 511 When the loop is locked, FIN is related to the reference frequency (FR) by the following equation: where A ≤ M + 1, 1 ≤ M ≤ 511 A consequence of the upper limit on A is that F IN must be greater than or equal to 90 × [FR / (R+1)] to obtain contiguous channels. The A counter can accept values as high as 15, but in typical operation it will cycle from 0 to 9 between increments in M. Programming the M counter with the minimum allowed value of “1” will result in a minimum M counter divide ratio of “2”. Prescaler Bypass Mode (*) Setting the frequency control register bit Pre_en “high” allows F IN to bypass the ÷10/11 prescaler. In this mode, the prescaler and A counter are powered down, and the input VCO frequency is divided by the M counter directly. The following equation relates F IN to the reference frequency FR: where 1 ≤ M ≤ 511 (*) Only integer mode In frequency bypass mode, neither A counter or K counter is used. Therefore, only integer-N operation is possible. Reference Counter The reference counter chain divides the reference frequency, F R, down to the phase detector comparison frequency, fc. The output frequency of the 6-bit R counter is related to the reference frequency by the following equation: fc = FR / (R+1) (5) where 0 ≤ R ≤ 63 Note that programming R with “0” will pass the reference frequency, F R, directly to the phase detector. Register Programming Serial Interface Mode While the E_WR input is “low” and the S_WR input is “low”, serial input data (SDATA input), B to B20, are clocked serially into the primary register on the rising edge of SCLK, MSB (B0) first. The LSB is used as address bit. When “0”, the contents from the primary register are transferred into the secondary register on the rising edge of either S_WR according to the timing diagrams shown in Figure 4. When “1”, data is transferred to the auxiliary register according to the same timing diagram. The secondary register is used to program the various counters, while the auxiliary register is used to program the DSM. Data are transferred to the counters as shown in Table 8.
ister on the rising edge of SCLK, MSB (B0) first. cording to the timing diagram shown in Figure 4. shown in Table 7 and Table 8. Table 7. Secondary Register Programming Table 8. Auxiliary Register Programming Table 9. Enhancement Register Programming Note: * Serial data clocked serially on SCLK rising edge while E_WR “low” and captured in secondary register on S_WR rising edge. Note: * Serial data clocked serially on SCLK rising edge while E_WR “low” and captured in secondary register on S_WR rising edge. Note: * Serial data clocked serially on SCLK rising edge while E_WR “high” and captured in the double buffer on E_WR falling edge.
Figure 4. Serial Interface Mode Timing Diagram The functions of the enhancement register bits are shown below with all bits active “high”. Table 10. Enhancement Register Bit Functionality Bit 2 fp output Drives the M counter output onto the D OUT output. Bit 3 Power down Power down of all functions except programming interface. Bit 4 Counter load Immediate and cont inuous load of counter programming. Bit 5 MSEL output Drives the internal dual modul us prescaler modulus select (MSEL) onto the DOUT output. Bit 6 fc output Drives the reference counter output onto the D OUT output. Bit 7 LD disable Disables the LD pin for quieter operation.
Figure 5. Typical Phase Noise quency, for a positive kV VCO. verting comparator with an open drain output. Thus LD is an “AND” function of PD_U and PD_D. A typical phase noise plot is shown below. “Trace 1” is the smoothed average and “Trace 2” is the raw data.
Figure 6. Typical Spurious Plot
Notes: 1. All pad locations originate from the die center and refer to the center of the pad.
- Minimum pad pitch is 150 µm. Pad openings are 90 µm.
Figure 7. Pad Numbering1,2 Table 11. Mechanical Specifications Note: * There are two different singulated die sizes per reticle.
Table 12. Pin Coordinates
specifications for product development. Specifications and features may change in any manner without notice. of this information. Use shall be entirely at the user’s own risk. No patent rights or licenses to any circuits described in this datasheet are implied or granted to any third party. For sales and contact information please visit www.psemi.com. Table 13. Ordering Information die are obtained from non-qualified wafers so are not suitable for qualification, production, radiation testing or flight use.