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Frequency range 5 GHz in 10/11 prescaler modulus 4 GHz in 5/6 prescaler modulus Phase noise floor figure of merit: –230 dBc/Hz Low power: 75 mA @ 2.7V Serial or direct mode access Packaged in a 44-lead CQFP 100 kRad(Si) total dose Figure 1. Functional Diagram
Table 1. Pin Descriptions Figure 3. Package Type Figure 2. Pin Configurations (Top View)
2 R4 Direct Input R counter bit4
3 R5 Direct Input R counter bit5
4 A3 Direct Input A counter bit3
5 GND Both Ground
6 M3 Direct Input M counter bit3
7 M2 Direct Input M counter bit2
8 M1 Direct Input M counter bit1
9 M0 Direct Input M counter bit0
11 GND Both Ground
12 M8 Direct Input M counter bit8
13 M7 Direct Input M counter bit7
or the 8-bit enhancement register (E_WR “high”) on the rising edge of SCLK. SDATA Serial Input Binary serial data input. Input data entered MSB first. register data is transferred to the secondary register on S_WR or Hop_WR rising edge.
Table 1. Pin Descriptions (continued) 17 Direct Direct Input Select “High” enables Di rect Mode. Select “Low” enables Serial Mode.
18 A0 Direct Input A counter bit0
clocked into the enhancement register on the rising edge of SCLK.
20 A2 Direct Input A counter bit2
22 Pre_en Direct Input Prescaler enable, active “low”. When “high”, FIN bypasses the prescaler. 23 Pre_5/6_Sel Direct Input 5/6 modulus select, ac tive “High.” When “Low,” 10/11 modulus selected. as possible to this pin and be connected in series with a 50Ω resistor to ground.
26 F IN Both Input
27 GND Both Ground
through enhancement register programming.
29 CEXT Both Output
inverting amplifier used for driving LD. high impedance, otherwise LD is a logic low (“0”).
32 PD_ D Both Output PD_ D is pulse down when fp leads fc
33 PD_ U Both Output PD_ U is pulse down when fc leads fp
36 GND Both Ground
40 R0 Direct Input R counter bit0
41 R1 Direct Input R counter bit1
42 R2 Direct Input R counter bit2
43 R3 Direct Input R counter bit3
44 GND Both Ground
Notes: 1. V DD pins 1, 10, 21, 24, 31, 34, 35 and 38 are connected by diodes and must be supplied with the same positive voltage level.
- All digital input pins have 70 k Ω pull-down resistors to ground.
Table 3. Absolute Maximum Ratings Notes: 1. Human Body Model (MIL-STD-883 Method 3015).
- Pin 28 is not used in normal operation.
exceeding the rating specified. devices are immune to latch-up. Table 2. Operating Ratings
50 MHz–5 GHz PMAX_CW 10 dBm
periods may reduce reliability. enhanced low dose rate sensitivity. Table 4. Single Event Effects Notes: 1. Testing performed using serial programming mode.
- SEE testing was conducted with Au, Ho, Xe, Kr, Cu ion species at 0°
- Minor transients (phase errors) observed resulting in self-recovering
operation without intervention.
Table 5. DC Characteristics @ VDD = 2.7V, –40 °C < TA < +85 °C, unless otherwise specified
Table 6. AC Characteristics @ VDD = 2.7V, –40 °C < TA < +85 °C, unless otherwise specified
800 MHz–4 GHz
800 MHz–<4 GHz
Table 6. AC Characteristics @ VDD = 2.7V, –40 °C < TA < +85 °C, unless otherwise specified (continued) Notes: 1. Timing parameters are guaranteed through desi gn characterization and not tested in production.
- f clk is verified during the functional pattern test. Serial programming sections of the functional pattern are clocked at 10 MHz to verify fclk specification.
- 0 dBm minimum is recommended for improved pha se noise performance when sine-wave is applied.
- CMOS logic levels can be used to drive the reference input. If the V DD of the CMOS driver matches the VDD of the PLL IC, then the reference input can be DC
- +2 dBm or higher is recommended for improved phase noise performance.
- The phase noise can be separated into two normalized specif ications: a floor figure of merit and a flicker figure of merit. To accurately measure the phase noise
flicker noise is measured at a frequency offset ≤ 1000 Hz. The formula assumes a –10 dB/decade slope versus frequency offset.
Figure 7. Equivalent Output Diagram
generates up and down frequency control signals. Figure 16. Functional Block Diagram
The main counter chain divides the RF input frequency, FIN, by an integer derived from the user- defined values in the “M” and “A” counters. It is composed of the 5/6 or 10/11 selectable modulus prescaler, modulus select logic, and 9-bit M counter. The prescaler can be set to either 5/6 or 10/11 based on the Pre_5/6_SEL pin. Setting Pre_en “low” enables the 5/6 or 10/11 prescaler. Setting Pre_en “high” allows F IN to bypass the prescaler and powers down the prescaler. The output from the main counter chain, fp, is related to the VCO frequency, Fin, by the following equation: where A M + 1, 1 ≤ M ≤ 511 Or fp = FIN / [5 x (M + 1) + A] where A M + 1, 1 ≤ M ≤ 511 When the loop is locked, FIN is related to the reference frequency, FR, by the following equation: where A M + 1, 1 ≤ M ≤ 511 Or FIN = [5 x (M + 1) + A] x [FR / (R + 1)] where A M + 1, 1 ≤ M ≤ 511 A consequence of the upper limit on A is that in Integer-N mode, to obtain contiguous channels, FIN must be = 90 x [FR / (R + 1)] with 10/11 modulus FIN must be = 20 x [FR / (R + 1)] with 5/6 modulus The A counter can accept values as high as 15, but in typical operation it will cycle from 0 to 9 between increments in M. Programming the M counter with the minimum allowed value of “1” will result in a minimum M counter divide ratio of “2”. Prescaler Bypass Mode Setting Pre_en “high” allows F IN to bypass and power down the prescaler. In this mode, the 5/6 or 10/11 prescaler and A register are not active, and the input VCO frequency is divided by the M counter directly. The following equation relates F in to the reference frequency, FR: where 1 ≤ M ≤ 511 Reference Counter The reference counter chain divides the reference frequency, FR, down to the phase detector comparison frequency, fc. The output frequency of the 6-bit R counter is related to the reference frequency by the following equation: where 0 ≤ R ≤ 63 Note that programming R with “0” will pass the reference frequency, FR, directly to the phase detector.
Figure 17. Data is transferred to the counters as according to the timing diagram shown in Figure 17. Table 7. Primary Register Programming Table 8. Enhancement Register Programming Note: * Serial data clocked serially on SCLK rising edge while E_WR “low” and captured in secondary register on S_WR rising edge. Note: * Serial data clocked serially on SCLK rising edge while E_WR “high” and captured in the double buffer on E_WR falling edge.
Figure 17. Serial Interface Mode Timing Diagram The functions of the enhancement register bits are shown below with all bits active “high”. Table 9. Enhancement Register Bit Functionality p output Drives the M counter output onto the D OUT output. Bit 3 Power down Power down of all functions except programming interface. Bit 4 Counter load Immediate and cont inuous load of counter programming. Bit 5 MSEL output Drives the internal dual modul us prescaler modulus select (MSEL) onto the DOUT output. Bit 6 f c output Drives the reference counter output onto the D OUT output. Bit 7 LD Disable Disables the LD pin for quieter operation.
©2010-2015 Peregrine Semiconductor Corp. All rights reserved. Document No. DOC-15214-7 │ UltraCMOS® RFIC Solutions Product Specification PE97240 Phase Detector The phase detector is triggered by rising edges from the main Counter (fp) and the reference counter (fc). It has two outputs, namely PD_U, and PD_D . If the divided VCO leads the divided reference in phase or frequency (fp leads fc), PD_D pulses “low”. If the divided reference leads the divided VCO in phase or frequency (fr leads fp), PD_U pulses “low”. The width of either pulse is directly proportional to phase offset between the two input signals, fp and fc. The phase detector gain is 400 mV/radian. PD_U and PD_D are designed to drive an active loop filter which controls the VCO tune voltage. PD_U pulses result in an increase in VCO frequency and PD_D results in a decrease in VCO frequency. A lock detect output, LD is also provided, via the pin C EXT. CEXT is the logical “NAND” of PD_U and PD_D waveforms, which is driven through a series 2 kΩ resistor. Connecting CEXT to an external shunt capacitor provides integration. CEXT also drives the input of an internal inverting comparator with an open drain output. Thus LD is an “AND” function of PD_U and PD_D. See Figure 16 for a functional block diagram of this circuit.
Figure 20. Evaluation Board Schematic
Figure 20. Evaluation Board Schematic (continued)
Figure 21. Package Drawing
Table 10. Ordering Information radiation testing or flight use. Figure 22. Top Marking Specifications specif ica t ions for produ ct de ve lopment. Spe cif icat ion s and fea tures may change in any manner without no t ice . o f th is informat ion . Use sha ll be en t ire ly at the user ’s own r isk. No pa tent r ight s or licen ses to any cir cu it s de scr ibed in th is data sheet are imp lied or granted to any th ird part y.