PE9704 PSEMI | Alldatasheet
Document overview
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Technical content
Features
- 3000 MHz operation
- ÷10/11 dual modulus prescaler
- Phase detector output
- Serial interface or hardwired programmable
- Ultra-low phase noise
- SEU < 10-9 errors / bit-day
- 100 Krad (Si) total dose
- 44-lead CQFJ
Figure 1. Block Diagram
Table 1. Pin Descriptions Figure 2. Pin Configurations (Top View) Figure 3. Package Type
2 R 0 Direct Input R Counter bit0
3 R 1 Direct Input R Counter bit1
4 R 2 Direct Input R Counter bit2
5 R 3 Direct Input R Counter bit3
6 GND Both (Note 1) Ground
7 R 4 Direct Input R Counter bit4
8 R 5 Direct Input R Counter bit5 (MSB)
9 M 0 Direct Input M Counter bit0
10 M 1 Direct Input M Counter bit1
11 VDD Both (Note 1) Same as pin 1
12 VDD Both (Note 1) Same as pin 1
13 M 2 Direct Input M Counter bit2
14 M 3 Direct Input M Counter bit3
register on S_WR rising edge. (E_WR “high”) on the rising edge of CLOCK.
Table 1. Pin Descriptions (continued)
17 GND Both Ground
19 M 7 Direct Input M Counter bit7
20 M 8 Direct Input M Counter bit8 (MSB)
21 A0 Direct Input A Counter bit0
22 D MODE Both Input Selects direct interface mode (DMODE =1) or serial interface mode (DMODE =0)
23 VDD Both (Note 1) Same as pin 1
clocked into the enhancement register on the rising edge of CLOCK. A1 Direct Input A Counter bit1.
25 A2 Direct Input A Counter bit2
26 A3 Direct Input A Counter bit3 (MSB)
27 FIN Both Input RF prescaler input from the VCO. 3.0 GHz maximum frequency.
31 VDD Both (Note 1) Same as pin 1
select (MSEL) can be routed to DOUT through enhancement register programming.
33 VDD Both (Note 1) Same as pin 1
36 PD_ D Both Output PD_ D pulses down when fp leads fc. 37 PD_ U Both PD_ U pulses down when fc leads fp.
38 VDD Both (Note 1) Same as pin 1
39 C EXT Both Output
inverting amplifier used for driving LD.
40 GND Both Ground
41 GND Both Ground
42 FR Both Input Reference frequency input
locked, LD is high impedance; otherwise LD is a logic low (“0”). Note 1: VDD pins 1, 11, 12, 23, 31, 33, 35, and 38 are connected by diodes and must be supplied with the same positive voltage level. Note 2: All digital input pins have 70 kΩ pull-down resistors to ground.
Table 2. Absolute Maximum Ratings Table 4. ESD Ratings exceeding the specified rating in Table 4. devices are immune to latch-up. Table 3. Operating Ratings Table 5. DC Characteristics: Counter and phase detector outputs: fc, fp.
Table 6. AC Characteristics: VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified Note 2: CMOS logic levels can be used to drive reference input if DC coupled. Voltage input needs to be a minimum of 0.5Vp-p. Note 3: Parameter is guaranteed through characterization only and is not tested.
©2003-2006 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0083-03 │ UltraCMOS™ RFIC Solutions Functional Description The PE9704 consists of a prescaler, counters, a phase detector, and control logic. The dual modulus prescaler divides the VCO frequency by either 10 or 11, depending on the value of the modulus select. Counters “R” and “M” divide the reference and prescaler output, respectively, by integer values stored in a 20-bit register. An additional counter (“A”) is used in the modulus select logic. The phase-frequency detector generates up and down frequency control signals. The control logic includes a selectable chip interface. Data can be written via a serial bus or hardwired directly to the pins. There are also various operational and test modes and a lock detect output. Main Counter Chain Normal Operating Mode Setting the PB control bit “low” enables the ÷10/11 prescaler. The main counter chain then divides the RF input frequency (F IN) by an integer derived from the values in the “M” and “A” counters. In this mode, the output from the main counter chain (fp) is related to the VCO frequency (FIN) by the following equation: where A ≤ M + 1, 1 ≤ M ≤ 511 When the loop is locked, FIN is related to the reference frequency (FR ) by the following equation: where A ≤ M + 1, 1 ≤ M ≤ 511 A consequence of the upper limit on A is that FIN must be greater than or equal to 90 x (FR / (R+1)) to obtain contiguous channels. The A counter can accept values as high as 15, but in typical operation it will cycle from 0 to 9 between increments in M. Programming the M counter with the minimum allowed value of “1” will result in a minimum M counter divide ratio of “2”. Prescaler Bypass Mode Setting the enhancement register bit PB “high” allows FIN to bypass the ÷10/11 prescaler. In this mode, the prescaler and A counter are powered down, and the input VCO frequency is divided by the M counter directly. This mode is only available when using the serial port to set the frequency control bits. The following equation relates F IN to the reference frequency FR : where 1 ≤ M ≤ 511 Reference Counter The reference counter chain divides the reference frequency FR down to the phase detector comparison frequency fc. The output frequency of the 6-bit R Counter is related to the reference frequency by the following equation: where 0 ≤ R ≤ 63 Note that programming R with “0” will pass the reference frequency (FR ) directly to the phase detector.
counters as shown in Table 7. data provides control bits as shown in Table 8. These bits are active when the Enh input is “low”. Table 7. Frequency Register Programming Table 8. Enhancement Register Programming
- Data is clocked serially on CLOCK rising edge while E_WR is “low” and transferred to frequency register on S_WR rising edge.
- Data is clocked serially on CLOCK rising edge while E_WR is “low” and transferred to frequency register on S_WR rising edge.
Figure 4. Serial Interface Mode Timing Diagram Table 9. Enhancement Register Bit Functionality counter (fc). It has two outputs, PD_U, and PD_D. loop filter which controls the VCO tune voltage. Bit 2 f p output Drives the M counter output onto the DOUT output. Bit 3 Power down Power down of all functions except programming interface. Bit 4 Counter load Immediate and continuous load of counter programming.
Figure 5. Package Drawing Table 10. Ordering Information
©2003-2006 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0083-03 │ UltraCMOS™ RFIC Solutions Sales Offices The Americas Peregrine Semiconductor Corporation
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