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Document overview
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Technical content
Features
- 2200 MHz operation
- 10/11 prescaler
- Internal phase detector with charge pump
- Serial, parallel or hardwired programmable
- Low power – 25 mA at 3 V
- Targeted at Q3236 PLL replacement
- 100 Krad total dose
- 44-lead CQFJ PE9601
Figure 2. Package Type
Table 1. Pin Descriptions Figure 3. Pin Configuration 2 R0 Direct Input R Counter bit0 (LSB). 3 R1 Direct Input R Counter bit1. 4 R2 Direct Input R Counter bit2. 5 R3 Direct Input R Counter bit3. D0 Parallel Input Parallel data bus bit0 (LSB). M0 Direct Input M Counter bit0 (LSB). 8 D1 Parallel Input Parallel data bus bit1. M1 Direct Input M Counter bit1. 9 D2 Parallel Input Parallel data bus bit2. M2 Direct Input M Counter bit2. 10 D3 Parallel Input Parallel data bus bit3. M3 Direct Input M Counter bit3. 11 VDD ALL (Note 1) Same as pin 1. 12 VDD ALL (Note 1) Same as pin 1.
Serial load enable input. While S_WR is “low”, Sdata can be serially clocked. Sdata Serial Input Binary serial data input. Input data entered MSB first. D5 Parallel Input Parallel data bus bit5. M5 Direct Input M Counter bit5. “low”) or the 8-bit enhancement register (E_WR “high”) on the rising edge of Sclk. D6 Parallel Input Parallel data bus bit6. M6 Direct Input M Counter bit6. for programming of internal counters while in Serial Interface Mode. D7 Parallel Input Parallel data bus bit7 (MSB). Pre_en Direct Input Prescaler enable, active “low”. When “high”, F in bypasses the prescaler. for programming of internal counters while in Parallel Interface Mode. A0 Direct Input A Counter bit0 (LSB). clocked into the enhancement register on the rising edge of Sclk. A1 Direct Input A Counter bit1. A2 Direct Input A Counter bit2. A3 Direct Input A Counter bit3 (MSB). 22 Bmode ALL Input Selects direct interface mode ( Bmode =1). 23 VDD ALL (Note 1) Same as pin 1. register on the rising edge of Hop_WR.
28 Fin ALL Input
Table 1. Pin Descriptions (continued)
enhancement register programming or by floating or grounding V DD pin 31. 31 VDD -fp ALL (Note 2) VDD for f p. through enhancement register programming. 33 VDD ALL (Note 1) Same as pin 1.
34 Cext ALL Output
inverting amplifier used for driving LD. 35 VDD ALL (Note 1) Same as pin 1.
36 CP ALL Output Charge pump current is sourced for “up” when f c leads f p and sinked for “down”
37 NC ALL (Note 4) No connection. 38 VDD -fc ALL (Note 2) VDD for f c. enhancement register programming or by floating or grounding V DD pin 38. 42 fr ALL Input Reference frequency input. See Figure 4.
43 LD ALL Output,
is high impedance, otherwise LD is a logic low (“0”). Note 1: V DD pins 1, 11, 12, 23, 33, and 35 are connected by diodes and must be supplied with the same positive voltage level. Note 2: V DD pins 31 and 38 are used to enable test modes and should be left floating. Note 3: All digital input pins have 70k Ω pull-down resistors to ground. Note 4: No connect pins can be left open or floating. Figure 4. Looking into the device PIN 42 - fr
Table 2. Absolute Maximum Ratings devices are immune to latch-up. exceeding the rating specified in Table 4. may cause permanent device damage. limits in the DC Electrical Specifications table. extended periods may affect device reliability. Table 3. Operating Ratings Table 4. ESD Ratings
Table 5. DC Characteristics Counter and phase detector outputs: f c, f p.
1.0 V T A = 25° C
Table 6. AC Characteristics with no maximum level specified. Note 3: Parameter is guaranteed through characterization o nly and is not tested.
phase detector, a charge pump and control logic. control logic includes a selectable chip interface. Figure 5. Functional Block Diagram
The main counter chain divides the RF input frequency, F in , by an integer derived from the user defined values in the “M” and “A” counters. It is composed of the 10/11 dual modulus prescaler, modulus select logic, and 9 bit M counter. Setting Pre_en “low” enables the 10/11 prescaler. Setting Pre_en “high” allows F in to bypass the prescaler and powers down the prescaler. The output from the main counter chain, f p, is related to the VCO frequency, F in , by the following equation: where A ≤≤ ≤≤ M + 1, M ¹ 0 When the loop is locked, F in is related to the reference frequency, f r, by the following equation: where A ≤≤ ≤≤ M + 1, M ¹ 0 A consequence of the upper limit on A is that F in must be greater than or equal to 90 x (f r / (R+1)) to obtain contiguous channels. Programming the M Counter with the minimum value of “1” will result in a minimum M Counter divide ratio of “2”. In Direct Interface Mode, main counter inputs M 7 and M8 are internally forced low. Reference Counter The reference counter chain divides the reference frequency, f r, down to the phase detector comparison frequency, f c. The output frequency of the 6 bit R Counter is related to the reference frequency by the following equation: f where R > 0 Note that programming R equal to “0” will pass the reference frequency, f r, directly to the phase detector. In Direct Interface Mode, R Counter inputs R 4 and R 5 are internally forced low (“0”). Register Programming Parallel Interface Mode Parallel Interface Mode is selected by setting the Bmode input “low” and the Smode input “low”. Parallel input data, D[7:0], are latched in a parallel fashion into one of three, 8-bit primary register sections on the rising edge of M1_WR, M2_WR, or A_WR per the mapping shown in Table 7 on page 10. The contents of the primary register are transferred into a secondary register on the rising edge of Hop_WR according to the timing diagram shown in Figure 6. Data are transferred to the counters as shown in Table 7 on page 10. The secondary register acts as a buffer to allow rapid changes to the VCO frequency. This double buffering for “ping-pong” counter control is programmed via the FSELP input. When FSELP is “high”, the primary register contents set the counter inputs. When FSELP is “low”, the secondary register contents are utilized. The FSELP input is synchronized with the loading of the counters in order to minimize glitches in the “ping-pong” case. Due to this attribute, applications using a single register should use the secondary register (i.e. tie FSELP “low”) to avoid problems with the prescaler powering up in the disabled state. Parallel input data, D[7:0], are latched into the enhancement register on the rising edge of E_WR according to the timing diagram shown in Figure 6. This data provides control bits as shown in Table 8 on page 10 with bit functionality enabled by asserting the Enh input “low”. Direct Interface Mode Direct Interface Mode is selected by setting the Bmode input “high”. Counter control bits are set directly at the pins as shown in Table 7. In Direct Interface Mode, main counter inputs M 7 and M 8, and R Counter inputs R 4 and R 5 are internally forced low (“0”) Serial Interface Mode Serial Interface Mode is selected by setting the Bmode input “low” and the Smode input “high”. While the E_WR input is “low” and the S_WR input is “low”, serial input data (Sdata input), B 0 to B 19 , are clocked serially into the primary register on the rising edge of Sclk, MSB (B 0) first. The contents from the primary register are transferred into the secondary register on the rising edge of either S_WR or Hop_WR according to the timing diagram shown in Figure 6 and Figure 7. Data are transferred to the counters as shown in Table 7 on page 10.
secondary register contents are utilized. register on the rising edge of Sclk, MSB (B 0) first.
- After the falling edge of E_WR, the data
Table 7. Primary Register Programming *Serial data clocked serially on Sclk rising edge while E_WR “low” and captured in secondary register on S_WR rising edge. Table 8. Enhancement Register Programming *Serial data clocked serially on Sclk rising edge while E_WR “high” and captured in the double buffer on E_WR falling edge.
The functions of the enhancement register bits are shown below with all bits active “high”. Table 9. Enhancement Register Bit Functionality Bit 3 Power down Power down of all functions except programming interface. Bit 5 MSEL output Drives the internal dual modulus prescaler modulus select (MSEL) onto the Dout output. Bit 6 Prescaler output Drives the raw internal pres caler output (fmain) onto the Dout output. Bit 7 fp, f c OE fp, f c outputs disabled. two input signals, f p and f c. pulse duration approximately the same as PD_U. PD_D similarly drives a current sink at pin CP.
Table 10. Ordering Information Figure 8. Package Drawing
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