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Technical content
Features
HaRP™ technology enhanced Eliminates gate and phase lag No insertion loss or phase drift High linearity: 60 dBm IIP3 Low insertion loss 0.77 dB @ 100 MHz 1.00 dB @ 3000 MHz 1.15 dB @ 6000 MHz 1.38 dB @ 8500 MHz High isolation (RF1-RF2) 86.5 dB @ 100 MHz 48.2 dB @ 3000 MHz 36.6 dB @ 6000 MHz 27.8 dB @ 8500 MHz Fast switching time 700 ns RF ON 300 ns RF OFF Low power consumption 3.3 µW @ 3.3V 1 dB compression point of +33 dBm Single-pin 3.3V CMOS logic control ESD tolerant to 1000V HBM Absorptive/non-reflective Offered in a 7-lead hermetic CFP surface-mount package and in DIE form Figure 2. Package Type
Table 1. Electrical Specifications @ -40°C ≤ T ≤ 85°C and 3.0V ≤ VDD ≤ 3.6V
8500 MHz
100 MHz 21 dB
3000 MHz 33 dB
6000 MHz 20 dB
8500 MHz 15 dB
100 MHz 20 dB
3000 MHz 18 dB
6000 MHz 15 dB
8500 MHz 8 dB
- Guaranteed but not tested
Table 2. Pin Descriptions Figure 3. Pin Layout (Top View)
1 RFC 1 RF common
2 RF1 1 RF port
4 LS Selects the RF1 to RFC path or RF2 to RFC
5 CTRL Unused (See Table 6)
7 RF2 1 RF port
Table 5. Absolute Maximum Ratings Table 4. Operating Ranges periods may reduce reliability. Table 3. Post Radiation Table
devices are immune to latch-up. Table 6. Truth Table
0 X off on RF2 active
1 X on off RF1 active
Figure 24. Evaluation Board Layout environmental conditions being evaluated. with an cumulative board thickness of 62 mils. of 15 mils and gap of 7 mils.
Figure 25. Evaluation Kit Schematic
- ALL TRANSMISION LINES ARE:
2 RF1
3 VDD
5 CTRL
6 VSS
Figure 26. Package Drawing
Figure 27. Top Marking Specification (Customer Notification Form). liability for the use of this information. Use shall be entirely at the user’s own risk. failure of the Peregrine product could create a situation in which personal injury or death might occur. of the use of its products in such applications. are the property of their respective companies. For sales and contact information please visit www.psemi.com. Table 7. Ordering Information