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3.0 GHz operation ÷10/11 dual modulus prescaler Internal phase detector Serial, parallel or hardwired programmable Ultra-low phase noise Available in 44-lead CQFJ Figure 1. Block Diagram
Table 1. Pin Descriptions (continued) Sdata Serial Input Binary serial data input. Input data entered MSB first. D5 Parallel Input Parallel data bus bit5. M5 Direct Input M Counter bit5. 8-bit enhancement register (E_WR “high”) on the rising edge of Sclk. D6 Parallel Input Parallel data bus bit6. M6 Direct Input M Counter bit6. programming of internal counters while in Serial Interface Mode. D7 Parallel Input Parallel data bus bit7 (MSB). Pre_en Direct Input Prescaler enable, active “low”. When “high”, Fin bypasses the prescaler. programming of internal counters while in Parallel Interface Mode. A0 Direct Input A Counter bit0 (LSB). the enhancement register on the rising edge of Sclk. A1 Direct Input A Counter bit1. A2 Direct Input A Counter bit2. A3 Direct Input A Counter bit3 (MSB). 22 Bmode ALL Input Selects direct interface mode (Bmode=1). 23 VDD ALL (Note 1) Same as pin 1.
26 Hop_WR Serial,
27 Fin ALL Input Prescaler input from the VCO. 3.0 GHz max frequency. this pin and be connected in series with a 50 Ω resistor directly to the ground plane.
Note 1: All V DD pins are connected by diodes and must be supplied with the same positive voltage level. Note 2: All digital input pins have 70 k Ω pull-down resistors to ground. register programming or by floating or grounding VDD pin 31. 31 VDD-fp ALL (Note 1) VDD for fp. Can be left floating or connected to GND to disable the fp output.
32 Dout Serial,
enhancement register programming. 33 VDD ALL (Note 1) Same as pin 1.
34 Cext ALL Output
Logical “NAND” of PD_U and PD_D terminated through an on chip, 2 kΩ series resistor. 35 VDD ALL (Note 1) Same as pin 1. 36 PD_D ALL Output PD_D is pulse down when fp leads fc. 37 PD_U ALL PD_U is pulse down when fc leads fp. 38 VDD-fc ALL (Note 1) VDD for fc can be left floating or connected to GND to disable the fc output. enhancement register programming or by floating or grounding VDD pin 38. 42 fr ALL Input Reference frequency input. impedance, otherwise LD is a logic low (“0”).
44 Enh Serial,
Input Enhancement mode. When asserted low (“0”), enhancement register bits are functional.
Table 2. Absolute Maximum Ratings Table 4. ESD Ratings exceeding the specified rating in Table 4. devices are immune to latch-up. Table 3. Operating Ratings Table 5. DC Characteristics: VDD = 3.0 V, -55° C ≤ TA ≤ 125° C, unless otherwise specified
Table 6. AC Characteristics: VDD = 3.0 V, -55° C ≤ TA ≤ 125° C, unless otherwise specified Note 1: Parameter is guaranteed through char acterization only and is not tested. noise amplifier to square up the edges is recommended at lower input frequencies. part of qualification testing. These parameter s are also exempt from PDA requirements. Note 5: Parameter is tested using 100pF load capacitance and is guaranteed through characterization only. Typical test delay is 12nS.
generates up and down frequency control signals. Figure 4. Functional Block Diagram
and powers down the prescaler. a minimum M Counter divide ratio of “2”. and M8 are internally forced low. R5 are internally forced low (“0”). Bmode input “low” and the Smode input “low”. secondary register contents are utilized. Figure 5. This data provides control bits as enabled by asserting the Enh input “low”. Bmode input “low” and the Smode input “high”. as shown in Table 7 on page 9. secondary register contents are utilized.
asserting the Enh input “low”. R4 and R5 are internally forced low (“0”). Table 7. Primary Register Programming Table 8. Enhancement Register Programming *Serial data clocked serially on Sclk rising edge while E_WR “low” and captured in secondary register on S_WR rising edge. *Serial data clocked serially on Sclk rising edge while E_WR “high” and captured in the double buffer on E_WR falling edge.
inverting comparator with an open drain output. Thus LD is an “AND” function of PD_U and PD_D. The functions of the enhancement register bits are shown below with all bits active “high”. Table 9. Enhancement Register Bit Functionality counter (fc). It has two outputs, PD_U, and PD_D. which numerically yields 0.43 V / radian. Bit 3 Power down Power down of all functions except programming interface. Bit 5 MSEL output Drives the intern al dual modulus prescaler modulus select (MSEL) onto the Dout output. Bit 6 Prescaler output Drives the raw internal prescaler output onto the Dout output. Bit 7 fp, fc OE fp, fc outputs disabled.
Figure 7. Package Drawing Table 10. Ordering Information specifications for product development. Specifications and features may change in any manner without notice. of this information. Use shall be entirely at the user’s own risk. No patent rights or licenses to any circuits described in this datasheet are implied or granted to any third party. are trademarks of Peregrine Semiconductor Corp. For sales and contact information please visit www.psemi.com.