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Features

 Open reflective architecture  Very low on-resistance of 1.2Ω  Low insertion loss  0.20 dB @ 900 MHz  0.40 dB @ 1900 MHz High power handling: 38 dBm (50Ω) Wide power supply range (2.3V to 4.8V) High ESD tolerance of 2 kV HBM on all pins Applications include:  Open and closed-loop tunable antennas for 2G/3G/4G  Tunable matching networks  Tunable filter networks  Bypassing applications  RFID readers DOC-53244

Table 1. Electrical Specifications @ 25°C, VDD = 2.75V Notes: 1. Assumes optimal matching with 1.5 nH inductor in series with each RF port.

  1. Open reflective architecture for flexible configuration of switch in tuning application.
  2. Pulsed RF input with 4620 µs period, 50 % duty cycle, measured per 3GPP TS 45.005.
  3. Power handling in the OFF state reduced due to highly reflective load condition.

DOC-11414-5 │ www.psemi.com ©2013–2014 Peregrine Semiconductor Corp. All rights reserved. Table 4. Operating Ranges

100 MHz–3 GHz

Figure 3. Pin Configuration (Top View) Table 2. Pin Descriptions to the limits in the Operating Ranges table. Table 5. Absolute Maximum Ratings devices are immune to latch-up. exceeding the specified rating. Notes: 1. Between all RF ports, and from RF ports to GND.

  1. Pulsed RF input duty cycle of 50% and 4620 µs, measured per 3GPP
  2. RF input power of 38 dBm (50 Ω, SWON) and 32 dBm (50Ω, SWOFF).

optimal RF performance, or used individually (leave unused pin floating).

  1. For optimal performance, recommend tying Pins 3, 5, 6, 10, 11 together

1 RF– Negative RF Port 1

2 RF– Negative RF Port 1

3 GND Ground 2

4 V DD Power Supply Pin

5 GND Ground 2

6 GND Ground 2

7 V1 Switch control input, CMOS logic level

8 RF+ Positive RF Port 1

9 RF+ Positive RF Port 1

10 GND Ground 2

11 GND Exposed Ground Paddle 2

Table 3. Truth Table Note: * Human Body Model (MIL_STD 883 Method 3015.7).

Resistance (ESR) of the switch core. package parasitics from RF ports to GND. Figure 4. Equivalent Circuit Model Schematic Table 6. Equivalent Circuit Model Parameters

DOC-11414-5 │ www.psemi.com ©2013–2014 Peregrine Semiconductor Corp. All rights reserved. Figure 5. Evaluation Board Evaluation Board transmission line loss for scalar de-embedding. thickness of this board is 62 mils (1.57 mm). and a metal thickness of 1.4 mils (0.051 mm).

Figure 6. Evaluation Board Schematic

14 PIN HEADER

1 RF-

2 RF-

10 RFGND

4 VDD

5 SCL

3 DGND

Note: Use PRT-08405 PCB part number.

DOC-11414-5 │ www.psemi.com ©2013–2014 Peregrine Semiconductor Corp. All rights reserved.

0.10 C A B

0.60 MAX

Figure 7. Top Marking Specifications the standard Peregrine package marking symbol (P). Figure 6. Package Drawing Notes: 1. Dimensions are in millimeters.

  1. Dimensions and tolerances per ASME Y14.5M, 1994.

Figure 8. Tape and Reel Specifications Table 7. Ordering Information specifications for product development. Specifications and features may change in any manner without notice. of this information. Use shall be entirely at the user’s own risk. No patent rights or licenses to any circuits described in this datasheet are implied or granted to any third party. For sales and contact information please visit www.psemi.com.