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Features

Attenuation: 0.5 dB steps to 31.5 dB Safe attenuation state transitions Monotonicity: 0.5 dB up to 4 GHz High attenuation accuracy  ±(0.10 + 1% x Atten) @ 1 GHz  ±(0.15 + 2% x Atten) @ 2.2 GHz  ±(0.15 + 8% x Atten) @ 4 GHz High linearity: +59 dBm IIP3 Wide power supply range of 2.3–5.5V 1.8V control logic compatible 105 °C operating temperature Programming modes  Direct parallel  Latched parallel  Serial Unique power-up state selection  Pin compatible to PE4302, PE4305 and PE4306 Control Logic Interface Parallel Control Power-Up Control Serial Control RF Input RF Output Switched Attenuator Array Figure 2. Package Type

Table 1. Electrical Specifications @ 25 °C (ZS= ZL = 50Ω), unless otherwise noted

1 MHz–<1 GHz

1 MHz–1 GHz

1 MHz–4 GHz

1950 MHz

Notes: 1. Normal mode: single external positive supply used.

  1. Bypass mode: both external positive supply and external negative supply used.
  2. The input 0.1dB compression point is a linearity figure of merit. Refer to Table 5 for the operating RF input power (50Ω).

Table 2. Pin Descriptions Figure 3. Pin Configuration (Top View)

1 C16 3,5 Attenuation control bit, 16 dB

2 RF1 1 RF1 port (RF input)

3 Data 3 Serial interface data input

4 Clock Serial interface clock input

4 Latch Enable input

7 PUP1 5 Power-up selection bit 1

8 PUP2 Power-up selection bit 2

12 VSS_EXT/

13 P/S Parallel/Serial mode select

14 RF2 1 RF2 port (RF output)

15 C8 Attenuation control bit, 8 dB

16 C4 Attenuation control bit, 4 dB

17 C2 Attenuation control bit, 2 dB

19 C1 Attenuation control bit, 1 dB

Table 4. Absolute Maximum Ratings Table 3. Operating Ranges periods may reduce reliability.

  1. Bypass mode: apply a negative voltage to V SS_EXT (pin 12) to bypass

and disable internal negative voltage generator.

  1. Applies to all pins except pins 1, 5, 7 and 20. Pins 1, 7 and 20 have

an internal pull-down resistor and pin 5 has an internal pull-up resistor.

  1. Pulsed, 5% duty cycle of 4620 µs period, 50 Ω.

blocking capacitors for proper operation if the 0 VDC requirement is met.

  1. Use V SS_EXT (pin 12, refer to Table 3) to bypass and disable internal

enable internal negative voltage generator.

  1. Place a 10 k Ω resistor in series, as close to pin as possible to avoid
  2. This pin has an internal 2 M Ω resistor to internal positive digital supply.
  3. This pin has an internal 200 k Ω resistor to GND.

attenuation state, as shown in Table 5. Characteristics), and switching speed (Table 1). Table 5. Truth Table* Note: * Not all 64 possible combinations of C0.5–C16 are shown in table. brought LOW, data in the shift register is latched. Table 8 (Serial Interface AC Characteristics). settings to be specified as the power-up state. automatically set to one of four possible values. (Power-Up Truth Table, Parallel Mode). Table 6. Parallel PUP Truth Table* and PUP1 and PUP2 are not active.

Figure 26. Evaluation Board Schematic Notes: 1. CAUTION: Contains parts and assemblies susceptible to damage by electrostatic discharge (ESD).

  1. Install shunt connector on JP2, JP3 and JP4.

Figure 29. Tape and Reel Drawing Table 10. Ordering Information specifications for product development. Specifications and features may change in any manner without notice. of this information. Use shall be entirely at the user’s own risk. No patent rights or licenses to any circuits described in this datasheet are implied or granted to any third party. are trademarks of Peregrine Semiconductor Corp. For sales and contact information please visit www.psemi.com.