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©2012-2013 Peregrine Semiconductor Corp. All rights reserved. Table 1. Electrical Specifications Temp = 25°C1, VDD = 2.3V to 5.5V (ZS = ZL = 50Ω)

2 RFX to RFC

  1. High frequency performance can be improved by external matching (see Figure 21 through Figure 26 and Figure 29)

©2012-2013 Peregrine Semiconductor Corp. All rights reserved. Table 5. Absolute Maximum Ratings

  1. MM ESD Voltage (JEDEC JESD22-A115-A)

Table 4. Operating Ranges Figure 3. Pin Configuration (Top View) Table 2. Pin Descriptions

1 GND Ground

2 RF2 1 RF Port 2

3 GND Ground

4 GND Ground

5 RFC

1 RF Common

6 GND Ground

7 GND Ground

8 RF1

1 RF Port 1

9 DGND Digital Ground

10 V1 Switch control input, CMOS logic level

11 LS Logic Select, CMOS logic level

Table 3. Truth Table devices are immune to latch-up. exceeding the specified rating. to the limits in the Operating Ranges table.

©2012-2013 Peregrine Semiconductor Corp. All rights reserved. Page 9 of 13 Document No. DOC-33314-1 | www.psemi.com Evaluation Board Figure 27. Evaluation Board Layout The SPDT switch evaluation board was designed to ease customer evaluation of Peregrine’s PE42422. The RF common port is connected through a 50Ω transmission line via the top SMA connector, J2. RF1 and RF2 ports are connected through 50Ω transmission lines via SMA connectors J1 and J3, respectively. A through 50Ω transmission is available via SMA connectors J4 and J5. This transmission line can be used to estimate the loss of the PCB over the environmental conditions being evaluated. J8 provides DC and digital inputs to the device. The board is constructed of a four metal layer material with a total thickness of 62 mils. The top and bottom RF layers are Rogers RO4350 material with a 10 mil RF core. The middle layers provide ground for the transmission lines. The transmission lines were designed using a coplanar waveguide with ground plane model using a trace width of 22 mils, trace gaps of 7 mils, and metal thickness of 2.1 mils. PRT-29005

©2012-2013 Peregrine Semiconductor Corp. All rights reserved. Figure 28. Evaluation Board Schematic

50 OHM 50 OHM

50 OHM

7 GND

9 DGND

12 VDD

©2012-2013 Peregrine Semiconductor Corp. All rights reserved. Figure 29. Evaluation Board Schematic with Matching

©2012-2013 Peregrine Semiconductor Corp. All rights reserved.

0.10 C A B

0.60 MAX

Figure 30. Package Drawing Figure 31. Top Marking Specifications

©2012-2013 Peregrine Semiconductor Corp. All rights reserved. Figure 32. Tape and Reel Specifications Table 6. Ordering Information specifications for product development. Specifications and features may change in any manner without notice. of this information. Use shall be entirely at the user’s own risk. No patent rights or licenses to any circuits described in this datasheet are implied or granted to any third party. are trademarks of Peregrine Semiconductor Corp. For sales and contact information please visit www.psemi.com.