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Features

 HaRP™ technology enhanced  No gate and phase lag  No drift in insertion loss and phase  Supports +1.8V control logic  High linearity  IIP3 of 65 dBm  High isolation  69 dB @ 1 GHz  62 dB @ 3 GHz  50 dB @ 6 GHz  High ESD tolerance  4kV HBM on RFC  2kV HBM on all other pins Product Description The PE42420 is a HaRP™ technology-enhanced absorptive 50Ω SPDT RF switch developed on the UltraCMOS® process technology. This general purpose switch is comprised of two RF ports and has very high isolation performance. It is ideal for RF and IF transceiver signal switching (signal amplitude adjust), discrete DSA stages, and filter bank switching applications. No blocking capacitors are required if DC voltage is not present on the RF ports. Peregrine’s HaRP™ technology enhancements deliver high linearity and excellent harmonics performance with the economy and integration of conventional CMOS. Figure 2. Package Type

Document No. DOC-14514-2 │ UltraCMOS® RFIC Solutions ©2010-2013 Peregrine Semiconductor Corp. All rights reserved. Table 1. Electrical Specifications Typical @ 25°C, VDD = 3.0V (ZS = ZL = 50Ω )

  1. The input 1dB compression point is a linearity figure of merit. Refer to Table 3 for the maximum operating power PIN (50Ω)

2 RFC–RFX 100–6000 MHz 33 dBm

3 RF11 RF port

8 RFC1 RF common

13 RF21 RF port

16 CTRL2 Digital control logic input 2

17 CTRL1 Digital control logic input 1

20 VDD Supply voltage

Table 2. Pin Descriptions Table 4. Absolute Maximum Ratings Figure 3. Pin Configuration (Top View) Table 3. Operating Ranges

  1. Human Body Model (MIL-STD 883 Method 3015)
  2. Machine Model (JEDEC JESD22-A115)

periods may reduce reliability.

Document No. DOC-14514-2 │ UltraCMOS® RFIC Solutions ©2010-2013 Peregrine Semiconductor Corp. All rights reserved. exceeding the specified rating. devices are immune to latch-up. Table 5. Truth Table

1 N/A 1

target value. Switching time is provided in Table 1.

Document No. DOC-14514-2 │ UltraCMOS® RFIC Solutions ©2010-2013 Peregrine Semiconductor Corp. All rights reserved. and digital inputs to the device. I/O traces are heavily isolated from one another. Figure 19. Evaluation Board Layouts

Figure 20. Evaluation Board Schematic

50 OHM T-Line

7 GND

2 GND

3 RF1

4 GND

5 GND

6 GND

1 GND

8 RFC

9 GND

10 GND

specifications for product development. Specifications and features may change in any manner without notice. of this information. Use shall be entirely at the user’s own risk. No patent rights or licenses to any circuits described in this datasheet are implied or granted to any third party. are trademarks of Peregrine Semiconductor Corp. For sales and contact information please visit www.psemi.com.

  1. Camber not to exceed 1 mm in 100 mm
  2. Ao and Bo measured as indicated
  3. Ko measured from a plane on the inside bottom of
  4. Pocket position relative to sprocket hole measured as

Figure 23. Tape and Reel Drawing Table 6. Ordering Information