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Technical content

Features

 AEC-Q100 Grade 2 certified  Supports operating temperature up to +105°C  Single-pin or complementary CMOS logic control inputs  Low insertion loss  0.35 dB @ 1000 MHz  0.50 dB @ 2000 MHz  Isolation of 30 dB @ 1000 MHz  High ESD tolerance of 2kV HBM  Typical input 1 dB compression point of +33.5 dBm  1.8V minimum power supply voltage  Small SC-70 package Figure 2. Package Type

  1. High frequency performance can be improved by external matching (see Figure 20 through Figure 25 and Figure 28)
  2. The DC transient at the output of any po rt of the switch when the control voltage is switched from Low to High or High to Low in a 50Ω test set-up, measured

Table 1. Electrical Specifications @ +25°C, VDD = 3.0V (ZS = ZL = 50Ω )

Table 2. Pin Descriptions exceeding the specified rating. Figure 3. Pin Configuration (Top View)

1 RF1 1 RF Port1

2 GND

3 RF2 1 RF Port2

4 CTRL Switch control input, CMOS logic level.

5 RFC 1 RF Common

6 CTRL or VDD

supply connection is required. pin is not required in this mode. Table 4. Absolute Maximum Ratings

1 Input power (50Ω) see

Table 3. Operating Ranges Figure 4. Maximum Power Handling periods may reduce reliability. PE42359 in the SC70 package is MSL1.

  1. Human Body Model (MIL_STD 883 Method 3015)
  2. Charged Device Model (JEDEC JESD22-C101)

Table 5. Single-pin Control Logic Truth Table Table 6. Complementary-pin Control Logic devices are immune to latch-up.

transmission line via the top SMA connector, J1. Figure 26. Evaluation Board Layouts

Figure 27. Evaluation Board Schematic have exactly the same electrical length.

Figure 28. Evaluation Board Schematic with Matching have exactly the same electrical length.

50 OHM

0.50 MIN

0.40 MIN

0.10 A B

Figure 29. Package Drawing Figure 30. Top Marking Specification

Figure 31. Tape and Reel Specifications Table 7. Ordering Information specifications for product development. Specifications and features may change in any manner without notice. of this information. Use shall be entirely at the user’s own risk. No patent rights or licenses to any circuits described in this datasheet are implied or granted to any third party. are trademarks of Peregrine Semiconductor Corp. For sales and contact information please visit www.psemi.com.